@ -15,7 +15,6 @@
# define CONFIG_SYS_DCSR_COP_CCP_ADDR (CONFIG_SYS_DCSRBAR + 0x02008040)
# define CONFIG_SYS_DCSR_COP_CCP_ADDR (CONFIG_SYS_DCSRBAR + 0x02008040)
# define CONFIG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000)
# define CONFIG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000)
# define CONFIG_SYS_CCI400_ADDR (CONFIG_SYS_IMMR + 0x00180000)
# define CONFIG_SYS_GIC400_ADDR (CONFIG_SYS_IMMR + 0x00400000)
# define CONFIG_SYS_GIC400_ADDR (CONFIG_SYS_IMMR + 0x00400000)
# define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x00530000)
# define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x00530000)
# define SYS_FSL_QSPI_ADDR (CONFIG_SYS_IMMR + 0x00550000)
# define SYS_FSL_QSPI_ADDR (CONFIG_SYS_IMMR + 0x00550000)
@ -544,54 +543,6 @@ struct ccsr_serdes {
u8 res_19a0 [ 0x2000 - 0x19a0 ] ; /* from 0x19a0 to 0x1fff */
u8 res_19a0 [ 0x2000 - 0x19a0 ] ; /* from 0x19a0 to 0x1fff */
} ;
} ;
# define CCI400_CTRLORD_TERM_BARRIER 0x00000008
# define CCI400_CTRLORD_EN_BARRIER 0
# define CCI400_SHAORD_NON_SHAREABLE 0x00000002
# define CCI400_DVM_MESSAGE_REQ_EN 0x00000002
# define CCI400_SNOOP_REQ_EN 0x00000001
/* CCI-400 registers */
struct ccsr_cci400 {
u32 ctrl_ord ; /* Control Override */
u32 spec_ctrl ; /* Speculation Control */
u32 secure_access ; /* Secure Access */
u32 status ; /* Status */
u32 impr_err ; /* Imprecise Error */
u8 res_14 [ 0x100 - 0x14 ] ;
u32 pmcr ; /* Performance Monitor Control */
u8 res_104 [ 0xfd0 - 0x104 ] ;
u32 pid [ 8 ] ; /* Peripheral ID */
u32 cid [ 4 ] ; /* Component ID */
struct {
u32 snoop_ctrl ; /* Snoop Control */
u32 sha_ord ; /* Shareable Override */
u8 res_1008 [ 0x1100 - 0x1008 ] ;
u32 rc_qos_ord ; /* read channel QoS Value Override */
u32 wc_qos_ord ; /* read channel QoS Value Override */
u8 res_1108 [ 0x110c - 0x1108 ] ;
u32 qos_ctrl ; /* QoS Control */
u32 max_ot ; /* Max OT */
u8 res_1114 [ 0x1130 - 0x1114 ] ;
u32 target_lat ; /* Target Latency */
u32 latency_regu ; /* Latency Regulation */
u32 qos_range ; /* QoS Range */
u8 res_113c [ 0x2000 - 0x113c ] ;
} slave [ 5 ] ; /* Slave Interface */
u8 res_6000 [ 0x9004 - 0x6000 ] ;
u32 cycle_counter ; /* Cycle counter */
u32 count_ctrl ; /* Count Control */
u32 overflow_status ; /* Overflow Flag Status */
u8 res_9010 [ 0xa000 - 0x9010 ] ;
struct {
u32 event_select ; /* Event Select */
u32 event_count ; /* Event Count */
u32 counter_ctrl ; /* Counter Control */
u32 overflow_status ; /* Overflow Flag Status */
u8 res_a010 [ 0xb000 - 0xa010 ] ;
} pcounter [ 4 ] ; /* Performance Counter */
u8 res_e004 [ 0x10000 - 0xe004 ] ;
} ;
/* MMU 500 */
/* MMU 500 */
# define SMMU_SCR0 (SMMU_BASE + 0x0)
# define SMMU_SCR0 (SMMU_BASE + 0x0)
# define SMMU_SCR1 (SMMU_BASE + 0x4)
# define SMMU_SCR1 (SMMU_BASE + 0x4)