* Implement adaptive SDRAM timing configuration based on actual CPU

clock frequency for INCA-IP; fix problem with board hanging when
  switching from 150MHz to 100MHz

* Add PCMCIA CS support for BMS2003 board

CHANGELOG

@@ -2,6 +2,12 @@
 Changes since U-Boot 1.0.1:
 ======================================================================
 
+* Implement adaptive SDRAM timing configuration based on actual CPU
+  clock frequency for INCA-IP; fix problem with board hanging when
+  switching from 150MHz to 100MHz
+
+* Add PCMCIA CS support for BMS2003 board
+
 * Add variable CPU clock for MPC859/866 systems (so far only TQM866M):
   see doc/README.MPC866 for details;
   implement workaround for "SIU4" and "SIU9" silicon bugs on MPC866;

board/incaip/memsetup.S

@@ -174,63 +174,120 @@ cgu_init:
 	.end	cgu_init
 
 
-	.globl	memsetup
+/*
-	.ent	memsetup
+ * void sdram_init(long)
-memsetup:
+ *
-
+ * a0 has the clock value
-	/* EBU and CGU Initialization.
  */
-	li	a0, CPU_CLOCK_RATE
+	.globl	sdram_init
-	move	t0, ra
+	.ent	sdram_init
+sdram_init:
 
-	/* We rely on the fact that neither ebu_init() nor cgu_init()
+	li	t1, MC_MODUL_BASE
-	 * modify t0 and a0.
+
-	 */
+	/* Disable memory controller before changing any of its registers */
-	bal	ebu_init
+	sw	zero, MC_CTRLENA(t1)
+
+	li	t2, 100000000
+	beq	a0, t2, 1f
 	nop
-	bal	cgu_init
+	li	t2, 133000000
+	beq	a0, t2, 2f
+	nop
+	li	t2, 150000000
+	beq	a0, t2, 3f
+	nop
+	b	5f
 	nop
-	move	ra, t0
 
-	/* SDRAM Initialization.
+	/* 100 MHz clock */
-	 */
+1:
-	li	t0, MC_MODUL_BASE
+	/* Set clock ratio (clkrat=1:1, rddel=3) */
+	li	t2, 0x00000003
+	sw	t2, MC_IOGP(t1)
 
-	/* Clear Error log registers */
+	/* Set sdram refresh rate (4K/64ms @ 100MHz) */
-	sw	zero, MC_ERRCAUSE(t0)
+	li	t2, 0x0000061A
-	sw	zero, MC_ERRADDR(t0)
+	b	4f
+	sw	t2, MC_TREFRESH(t1)
+
+	/* 133 MHz clock */
+2:
+	/* Set clock ratio (clkrat=1:1, rddel=3) */
+	li	t2, 0x00000003
+	sw	t2, MC_IOGP(t1)
+
+	/* Set sdram refresh rate (4K/64ms @ 133MHz) */
+	li	t2, 0x00000822
+	b	4f
+	sw	t2, MC_TREFRESH(t1)
+
+	/* 150 MHz clock */
+3:
+	/* Set clock ratio (clkrat=3:2, rddel=4) */
+	li	t2, 0x00000014
+	sw	t2, MC_IOGP(t1)
+
+	/* Set sdram refresh rate (4K/64ms @ 150MHz) */
+	li	t2, 0x00000927
+	sw	t2, MC_TREFRESH(t1)
 
-	/* Set clock ratio to 1:1 */
+4:
-	li	t1, 0x03		/* clkrat=1:1, rddel=3 */
+	/* Clear Error log registers */
-	sw	t1, MC_IOGP(t0)
+	sw	zero, MC_ERRCAUSE(t1)
+	sw	zero, MC_ERRADDR(t1)
 
 	/* Clear Power-down registers */
-	sw	zero, MC_SELFRFSH(t0)
+	sw	zero, MC_SELFRFSH(t1)
 
 	/* Set CAS Latency */
-	li	t1, 0x00000020		/* CL = 2 */
+	li	t2, 0x00000020		/* CL = 2 */
-	sw	t1, MC_MRSCODE(t0)
+	sw	t2, MC_MRSCODE(t1)
 
 	/* Set word width to 16 bit */
-	li	t1, 0x2
+	li	t2, 0x2
-	sw	t1, MC_CFGDW(t0)
+	sw	t2, MC_CFGDW(t1)
 
 	/* Set CS0 to SDRAM parameters */
-	li	t1, 0x000014C9
+	li	t2, 0x000014C9
-	sw	t1, MC_CFGPB0(t0)
+	sw	t2, MC_CFGPB0(t1)
 
 	/* Set SDRAM latency parameters */
-	li	t1, 0x00026325		/* BC PC100 */
+	li	t2, 0x00026325		/* BC PC100 */
-	sw	t1, MC_LATENCY(t0)
+	sw	t2, MC_LATENCY(t1)
-
-	/* Set SDRAM refresh rate */
-	li	t1, 0x00000C30		/* 4K/64ms @ 100MHz */
-	sw	t1, MC_TREFRESH(t0)
 
+5:
 	/* Finally enable the controller */
-	li	t1, 1
+	li	t2, 0x00000001
-	sw	t1, MC_CTRLENA(t0)
+	sw	t2, MC_CTRLENA(t1)
 
 	j	ra
 	nop
+
+	.end	sdram_init
+
+
+	.globl	memsetup
+	.ent	memsetup
+memsetup:
+
+	/* EBU, CGU and SDRAM Initialization.
+	 */
+	li	a0, CPU_CLOCK_RATE
+	move	t0, ra
+
+	/* We rely on the fact that neither ebu_init() nor cgu_init() nor sdram_init()
+	 * modify t0 and a0.
+	 */
+	bal	cgu_init
+	nop
+	bal	ebu_init
+	nop
+	bal	sdram_init
+	nop
+	move	ra, t0
+
+	j	ra
+	nop
+
 	.end	memsetup

cpu/mips/incaip_clock.c

@@ -101,13 +101,15 @@ int incaip_set_cpuclk (void)
 {
 	extern void ebu_init(long);
 	extern void cgu_init(long);
+	extern void sdram_init(long);
 	uchar tmp[64];
 	ulong cpuclk;
 
 	if (getenv_r ("cpuclk", tmp, sizeof (tmp)) > 0) {
 		cpuclk = simple_strtoul (tmp, NULL, 10) * 1000000;
-		ebu_init (cpuclk);
 		cgu_init (cpuclk);
+		ebu_init (cpuclk);
+		sdram_init (cpuclk);
 	}
 
 	return 0;

doc/README.MPC866

@@ -0,0 +1,19 @@
+The current implementation allows the user to specify the desired CPU
+clock value, in MHz, via an environment variable "cpuclk".
+
+Three compile-time constants are used:
+
+	CFG_866_OSCCLK            - input quartz clock
+	CFG_866_CPUCLK_MIN        - minimum allowed CPU clock
+	CFG_866_CPUCLK_MAX        - maximum allowed CPU clock
+	CFG_866_CPUCLK_DEFAULT    - default CPU clock value
+
+If the "cpuclk" environment variable value is within the CPUCLK_MIN /
+CPUCLK_MAX limits, the specified value is used. Otherwise, the
+default CPU clock value is set.
+
+Please note that for now the new clock-handling code has been enabled
+for the TQM866M board only, even though it should be pretty much
+common for other MPC859 / MPC866 based boards also. Our intention
+here was to move in small steps and not to break the existing code
+for other boards.

include/configs/TQM866M.h

@@ -37,15 +37,13 @@
 #define CONFIG_TQM866M		1	/* ...on a TQM8xxM module	*/
 
 #define CFG_866_OSCCLK		 10000000	/*  10 MHz - PLL input clock		*/
-#define CFG_866_CPUCLK_MIN	40000000	/*  40 MHz - CPU minimum clock		*/
+#define CFG_866_CPUCLK_MIN	 10000000	/*  10 MHz - CPU minimum clock		*/
 #define CFG_866_CPUCLK_MAX	133000000	/* 133 MHz - CPU maximum clock		*/
-#define CFG_866_CPUCLK_DEFAULT	100000000	/* 100 MHz - CPU default clock		*/
+#define CFG_866_CPUCLK_DEFAULT	 50000000	/*  50 MHz - CPU default clock		*/
 						/* (it will be used if there is no	*/
 						/* 'cpuclk' variable with valid value)	*/
 
 #define CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/
-#undef	CONFIG_8xx_CONS_SMC2
-#undef	CONFIG_8xx_CONS_NONE
 
 #define CONFIG_BAUDRATE		115200	/* console baudrate = 115kbps	*/
 

include/configs/bms2003.h

@@ -346,6 +346,7 @@
 #define CFG_PCMCIA_ATTRB_SIZE	( 64 << 20 )
 #define CFG_PCMCIA_IO_ADDR	(0xEC100000)
 #define CFG_PCMCIA_IO_SIZE	( 64 << 20 )
+#define PCMCIA_MEM_WIN_NO	5
 #define NSCU_OE_INV		1		/* PCMCIA_GCRX_CXOE is inverted */
 #endif