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powerpc:Rename CONFIG_PBLRCW_CONFIG & CONFIG_SYS_FSL_PBL_PBI

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Rename CONFIG_PBLRCW_CONFIG and CONFIG_PBLRCW_CONFIG.

Also add their details in README.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
master
Prabhakar Kushwaha 11 years ago committed by York Sun
parent 3fdc827ca8
commit 690e425844
9 changed files with 33 additions and 19 deletions
Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL
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  1. 4
      Makefile
  2. 9
      README
  3. 4
      include/configs/B4860QDS.h
  4. 5
      include/configs/P2041RDB.h
  5. 4
      include/configs/T1040QDS.h
  6. 4
      include/configs/T2080QDS.h
  7. 4
      include/configs/T4240QDS.h
  8. 14
      include/configs/corenet_ds.h
  9. 4
      include/configs/km/kmp204x-common.h

4
Makefile
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@ -419,8 +419,8 @@ $(obj)u-boot.kwb: $(obj)u-boot.bin
-a $(CONFIG_SYS_TEXT_BASE) -e $(CONFIG_SYS_TEXT_BASE) -d $< $@ -a $(CONFIG_SYS_TEXT_BASE) -e $(CONFIG_SYS_TEXT_BASE) -d $< $@
$(obj)u-boot.pbl: $(obj)u-boot.bin $(obj)u-boot.pbl: $(obj)u-boot.bin
$(obj)tools/mkimage -n $(CONFIG_PBLRCW_CONFIG) \ $(obj)tools/mkimage -n $(CONFIG_SYS_FSL_PBL_RCW) \
-R $(CONFIG_PBLPBI_CONFIG) -T pblimage \ -R $(CONFIG_SYS_FSL_PBL_PBI) -T pblimage \
-d $< $@ -d $< $@
$(obj)u-boot.sha1: $(obj)u-boot.bin $(obj)u-boot.sha1: $(obj)u-boot.bin

9
README
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@ -472,6 +472,15 @@ The following options need to be configured:
Board config to use DDR3. It can be enabled for SoCs with Board config to use DDR3. It can be enabled for SoCs with
Freescale DDR3 controllers. Freescale DDR3 controllers.
CONFIG_SYS_FSL_PBL_PBI
It enables addition of RCW (Power on reset configuration) in built image.
Please refer doc/README.pblimage for more details
CONFIG_SYS_FSL_PBL_RCW
It adds PBI(pre-boot instructions) commands in u-boot build image.
PBI commands can be used to configure SoC before it starts the execution.
Please refer doc/README.pblimage for more details
- Intel Monahans options: - Intel Monahans options:
CONFIG_SYS_MONAHANS_RUN_MODE_OSC_RATIO CONFIG_SYS_MONAHANS_RUN_MODE_OSC_RATIO

4
include/configs/B4860QDS.h
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@ -16,8 +16,8 @@
#ifdef CONFIG_RAMBOOT_PBL #ifdef CONFIG_RAMBOOT_PBL
#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
#define CONFIG_PBLPBI_CONFIG $(SRCTREE)/board/freescale/b4860qds/b4_pbi.cfg #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/b4860qds/b4_pbi.cfg
#define CONFIG_PBLRCW_CONFIG $(SRCTREE)/board/freescale/b4860qds/b4_rcw.cfg #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/b4860qds/b4_rcw.cfg
#endif #endif
#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE

5
include/configs/P2041RDB.h
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@ -18,8 +18,9 @@
#ifdef CONFIG_RAMBOOT_PBL #ifdef CONFIG_RAMBOOT_PBL
#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
#define CONFIG_PBLPBI_CONFIG $(SRCTREE)/board/freescale/corenet_ds/pbi.cfg #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/corenet_ds/pbi.cfg
#define CONFIG_PBLRCW_CONFIG $(SRCTREE)/board/freescale/corenet_ds/rcw_p2041rdb.cfg #define CONFIG_SYS_FSL_PBL_RCW \
$(SRCTREE)/board/freescale/corenet_ds/rcw_p2041rdb.cfg
#endif #endif
#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE

4
include/configs/T1040QDS.h
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@ -32,8 +32,8 @@
#ifdef CONFIG_RAMBOOT_PBL #ifdef CONFIG_RAMBOOT_PBL
#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
#define CONFIG_PBLPBI_CONFIG $(SRCTREE)/board/freescale/t1040qds/t1040_pbi.cfg #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t1040qds/t1040_pbi.cfg
#define CONFIG_PBLRCW_CONFIG $(SRCTREE)/board/freescale/t1040qds/t1040_rcw.cfg #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t1040qds/t1040_rcw.cfg
#endif #endif
/* High Level Configuration Options */ /* High Level Configuration Options */

4
include/configs/T2080QDS.h
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@ -45,8 +45,8 @@
#ifdef CONFIG_RAMBOOT_PBL #ifdef CONFIG_RAMBOOT_PBL
#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
#define CONFIG_PBLPBI_CONFIG $(SRCTREE)/board/freescale/t2080qds/t2080_pbi.cfg #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t2080qds/t2080_pbi.cfg
#define CONFIG_PBLRCW_CONFIG $(SRCTREE)/board/freescale/t2080qds/t2080_rcw.cfg #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t2080qds/t2080_rcw.cfg
#endif #endif
#define CONFIG_SRIO_PCIE_BOOT_MASTER #define CONFIG_SRIO_PCIE_BOOT_MASTER

4
include/configs/T4240QDS.h
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@ -21,8 +21,8 @@
#ifdef CONFIG_RAMBOOT_PBL #ifdef CONFIG_RAMBOOT_PBL
#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
#define CONFIG_PBLPBI_CONFIG $(SRCTREE)/board/freescale/t4qds/t4_pbi.cfg #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t4qds/t4_pbi.cfg
#define CONFIG_PBLRCW_CONFIG $(SRCTREE)/board/freescale/t4qds/t4_rcw.cfg #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t4qds/t4_rcw.cfg
#endif #endif
#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE

14
include/configs/corenet_ds.h
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@ -15,15 +15,19 @@
#ifdef CONFIG_RAMBOOT_PBL #ifdef CONFIG_RAMBOOT_PBL
#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
#define CONFIG_PBLPBI_CONFIG $(SRCTREE)/board/freescale/corenet_ds/pbi.cfg #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/corenet_ds/pbi.cfg
#if defined(CONFIG_P3041DS) #if defined(CONFIG_P3041DS)
#define CONFIG_PBLRCW_CONFIG $(SRCTREE)/board/freescale/corenet_ds/rcw_p3041ds.cfg #define CONFIG_SYS_FSL_PBL_RCW \
$(SRCTREE)/board/freescale/corenet_ds/rcw_p3041ds.cfg
#elif defined(CONFIG_P4080DS) #elif defined(CONFIG_P4080DS)
#define CONFIG_PBLRCW_CONFIG $(SRCTREE)/board/freescale/corenet_ds/rcw_p4080ds.cfg #define CONFIG_SYS_FSL_PBL_RCW \
$(SRCTREE)/board/freescale/corenet_ds/rcw_p4080ds.cfg
#elif defined(CONFIG_P5020DS) #elif defined(CONFIG_P5020DS)
#define CONFIG_PBLRCW_CONFIG $(SRCTREE)/board/freescale/corenet_ds/rcw_p5020ds.cfg #define CONFIG_SYS_FSL_PBL_RCW \
$(SRCTREE)/board/freescale/corenet_ds/rcw_p5020ds.cfg
#elif defined(CONFIG_P5040DS) #elif defined(CONFIG_P5040DS)
#define CONFIG_PBLRCW_CONFIG $(SRCTREE)/board/freescale/corenet_ds/rcw_p5040ds.cfg #define CONFIG_SYS_FSL_PBL_RCW \
$(SRCTREE)/board/freescale/corenet_ds/rcw_p5040ds.cfg
#endif #endif
#endif #endif

4
include/configs/km/kmp204x-common.h
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@ -24,8 +24,8 @@
#define CONFIG_RAMBOOT_PBL #define CONFIG_RAMBOOT_PBL
#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
#define CONFIG_PBLPBI_CONFIG $(SRCTREE)/board/keymile/kmp204x/pbi.cfg #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/keymile/kmp204x/pbi.cfg
#define CONFIG_PBLRCW_CONFIG $(SRCTREE)/board/keymile/kmp204x/rcw_kmp204x.cfg #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/keymile/kmp204x/rcw_kmp204x.cfg
/* High Level Configuration Options */ /* High Level Configuration Options */
#define CONFIG_BOOKE #define CONFIG_BOOKE

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