Remove edb9301, edb9302, edb9302a, edb9307, edb9307a, edb9312, edb9315 and edb9315a boards. Signed-off-by: Wolfgang Denk <wd@denx.de>master
Wolfgang Denk
14 years ago
committed by
Albert ARIBAUD
parent
5dcf53696f
commit
716f7ade10
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#
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# (C) Copyright 2003-2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk |
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LIB = $(obj)lib$(BOARD).o
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COBJS := edb93xx.o flash_cfg.o pll_cfg.o sdram_cfg.o
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS))
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SOBJS := $(addprefix $(obj),$(SOBJS))
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$(LIB): $(obj).depend $(OBJS) $(SOBJS) |
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$(call cmd_link_o_target, $(OBJS) $(SOBJS))
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clean: |
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rm -f $(SOBJS) $(OBJS)
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distclean: clean |
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rm -f $(LIB) core *.bak .depend
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#########################################################################
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk |
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sinclude $(obj).depend |
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#########################################################################
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@ -1,33 +0,0 @@ |
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LDSCRIPT := $(SRCTREE)/arch/arm/cpu/arm920t/ep93xx/u-boot.lds
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ifdef CONFIG_EDB9301 |
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CONFIG_SYS_TEXT_BASE = 0x05700000
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endif |
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ifdef CONFIG_EDB9302 |
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CONFIG_SYS_TEXT_BASE = 0x05700000
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endif |
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ifdef CONFIG_EDB9302A |
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CONFIG_SYS_TEXT_BASE = 0xc5700000
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endif |
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ifdef CONFIG_EDB9307 |
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CONFIG_SYS_TEXT_BASE = 0x01f00000
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endif |
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ifdef CONFIG_EDB9307A |
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CONFIG_SYS_TEXT_BASE = 0xc1f00000
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endif |
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ifdef CONFIG_EDB9312 |
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CONFIG_SYS_TEXT_BASE = 0x01f00000
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endif |
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ifdef CONFIG_EDB9315 |
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CONFIG_SYS_TEXT_BASE = 0x01f00000
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endif |
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ifdef CONFIG_EDB9315A |
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CONFIG_SYS_TEXT_BASE = 0xc1f00000
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endif |
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@ -1,34 +0,0 @@ |
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/*
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* Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net> |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#include <common.h> |
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/* delay execution before timers are initialized */ |
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static inline void early_udelay(uint32_t usecs) |
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{ |
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/* loop takes 4 cycles at 5.0ns (fastest case, running at 200MHz) */ |
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register uint32_t loops = usecs * (1000 / 20); |
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__asm__ volatile ("1:\n" |
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"subs %0, %1, #1\n" |
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"bne 1b":"=r" (loops):"0" (loops)); |
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} |
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@ -1,110 +0,0 @@ |
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/*
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* Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net> |
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* |
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* (C) Copyright 2002 2003 |
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* Network Audio Technologies, Inc. <www.netaudiotech.com> |
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* Adam Bezanson <bezanson@netaudiotech.com> |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#include <common.h> |
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#include <netdev.h> |
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#include <asm/arch/ep93xx.h> |
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#include <asm/io.h> |
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DECLARE_GLOBAL_DATA_PTR; |
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#define MAX_BANK_SIZE 0x04000000 /* 64 MB */ |
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static ulong const bank_addr[CONFIG_NR_DRAM_BANKS] = { |
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PHYS_SDRAM_1, |
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#ifdef PHYS_SDRAM_2 |
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PHYS_SDRAM_2, |
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#endif |
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#ifdef PHYS_SDRAM_3 |
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PHYS_SDRAM_3, |
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#endif |
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#ifdef PHYS_SDRAM_4 |
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PHYS_SDRAM_4 |
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#endif |
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}; |
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int board_init(void) |
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{ |
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struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE; |
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icache_enable(); |
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#ifdef USE_920T_MMU |
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dcache_enable(); |
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#endif |
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/*
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* set UARTBAUD bit to drive UARTs with 14.7456MHz instead of |
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* 14.7456/2 MHz |
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*/ |
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uint32_t value = readl(&syscon->pwrcnt); |
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value |= SYSCON_PWRCNT_UART_BAUD; |
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writel(value, &syscon->pwrcnt); |
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/* Enable the uart in devicecfg */ |
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value = readl(&syscon->devicecfg); |
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value |= 1<<18 /* U1EN */; |
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writel(0xAA, &syscon->sysswlock); |
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writel(value, &syscon->devicecfg); |
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/* Machine number, as defined in linux/arch/arm/tools/mach-types */ |
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gd->bd->bi_arch_number = CONFIG_MACH_TYPE; |
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/* adress of boot parameters */ |
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gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR; |
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/* We have a console */ |
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gd->have_console = 1; |
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return 0; |
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} |
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int board_eth_init(bd_t *bd) |
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{ |
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return ep93xx_eth_initialize(0, MAC_BASE); |
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} |
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int dram_init(void) |
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{ |
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unsigned int *src, *dst; |
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int i; |
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for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { |
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const ulong bank_size = get_ram_size((long *)bank_addr[i], |
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MAX_BANK_SIZE); |
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if (bank_size) { |
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gd->bd->bi_dram[i].start = bank_addr[i]; |
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gd->bd->bi_dram[i].size = bank_size; |
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} |
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} |
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/* copy exception vectors */ |
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src = (unsigned int *)_armboot_start; |
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dst = (unsigned int *)PHYS_SDRAM_1; |
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memcpy(dst, src, 16 * sizeof(unsigned int)); |
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return 0; |
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} |
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@ -1,38 +0,0 @@ |
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/*
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* Flash setup for Cirrus edb93xx boards |
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* |
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* Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net> |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#include <common.h> |
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#include <asm/arch/ep93xx.h> |
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#include <asm/io.h> |
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#define SMC_BCR6_VALUE (2 << SMC_BCR_IDCY_SHIFT | 5 << SMC_BCR_WST1_SHIFT | \ |
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SMC_BCR_BLE | 2 << SMC_BCR_WST2_SHIFT | \
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1 << SMC_BCR_MW_SHIFT) |
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void flash_cfg(void) |
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{ |
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struct smc_regs *smc = (struct smc_regs *)SMC_BASE; |
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writel(SMC_BCR6_VALUE, &smc->bcr6); |
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} |
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@ -1,58 +0,0 @@ |
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/*
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* PLL setup for Cirrus edb93xx boards |
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* |
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* Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net> |
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* |
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* Copyright (C) 2006 Dominic Rath <Dominic.Rath@gmx.de> |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#include <common.h> |
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#include <asm/io.h> |
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#include "pll_cfg.h" |
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#include "early_udelay.h" |
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void pll_cfg(void) |
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{ |
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struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE; |
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/* setup PLL1 */ |
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writel(CLKSET1_VAL, &syscon->clkset1); |
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/*
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* flush the pipeline |
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* writing to CLKSET1 causes the EP93xx to enter standby for between |
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* 8 ms to 16 ms, until PLL1 stabilizes |
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*/ |
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asm("nop"); |
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asm("nop"); |
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asm("nop"); |
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asm("nop"); |
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asm("nop"); |
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/* setup PLL2 */ |
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writel(CLKSET2_VAL, &syscon->clkset2); |
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/*
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* the user's guide recommends to wait at least 1 ms for PLL2 to |
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* stabilize |
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*/ |
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early_udelay(1000); |
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} |
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@ -1,72 +0,0 @@ |
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/*
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* PLL register values for Cirrus edb93xx boards |
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* |
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* Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net> |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#include <config.h> |
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#include <asm/arch/ep93xx.h> |
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#if defined(CONFIG_EDB9301) || defined(CONFIG_EDB9302) || \ |
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defined(CONFIG_EDB9302A) |
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/*
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* fclk_div: 2, nbyp1: 1, hclk_div: 5, pclk_div: 2 |
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* pll1_x1: 294912000.000000, pll1_x2ip: 36864000.000000, |
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* pll1_x2: 331776000.000000, pll1_out: 331776000.000000 |
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*/ |
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#define CLKSET1_VAL (7 << SYSCON_CLKSET_PLL_X2IPD_SHIFT | \ |
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8 << SYSCON_CLKSET_PLL_X2FBD2_SHIFT | \
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19 << SYSCON_CLKSET_PLL_X1FBD1_SHIFT | \
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1 << SYSCON_CLKSET1_PCLK_DIV_SHIFT | \
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3 << SYSCON_CLKSET1_HCLK_DIV_SHIFT | \
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SYSCON_CLKSET1_NBYP1 | \
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1 << SYSCON_CLKSET1_FCLK_DIV_SHIFT) |
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#elif defined(CONFIG_EDB9307) || defined(CONFIG_EDB9307A) || \ |
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defined CONFIG_EDB9312 || defined(CONFIG_EDB9315) || \
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defined(CONFIG_EDB9315A) |
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/*
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* fclk_div: 2, nbyp1: 1, hclk_div: 4, pclk_div: 2 |
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* pll1_x1: 3096576000.000000, pll1_x2ip: 129024000.000000, |
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* pll1_x2: 3999744000.000000, pll1_out: 1999872000.000000 |
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*/ |
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#define CLKSET1_VAL (23 << SYSCON_CLKSET_PLL_X2IPD_SHIFT | \ |
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30 << SYSCON_CLKSET_PLL_X2FBD2_SHIFT | \
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20 << SYSCON_CLKSET_PLL_X1FBD1_SHIFT | \
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1 << SYSCON_CLKSET1_PCLK_DIV_SHIFT | \
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2 << SYSCON_CLKSET1_HCLK_DIV_SHIFT | \
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SYSCON_CLKSET1_NBYP1 | \
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1 << SYSCON_CLKSET1_FCLK_DIV_SHIFT) |
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#else |
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#error "Undefined board" |
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#endif |
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/*
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* usb_div: 4, nbyp2: 1, pll2_en: 1 |
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* pll2_x1: 368640000.000000, pll2_x2ip: 15360000.000000, |
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* pll2_x2: 384000000.000000, pll2_out: 192000000.000000 |
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*/ |
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#define CLKSET2_VAL (23 << SYSCON_CLKSET_PLL_X2IPD_SHIFT | \ |
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24 << SYSCON_CLKSET_PLL_X2FBD2_SHIFT | \
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24 << SYSCON_CLKSET_PLL_X1FBD1_SHIFT | \
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1 << SYSCON_CLKSET_PLL_PS_SHIFT | \
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SYSCON_CLKSET2_PLL2_EN | \
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SYSCON_CLKSET2_NBYP2 | \
|
|
||||||
3 << SYSCON_CLKSET2_USB_DIV_SHIFT) |
|
||||||
@ -1,146 +0,0 @@ |
|||||||
/*
|
|
||||||
* Copyright (C) 2009, 2010 Matthias Kaehlcke <matthias@kaehlcke.net> |
|
||||||
* |
|
||||||
* Copyright (C) 2006 Dominic Rath <Dominic.Rath@gmx.de> |
|
||||||
* |
|
||||||
* See file CREDITS for list of people who contributed to this |
|
||||||
* project. |
|
||||||
* |
|
||||||
* This program is free software; you can redistribute it and/or |
|
||||||
* modify it under the terms of the GNU General Public License as |
|
||||||
* published by the Free Software Foundation; either version 2 of |
|
||||||
* the License, or (at your option) any later version. |
|
||||||
* |
|
||||||
* This program is distributed in the hope that it will be useful, |
|
||||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
||||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
||||||
* GNU General Public License for more details. |
|
||||||
* |
|
||||||
* You should have received a copy of the GNU General Public License |
|
||||||
* along with this program; if not, write to the Free Software |
|
||||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
|
||||||
* MA 02111-1307 USA |
|
||||||
*/ |
|
||||||
|
|
||||||
#include <asm/io.h> |
|
||||||
#include "sdram_cfg.h" |
|
||||||
#include "early_udelay.h" |
|
||||||
|
|
||||||
#define PROGRAM_MODE_REG(bank) (*(volatile uint32_t *) \ |
|
||||||
(SDRAM_BASE_ADDR | SDRAM_BANK_SEL_##bank | SDRAM_MODE_REG_VAL)) |
|
||||||
|
|
||||||
#define PRECHARGE_BANK(bank) (*(volatile uint32_t *) \ |
|
||||||
(SDRAM_BASE_ADDR | SDRAM_BANK_SEL_##bank)) = 0 |
|
||||||
|
|
||||||
static void precharge_all_banks(void); |
|
||||||
static void setup_refresh_timer(void); |
|
||||||
static void program_mode_registers(void); |
|
||||||
|
|
||||||
void sdram_cfg(void) |
|
||||||
{ |
|
||||||
struct sdram_regs *sdram = (struct sdram_regs *)SDRAM_BASE; |
|
||||||
|
|
||||||
writel(SDRAM_DEVCFG_VAL, &sdram->SDRAM_DEVCFG_REG); |
|
||||||
|
|
||||||
/* Issue continous NOP commands */ |
|
||||||
writel(GLCONFIG_INIT | GLCONFIG_MRS | GLCONFIG_CKE, &sdram->glconfig); |
|
||||||
|
|
||||||
early_udelay(200); |
|
||||||
|
|
||||||
precharge_all_banks(); |
|
||||||
|
|
||||||
setup_refresh_timer(); |
|
||||||
|
|
||||||
program_mode_registers(); |
|
||||||
|
|
||||||
/* Select normal operation mode */ |
|
||||||
writel(GLCONFIG_CKE, &sdram->glconfig); |
|
||||||
} |
|
||||||
|
|
||||||
static void precharge_all_banks(void) |
|
||||||
{ |
|
||||||
struct sdram_regs *sdram = (struct sdram_regs *)SDRAM_BASE; |
|
||||||
|
|
||||||
/* Issue PRECHARGE ALL commands */ |
|
||||||
writel(GLCONFIG_INIT | GLCONFIG_CKE, &sdram->glconfig); |
|
||||||
|
|
||||||
/*
|
|
||||||
* Errata of most EP93xx revisions say that PRECHARGE ALL isn't always |
|
||||||
* issued |
|
||||||
* |
|
||||||
* Cirrus proposes a workaround which consists in performing a read from |
|
||||||
* each bank to force the precharge. This causes some boards to hang. |
|
||||||
* Writing to the SDRAM banks instead of reading has the same |
|
||||||
* side-effect (the SDRAM controller issues the necessary precharges), |
|
||||||
* but is known to work on all supported boards |
|
||||||
*/ |
|
||||||
|
|
||||||
PRECHARGE_BANK(0); |
|
||||||
|
|
||||||
#if (CONFIG_NR_DRAM_BANKS >= 2) |
|
||||||
PRECHARGE_BANK(1); |
|
||||||
#endif |
|
||||||
|
|
||||||
#if (CONFIG_NR_DRAM_BANKS >= 3) |
|
||||||
PRECHARGE_BANK(2); |
|
||||||
#endif |
|
||||||
|
|
||||||
#if (CONFIG_NR_DRAM_BANKS == 4) |
|
||||||
PRECHARGE_BANK(3); |
|
||||||
#endif |
|
||||||
} |
|
||||||
|
|
||||||
static void setup_refresh_timer(void) |
|
||||||
{ |
|
||||||
struct sdram_regs *sdram = (struct sdram_regs *)SDRAM_BASE; |
|
||||||
|
|
||||||
/* Load refresh timer with 10 to issue refresh every 10 cycles */ |
|
||||||
writel(0x0a, &sdram->refrshtimr); |
|
||||||
|
|
||||||
/*
|
|
||||||
* Wait at least 80 clock cycles to provide 8 refresh cycles |
|
||||||
* to all SDRAMs |
|
||||||
*/ |
|
||||||
early_udelay(1); |
|
||||||
|
|
||||||
/*
|
|
||||||
* Program refresh timer with normal value |
|
||||||
* We need 8192 refresh cycles every 64ms |
|
||||||
* at 15ns (HCLK >= 66MHz) per cycle: |
|
||||||
* 64ms / 8192 = 7.8125us |
|
||||||
* 7.8125us / 15ns = 520 (0x208) |
|
||||||
*/ |
|
||||||
/*
|
|
||||||
* TODO: redboot uses 0x1e0 for the slowest possible device |
|
||||||
* but i don't understand how this value is calculated |
|
||||||
*/ |
|
||||||
writel(0x208, &sdram->refrshtimr); |
|
||||||
} |
|
||||||
|
|
||||||
static void program_mode_registers(void) |
|
||||||
{ |
|
||||||
struct sdram_regs *sdram = (struct sdram_regs *)SDRAM_BASE; |
|
||||||
|
|
||||||
/* Select mode register update mode */ |
|
||||||
writel(GLCONFIG_MRS | GLCONFIG_CKE, &sdram->glconfig); |
|
||||||
|
|
||||||
/*
|
|
||||||
* The mode registers are programmed by performing a read from each |
|
||||||
* SDRAM bank. The value of the address that is read defines the value |
|
||||||
* that is written into the mode register |
|
||||||
*/ |
|
||||||
|
|
||||||
PROGRAM_MODE_REG(0); |
|
||||||
|
|
||||||
#if (CONFIG_NR_DRAM_BANKS >= 2) |
|
||||||
PROGRAM_MODE_REG(1); |
|
||||||
#endif |
|
||||||
|
|
||||||
#if (CONFIG_NR_DRAM_BANKS >= 3) |
|
||||||
PROGRAM_MODE_REG(2); |
|
||||||
#endif |
|
||||||
|
|
||||||
#if (CONFIG_NR_DRAM_BANKS == 4) |
|
||||||
PROGRAM_MODE_REG(3); |
|
||||||
#endif |
|
||||||
} |
|
||||||
@ -1,144 +0,0 @@ |
|||||||
/*
|
|
||||||
* Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net> |
|
||||||
* |
|
||||||
* Copyright (C) 2006 Dominic Rath <Dominic.Rath@gmx.de> |
|
||||||
* |
|
||||||
* See file CREDITS for list of people who contributed to this |
|
||||||
* project. |
|
||||||
* |
|
||||||
* This program is free software; you can redistribute it and/or |
|
||||||
* modify it under the terms of the GNU General Public License as |
|
||||||
* published by the Free Software Foundation; either version 2 of |
|
||||||
* the License, or (at your option) any later version. |
|
||||||
* |
|
||||||
* This program is distributed in the hope that it will be useful, |
|
||||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
||||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
||||||
* GNU General Public License for more details. |
|
||||||
* |
|
||||||
* You should have received a copy of the GNU General Public License |
|
||||||
* along with this program; if not, write to the Free Software |
|
||||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
|
||||||
* MA 02111-1307 USA |
|
||||||
*/ |
|
||||||
|
|
||||||
#include <config.h> |
|
||||||
#include <asm/arch/ep93xx.h> |
|
||||||
|
|
||||||
#define SDRAM_BASE_ADDR PHYS_SDRAM_1 |
|
||||||
|
|
||||||
#ifdef CONFIG_EDB93XX_SDCS0 |
|
||||||
#define SDRAM_DEVCFG_REG devcfg0 |
|
||||||
#elif defined(CONFIG_EDB93XX_SDCS3) |
|
||||||
#define SDRAM_DEVCFG_REG devcfg3 |
|
||||||
#else |
|
||||||
#error "SDRAM bank configuration" |
|
||||||
#endif |
|
||||||
|
|
||||||
#if defined(CONFIG_EDB9301) || defined(CONFIG_EDB9302) || \ |
|
||||||
defined(CONFIG_EDB9302A) |
|
||||||
/*
|
|
||||||
* 1x Samsung K4S561632C-TC/L75 4M x 16bit x 4 banks SDRAM |
|
||||||
* |
|
||||||
* CLK cycle time min: |
|
||||||
* @ CAS latency = 3: 7.5ns |
|
||||||
* @ CAS latency = 2: 10ns |
|
||||||
* We're running at 66MHz (15ns cycle time) external bus speed (HCLK), |
|
||||||
* so it's safe to use CAS latency = 2 |
|
||||||
* |
|
||||||
* RAS-to-CAS delay min: |
|
||||||
* 20ns |
|
||||||
* At 15ns cycle time, we use RAS-to-CAS delay = 2 |
|
||||||
* |
|
||||||
* SROMLL = 1: Swap BA[1:0] with A[13:12], making the SDRAM appear |
|
||||||
* as four blocks of 8MB size, instead of eight blocks of 4MB size: |
|
||||||
* |
|
||||||
* EDB9301/EDB9302: |
|
||||||
* |
|
||||||
* 0x00000000 - 0x007fffff |
|
||||||
* 0x01000000 - 0x017fffff |
|
||||||
* 0x04000000 - 0x047fffff |
|
||||||
* 0x05000000 - 0x057fffff |
|
||||||
* |
|
||||||
* |
|
||||||
* EDB9302a: |
|
||||||
* |
|
||||||
* 0xc0000000 - 0xc07fffff |
|
||||||
* 0xc1000000 - 0xc17fffff |
|
||||||
* 0xc4000000 - 0xc47fffff |
|
||||||
* 0xc5000000 - 0xc57fffff |
|
||||||
* |
|
||||||
* BANKCOUNT = 1: This is a device with four banks |
|
||||||
*/ |
|
||||||
|
|
||||||
#define SDRAM_DEVCFG_VAL (SDRAM_DEVCFG_BANKCOUNT | \ |
|
||||||
SDRAM_DEVCFG_SROMLL | \
|
|
||||||
SDRAM_DEVCFG_CASLAT_2 | \
|
|
||||||
SDRAM_DEVCFG_RASTOCAS_2 | \
|
|
||||||
SDRAM_DEVCFG_EXTBUSWIDTH) |
|
||||||
|
|
||||||
/*
|
|
||||||
* 16 bit ext. bus |
|
||||||
* |
|
||||||
* A[22:09] is output as SYA[13:0] |
|
||||||
* CAS latency: 2 |
|
||||||
* Burst type: sequential |
|
||||||
* Burst length: 8 (required for 16 bit ext. bus) |
|
||||||
* SYA[13:0] = 0x0023 |
|
||||||
*/ |
|
||||||
#define SDRAM_MODE_REG_VAL 0x4600 |
|
||||||
|
|
||||||
#define SDRAM_BANK_SEL_0 0x00000000 /* A[22:21] = b00 */ |
|
||||||
#define SDRAM_BANK_SEL_1 0x00200000 /* A[22:21] = b01 */ |
|
||||||
#define SDRAM_BANK_SEL_2 0x00400000 /* A[22:21] = b10 */ |
|
||||||
#define SDRAM_BANK_SEL_3 0x00600000 /* A[22:21] = b11 */ |
|
||||||
|
|
||||||
#elif defined(CONFIG_EDB9307) || defined(CONFIG_EDB9307A) || \ |
|
||||||
defined CONFIG_EDB9312 || defined(CONFIG_EDB9315) || \
|
|
||||||
defined(CONFIG_EDB9315A) |
|
||||||
/*
|
|
||||||
* 2x Samsung K4S561632C-TC/L75 4M x 16bit x 4 banks SDRAM |
|
||||||
* |
|
||||||
* CLK cycle time min: |
|
||||||
* @ CAS latency = 3: 7.5ns |
|
||||||
* @ CAS latency = 2: 10ns |
|
||||||
* We're running at 100MHz (10ns cycle time) external bus speed (HCLK), |
|
||||||
* so it's safe to use CAS latency = 2 |
|
||||||
* |
|
||||||
* RAS-to-CAS delay min: |
|
||||||
* 20ns |
|
||||||
* At 10ns cycle time, we use RAS-to-CAS delay = 2 |
|
||||||
* |
|
||||||
* EDB9307, EDB9312, EDB9315: |
|
||||||
* |
|
||||||
* 0x00000000 - 0x01ffffff |
|
||||||
* 0x04000000 - 0x05ffffff |
|
||||||
* |
|
||||||
* |
|
||||||
* EDB9307a, EDB9315a: |
|
||||||
* |
|
||||||
* 0xc0000000 - 0xc1ffffff |
|
||||||
* 0xc4000000 - 0xc5ffffff |
|
||||||
*/ |
|
||||||
|
|
||||||
#define SDRAM_DEVCFG_VAL (SDRAM_DEVCFG_BANKCOUNT | \ |
|
||||||
SDRAM_DEVCFG_SROMLL | \
|
|
||||||
SDRAM_DEVCFG_CASLAT_2 | \
|
|
||||||
SDRAM_DEVCFG_RASTOCAS_2) |
|
||||||
|
|
||||||
/*
|
|
||||||
* 32 bit ext. bus |
|
||||||
* |
|
||||||
* A[23:10] is output as SYA[13:0] |
|
||||||
* CAS latency: 2 |
|
||||||
* Burst type: sequential |
|
||||||
* Burst length: 4 |
|
||||||
* SYA[13:0] = 0x0022 |
|
||||||
*/ |
|
||||||
#define SDRAM_MODE_REG_VAL 0x8800 |
|
||||||
|
|
||||||
#define SDRAM_BANK_SEL_0 0x00000000 /* A[23:22] = b00 */ |
|
||||||
#define SDRAM_BANK_SEL_1 0x00400000 /* A[23:22] = b01 */ |
|
||||||
#define SDRAM_BANK_SEL_2 0x00800000 /* A[23:22] = b10 */ |
|
||||||
#define SDRAM_BANK_SEL_3 0x00c00000 /* A[23:22] = b11 */ |
|
||||||
#endif |
|
||||||
@ -1,269 +0,0 @@ |
|||||||
/*
|
|
||||||
* U-boot - Configuration file for Cirrus Logic EDB93xx boards |
|
||||||
*/ |
|
||||||
|
|
||||||
#ifndef __CONFIG_H |
|
||||||
#define __CONFIG_H |
|
||||||
|
|
||||||
#ifdef CONFIG_edb9301 |
|
||||||
#define CONFIG_EDB9301 |
|
||||||
#elif defined(CONFIG_edb9302) |
|
||||||
#define CONFIG_EDB9302 |
|
||||||
#elif defined(CONFIG_edb9302a) |
|
||||||
#define CONFIG_EDB9302A |
|
||||||
#elif defined(CONFIG_edb9307) |
|
||||||
#define CONFIG_EDB9307 |
|
||||||
#elif defined(CONFIG_edb9307a) |
|
||||||
#define CONFIG_EDB9307A |
|
||||||
#elif defined(CONFIG_edb9312) |
|
||||||
#define CONFIG_EDB9312 |
|
||||||
#elif defined(CONFIG_edb9315) |
|
||||||
#define CONFIG_EDB9315 |
|
||||||
#elif defined(CONFIG_edb9315a) |
|
||||||
#define CONFIG_EDB9315A |
|
||||||
#else |
|
||||||
#error "no board defined" |
|
||||||
#endif |
|
||||||
|
|
||||||
/* Initial environment and monitor configuration options. */ |
|
||||||
#define CONFIG_BOOTDELAY 2 |
|
||||||
#define CONFIG_CMDLINE_TAG 1 |
|
||||||
#define CONFIG_INITRD_TAG 1 |
|
||||||
#define CONFIG_SETUP_MEMORY_TAGS 1 |
|
||||||
#define CONFIG_BOOTARGS "root=/dev/nfs console=ttyAM0,115200 ip=dhcp" |
|
||||||
#define CONFIG_BOOTFILE "edb93xx.img" |
|
||||||
|
|
||||||
#define CONFIG_SYS_HUSH_PARSER 1 |
|
||||||
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " |
|
||||||
|
|
||||||
#ifdef CONFIG_EDB9301 |
|
||||||
#define CONFIG_EP9301 |
|
||||||
#define CONFIG_MACH_TYPE MACH_TYPE_EDB9301 |
|
||||||
#define CONFIG_SYS_PROMPT "EDB9301> " |
|
||||||
#define CONFIG_ENV_SECT_SIZE 0x00020000 |
|
||||||
#elif defined(CONFIG_EDB9302) |
|
||||||
#define CONFIG_EP9302 |
|
||||||
#define CONFIG_MACH_TYPE MACH_TYPE_EDB9302 |
|
||||||
#define CONFIG_SYS_PROMPT "EDB9302> " |
|
||||||
#define CONFIG_ENV_SECT_SIZE 0x00020000 |
|
||||||
#elif defined(CONFIG_EDB9302A) |
|
||||||
#define CONFIG_EP9302 |
|
||||||
#define CONFIG_MACH_TYPE MACH_TYPE_EDB9302A |
|
||||||
#define CONFIG_SYS_PROMPT "EDB9302A> " |
|
||||||
#define CONFIG_ENV_SECT_SIZE 0x00020000 |
|
||||||
#elif defined(CONFIG_EDB9307) |
|
||||||
#define CONFIG_EP9307 |
|
||||||
#define CONFIG_MACH_TYPE MACH_TYPE_EDB9307 |
|
||||||
#define CONFIG_SYS_PROMPT "EDB9307> " |
|
||||||
#define CONFIG_ENV_SECT_SIZE 0x00040000 |
|
||||||
#elif defined(CONFIG_EDB9307A) |
|
||||||
#define CONFIG_EP9307 |
|
||||||
#define CONFIG_MACH_TYPE MACH_TYPE_EDB9307A |
|
||||||
#define CONFIG_SYS_PROMPT "EDB9307A> " |
|
||||||
#define CONFIG_ENV_SECT_SIZE 0x00040000 |
|
||||||
#elif defined(CONFIG_EDB9312) |
|
||||||
#define CONFIG_EP9312 |
|
||||||
#define CONFIG_MACH_TYPE MACH_TYPE_EDB9312 |
|
||||||
#define CONFIG_SYS_PROMPT "EDB9312> " |
|
||||||
#define CONFIG_ENV_SECT_SIZE 0x00040000 |
|
||||||
#elif defined(CONFIG_EDB9315) |
|
||||||
#define CONFIG_EP9315 |
|
||||||
#define CONFIG_MACH_TYPE MACH_TYPE_EDB9315 |
|
||||||
#define CONFIG_SYS_PROMPT "EDB9315> " |
|
||||||
#define CONFIG_ENV_SECT_SIZE 0x00040000 |
|
||||||
#elif defined(CONFIG_EDB9315A) |
|
||||||
#define CONFIG_EP9315 |
|
||||||
#define CONFIG_MACH_TYPE MACH_TYPE_EDB9315A |
|
||||||
#define CONFIG_SYS_PROMPT "EDB9315A> " |
|
||||||
#define CONFIG_ENV_SECT_SIZE 0x00040000 |
|
||||||
#else |
|
||||||
#error "no board defined" |
|
||||||
#endif |
|
||||||
|
|
||||||
/* High-level configuration options */ |
|
||||||
#define CONFIG_ARM920T 1 /* This is an ARM920T core... */ |
|
||||||
#define CONFIG_EP93XX 1 /* in a Cirrus Logic 93xx SoC */ |
|
||||||
|
|
||||||
#define CONFIG_SYS_CLK_FREQ 14745600 /* EP93xx has a 14.7456 clock */ |
|
||||||
#define CONFIG_SYS_HZ 1000 /* decr freq: 1 ms ticks */ |
|
||||||
#undef CONFIG_USE_IRQ /* Don't need IRQ/FIQ */ |
|
||||||
|
|
||||||
/* Monitor configuration */ |
|
||||||
#include <config_cmd_default.h> |
|
||||||
#undef CONFIG_CMD_FPGA |
|
||||||
#undef CONFIG_CMD_SETGETDCR |
|
||||||
#undef CONFIG_CMD_XIMG |
|
||||||
|
|
||||||
#undef CONFIG_CMD_DATE |
|
||||||
#define CONFIG_CMD_DHCP |
|
||||||
#define CONFIG_CMD_FAT |
|
||||||
#define CONFIG_CMD_JFFS2 |
|
||||||
|
|
||||||
#define CONFIG_SYS_LONGHELP /* Enable "long" help in mon */ |
|
||||||
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */ |
|
||||||
/* Print buffer size */ |
|
||||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) |
|
||||||
/* Boot argument buffer size */ |
|
||||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE |
|
||||||
#define CONFIG_SYS_MAXARGS 16 /* Max number of command args */ |
|
||||||
|
|
||||||
/* Serial port hardware configuration */ |
|
||||||
#define CONFIG_PL010_SERIAL |
|
||||||
#define CONFIG_CONS_INDEX 0 |
|
||||||
#define CONFIG_BAUDRATE 115200 |
|
||||||
#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200} |
|
||||||
#define CONFIG_SYS_SERIAL0 0x808C0000 |
|
||||||
#define CONFIG_SYS_SERIAL1 0x808D0000 |
|
||||||
#define CONFIG_PL01x_PORTS {(void *)CONFIG_SYS_SERIAL0, \ |
|
||||||
(void *)CONFIG_SYS_SERIAL1} |
|
||||||
|
|
||||||
/* Status LED */ |
|
||||||
#define CONFIG_STATUS_LED 1 /* Status LED enabled */ |
|
||||||
#define CONFIG_BOARD_SPECIFIC_LED 1 |
|
||||||
#define STATUS_LED_GREEN 0 |
|
||||||
#define STATUS_LED_RED 1 |
|
||||||
/* Green */ |
|
||||||
#define STATUS_LED_BIT STATUS_LED_GREEN |
|
||||||
#define STATUS_LED_STATE STATUS_LED_ON |
|
||||||
#define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2) |
|
||||||
/* Red */ |
|
||||||
#define STATUS_LED_BIT1 STATUS_LED_RED |
|
||||||
#define STATUS_LED_STATE1 STATUS_LED_OFF |
|
||||||
#define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ / 2) |
|
||||||
/* Optional value */ |
|
||||||
#define STATUS_LED_BOOT STATUS_LED_BIT |
|
||||||
|
|
||||||
/* Network hardware configuration */ |
|
||||||
#define CONFIG_DRIVER_EP93XX_MAC |
|
||||||
#define CONFIG_MII_SUPPRESS_PREAMBLE |
|
||||||
#define CONFIG_MII |
|
||||||
#define CONFIG_PHY_ADDR 1 |
|
||||||
#define CONFIG_NET_MULTI |
|
||||||
#undef CONFIG_NETCONSOLE |
|
||||||
|
|
||||||
/* SDRAM configuration */ |
|
||||||
#if defined(CONFIG_EDB9301) || defined(CONFIG_EDB9302) |
|
||||||
/*
|
|
||||||
* EDB9301/2 has 4 banks of SDRAM consisting of 1x Samsung K4S561632E-TC75 |
|
||||||
* 256 Mbit SDRAM on a 16-bit data bus, for a total of 32MB of SDRAM. We set |
|
||||||
* the SROMLL bit on the processor, resulting in this non-contiguous memory map. |
|
||||||
*/ |
|
||||||
#define CONFIG_NR_DRAM_BANKS 4 |
|
||||||
#define PHYS_SDRAM_1 0x00000000 |
|
||||||
#define PHYS_SDRAM_SIZE_1 0x00800000 |
|
||||||
#define PHYS_SDRAM_2 0x01000000 |
|
||||||
#define PHYS_SDRAM_SIZE_2 0x00800000 |
|
||||||
#define PHYS_SDRAM_3 0x04000000 |
|
||||||
#define PHYS_SDRAM_SIZE_3 0x00800000 |
|
||||||
#define PHYS_SDRAM_4 0x05000000 |
|
||||||
#define PHYS_SDRAM_SIZE_4 0x00800000 |
|
||||||
#define CONFIG_EDB93XX_SDCS3 |
|
||||||
#define CONFIG_SYS_MEMTEST_START 0x00100000 |
|
||||||
#define CONFIG_SYS_MEMTEST_END 0x007fffff |
|
||||||
|
|
||||||
#elif defined(CONFIG_EDB9302A) |
|
||||||
/*
|
|
||||||
* EDB9302a has 4 banks of SDRAM consisting of 1x Samsung K4S561632E-TC75 |
|
||||||
* 256 Mbit SDRAM on a 16-bit data bus, for a total of 32MB of SDRAM. We set |
|
||||||
* the SROMLL bit on the processor, resulting in this non-contiguous memory map. |
|
||||||
*/ |
|
||||||
#define CONFIG_NR_DRAM_BANKS 4 |
|
||||||
#define PHYS_SDRAM_1 0xc0000000 |
|
||||||
#define PHYS_SDRAM_SIZE_1 0x00800000 |
|
||||||
#define PHYS_SDRAM_2 0xc1000000 |
|
||||||
#define PHYS_SDRAM_SIZE_2 0x00800000 |
|
||||||
#define PHYS_SDRAM_3 0xc4000000 |
|
||||||
#define PHYS_SDRAM_SIZE_3 0x00800000 |
|
||||||
#define PHYS_SDRAM_4 0xc5000000 |
|
||||||
#define PHYS_SDRAM_SIZE_4 0x00800000 |
|
||||||
#define CONFIG_EDB93XX_SDCS0 |
|
||||||
#define CONFIG_SYS_MEMTEST_START 0xc0100000 |
|
||||||
#define CONFIG_SYS_MEMTEST_END 0xc07fffff |
|
||||||
|
|
||||||
#elif defined(CONFIG_EDB9307) || defined CONFIG_EDB9312 || \ |
|
||||||
defined(CONFIG_EDB9315) |
|
||||||
/*
|
|
||||||
* The EDB9307, EDB9312, and EDB9315 have 2 banks of SDRAM consisting of |
|
||||||
* 2x Samsung K4S561632E-TC75 256 Mbit on a 32-bit data bus, for a total of |
|
||||||
* 64 MB of SDRAM. |
|
||||||
*/ |
|
||||||
#define CONFIG_NR_DRAM_BANKS 2 |
|
||||||
#define PHYS_SDRAM_1 0x00000000 |
|
||||||
#define PHYS_SDRAM_SIZE_1 0x02000000 |
|
||||||
#define PHYS_SDRAM_2 0x04000000 |
|
||||||
#define PHYS_SDRAM_SIZE_2 0x02000000 |
|
||||||
#define CONFIG_EDB93XX_SDCS3 |
|
||||||
#define CONFIG_SYS_MEMTEST_START 0x00100000 |
|
||||||
#define CONFIG_SYS_MEMTEST_END 0x01e00000 |
|
||||||
|
|
||||||
#elif defined(CONFIG_EDB9307A) || defined(CONFIG_EDB9315A) |
|
||||||
/*
|
|
||||||
* The EDB9307A and EDB9315A have 2 banks of SDRAM consisting of 2x Samsung |
|
||||||
* K4S561632E-TC75 256 Mbit on a 32-bit data bus, for a total of 64 MB of SDRAM. |
|
||||||
*/ |
|
||||||
#define CONFIG_NR_DRAM_BANKS 2 |
|
||||||
#define PHYS_SDRAM_1 0xc0000000 |
|
||||||
#define PHYS_SDRAM_SIZE_1 0x02000000 |
|
||||||
#define PHYS_SDRAM_2 0xc4000000 |
|
||||||
#define PHYS_SDRAM_SIZE_2 0x02000000 |
|
||||||
#define CONFIG_EDB93XX_SDCS0 |
|
||||||
#define CONFIG_SYS_MEMTEST_START 0xc0100000 |
|
||||||
#define CONFIG_SYS_MEMTEST_END 0xc1e00000 |
|
||||||
#endif |
|
||||||
|
|
||||||
/* Default load address */ |
|
||||||
#define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x01000000) |
|
||||||
|
|
||||||
/* Must match kernel config */ |
|
||||||
#define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100) |
|
||||||
|
|
||||||
/* Run-time memory allocatons */ |
|
||||||
#define CONFIG_STACKSIZE (128 * 1024) |
|
||||||
|
|
||||||
#if defined(CONFIG_USE_IRQ) |
|
||||||
#define CONFIG_STACKSIZE_IRQ (4 * 1024) |
|
||||||
#define CONFIG_STACKSIZE_FIQ (4 * 1024) |
|
||||||
#endif |
|
||||||
|
|
||||||
#define CONFIG_SYS_MALLOC_LEN (512 * 1024) |
|
||||||
|
|
||||||
/* -----------------------------------------------------------------------------
|
|
||||||
* FLASH and environment organization |
|
||||||
* |
|
||||||
* The EDB9301 and EDB9302(a) have 1 bank of flash memory at 0x60000000 |
|
||||||
* consisting of 1x Intel TE28F128J3C-150 128 Mbit flash on a 16-bit data bus, |
|
||||||
* for a total of 16 MB of CFI-compatible flash. |
|
||||||
* |
|
||||||
* The EDB9307(a), EDB9312, and EDB9315(a) have 1 bank of flash memory at |
|
||||||
* 0x60000000 consisting of 2x Micron MT28F128J3-12 128 Mbit flash on a 32-bit |
|
||||||
* data bus, for a total of 32 MB of CFI-compatible flash. |
|
||||||
* |
|
||||||
* EDB9301/02(a) EDB9307(a)/12/15(a) |
|
||||||
* 0x60000000 - 0x0003FFFF u-boot u-boot |
|
||||||
* 0x60040000 - 0x0005FFFF environment #1 environment #1 |
|
||||||
* 0x60060000 - 0x0007FFFF environment #2 environment #1 (continued) |
|
||||||
* 0x60080000 - 0x0009FFFF unused environment #2 |
|
||||||
* 0x600A0000 - 0x000BFFFF unused environment #2 (continued) |
|
||||||
* 0x600C0000 - 0x00FFFFFF unused unused |
|
||||||
* 0x61000000 - 0x01FFFFFF not present unused |
|
||||||
*/ |
|
||||||
#define CONFIG_SYS_FLASH_CFI |
|
||||||
#define CONFIG_FLASH_CFI_DRIVER |
|
||||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1 |
|
||||||
#define CONFIG_SYS_MAX_FLASH_SECT 128 |
|
||||||
|
|
||||||
#define PHYS_FLASH_1 0x60000000 |
|
||||||
#define CONFIG_SYS_FLASH_BASE (PHYS_FLASH_1) |
|
||||||
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE |
|
||||||
#define CONFIG_SYS_MONITOR_LEN (256 * 1024) |
|
||||||
|
|
||||||
#define CONFIG_ENV_OVERWRITE /* Vendor params unprotected */ |
|
||||||
#define CONFIG_ENV_IS_IN_FLASH |
|
||||||
#define CONFIG_ENV_ADDR 0x60040000 |
|
||||||
|
|
||||||
#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) |
|
||||||
|
|
||||||
#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE |
|
||||||
#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE |
|
||||||
|
|
||||||
#endif /* !defined (__CONFIG_H) */ |
|
||||||
Loading…
Reference in new issue