Add timer support for Stratix SoC Signed-off-by: Chin Liang See <chin.liang.see@intel.com> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Marek Vasut <marex@denx.de>lime2-spi
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2017-2018 Intel Corporation <www.intel.com> |
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* |
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*/ |
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#include <common.h> |
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#include <asm/io.h> |
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#include <asm/arch/timer.h> |
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/*
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* Timer initialization |
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*/ |
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int timer_init(void) |
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{ |
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int enable = 0x3; /* timer enable + output signal masked */ |
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int loadval = ~0; |
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/* enable system counter */ |
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writel(enable, SOCFPGA_GTIMER_SEC_ADDRESS); |
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/* enable processor pysical counter */ |
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asm volatile("msr cntp_ctl_el0, %0" : : "r" (enable)); |
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asm volatile("msr cntp_tval_el0, %0" : : "r" (loadval)); |
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return 0; |
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} |
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