Support the DesginWare MMC Controller. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Rajeshawari Shinde <rajeshwari.s@samsung.com> Signed-off-by: Andy Fleming <afleming@freescale.com>master
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/*
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* (C) Copyright 2012 SAMSUNG Electronics |
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* Jaehoon Chung <jh80.chung@samsung.com> |
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* Rajeshawari Shinde <rajeshwari.s@samsung.com> |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
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* |
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*/ |
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#include <common.h> |
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#include <malloc.h> |
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#include <mmc.h> |
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#include <dwmmc.h> |
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#include <asm/arch/clk.h> |
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#include <asm-generic/errno.h> |
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#define PAGE_SIZE 4096 |
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static int dwmci_wait_reset(struct dwmci_host *host, u32 value) |
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{ |
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unsigned long timeout = 1000; |
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u32 ctrl; |
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dwmci_writel(host, DWMCI_CTRL, value); |
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while (timeout--) { |
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ctrl = dwmci_readl(host, DWMCI_CTRL); |
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if (!(ctrl & DWMCI_RESET_ALL)) |
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return 1; |
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} |
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return 0; |
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} |
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static void dwmci_set_idma_desc(struct dwmci_idmac *idmac, |
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u32 desc0, u32 desc1, u32 desc2) |
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{ |
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struct dwmci_idmac *desc = idmac; |
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desc->flags = desc0; |
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desc->cnt = desc1; |
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desc->addr = desc2; |
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desc->next_addr = (unsigned int)desc + sizeof(struct dwmci_idmac); |
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} |
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static void dwmci_prepare_data(struct dwmci_host *host, |
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struct mmc_data *data) |
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{ |
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unsigned long ctrl; |
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unsigned int i = 0, flags, cnt, blk_cnt; |
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ulong data_start, data_end, start_addr; |
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ALLOC_CACHE_ALIGN_BUFFER(struct dwmci_idmac, cur_idmac, data->blocks); |
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blk_cnt = data->blocks; |
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dwmci_wait_reset(host, DWMCI_CTRL_FIFO_RESET); |
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data_start = (ulong)cur_idmac; |
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dwmci_writel(host, DWMCI_DBADDR, (unsigned int)cur_idmac); |
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if (data->flags == MMC_DATA_READ) |
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start_addr = (unsigned int)data->dest; |
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else |
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start_addr = (unsigned int)data->src; |
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do { |
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flags = DWMCI_IDMAC_OWN | DWMCI_IDMAC_CH ; |
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flags |= (i == 0) ? DWMCI_IDMAC_FS : 0; |
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if (blk_cnt <= 8) { |
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flags |= DWMCI_IDMAC_LD; |
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cnt = data->blocksize * blk_cnt; |
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} else |
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cnt = data->blocksize * 8; |
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dwmci_set_idma_desc(cur_idmac, flags, cnt, |
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start_addr + (i * PAGE_SIZE)); |
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if(blk_cnt < 8) |
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break; |
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blk_cnt -= 8; |
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cur_idmac++; |
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i++; |
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} while(1); |
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data_end = (ulong)cur_idmac; |
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flush_dcache_range(data_start, data_end + ARCH_DMA_MINALIGN); |
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ctrl = dwmci_readl(host, DWMCI_CTRL); |
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ctrl |= DWMCI_IDMAC_EN | DWMCI_DMA_EN; |
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dwmci_writel(host, DWMCI_CTRL, ctrl); |
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ctrl = dwmci_readl(host, DWMCI_BMOD); |
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ctrl |= DWMCI_BMOD_IDMAC_FB | DWMCI_BMOD_IDMAC_EN; |
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dwmci_writel(host, DWMCI_BMOD, ctrl); |
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dwmci_writel(host, DWMCI_BLKSIZ, data->blocksize); |
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dwmci_writel(host, DWMCI_BYTCNT, data->blocksize * data->blocks); |
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} |
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static int dwmci_set_transfer_mode(struct dwmci_host *host, |
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struct mmc_data *data) |
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{ |
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unsigned long mode; |
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mode = DWMCI_CMD_DATA_EXP; |
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if (data->flags & MMC_DATA_WRITE) |
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mode |= DWMCI_CMD_RW; |
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return mode; |
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} |
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static int dwmci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, |
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struct mmc_data *data) |
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{ |
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struct dwmci_host *host = (struct dwmci_host *)mmc->priv; |
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int flags = 0, i; |
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unsigned int timeout = 100000; |
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u32 retry = 10000; |
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u32 mask, ctrl; |
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while (dwmci_readl(host, DWMCI_STATUS) & DWMCI_BUSY) { |
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if (timeout == 0) { |
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printf("Timeout on data busy\n"); |
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return TIMEOUT; |
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} |
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timeout--; |
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} |
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dwmci_writel(host, DWMCI_RINTSTS, DWMCI_INTMSK_ALL); |
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if (data) |
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dwmci_prepare_data(host, data); |
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dwmci_writel(host, DWMCI_CMDARG, cmd->cmdarg); |
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if (data) |
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flags = dwmci_set_transfer_mode(host, data); |
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if ((cmd->resp_type & MMC_RSP_136) && (cmd->resp_type & MMC_RSP_BUSY)) |
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return -1; |
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if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION) |
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flags |= DWMCI_CMD_ABORT_STOP; |
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else |
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flags |= DWMCI_CMD_PRV_DAT_WAIT; |
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if (cmd->resp_type & MMC_RSP_PRESENT) { |
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flags |= DWMCI_CMD_RESP_EXP; |
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if (cmd->resp_type & MMC_RSP_136) |
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flags |= DWMCI_CMD_RESP_LENGTH; |
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} |
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if (cmd->resp_type & MMC_RSP_CRC) |
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flags |= DWMCI_CMD_CHECK_CRC; |
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flags |= (cmd->cmdidx | DWMCI_CMD_START | DWMCI_CMD_USE_HOLD_REG); |
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debug("Sending CMD%d\n",cmd->cmdidx); |
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dwmci_writel(host, DWMCI_CMD, flags); |
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for (i = 0; i < retry; i++) { |
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mask = dwmci_readl(host, DWMCI_RINTSTS); |
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if (mask & DWMCI_INTMSK_CDONE) { |
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if (!data) |
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dwmci_writel(host, DWMCI_RINTSTS, mask); |
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break; |
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} |
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} |
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if (i == retry) |
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return TIMEOUT; |
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if (mask & DWMCI_INTMSK_RTO) { |
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debug("Response Timeout..\n"); |
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return TIMEOUT; |
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} else if (mask & DWMCI_INTMSK_RE) { |
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debug("Response Error..\n"); |
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return -1; |
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} |
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if (cmd->resp_type & MMC_RSP_PRESENT) { |
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if (cmd->resp_type & MMC_RSP_136) { |
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cmd->response[0] = dwmci_readl(host, DWMCI_RESP3); |
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cmd->response[1] = dwmci_readl(host, DWMCI_RESP2); |
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cmd->response[2] = dwmci_readl(host, DWMCI_RESP1); |
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cmd->response[3] = dwmci_readl(host, DWMCI_RESP0); |
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} else { |
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cmd->response[0] = dwmci_readl(host, DWMCI_RESP0); |
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} |
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} |
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if (data) { |
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do { |
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mask = dwmci_readl(host, DWMCI_RINTSTS); |
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if (mask & (DWMCI_DATA_ERR | DWMCI_DATA_TOUT)) { |
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debug("DATA ERROR!\n"); |
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return -1; |
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} |
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} while (!(mask & DWMCI_INTMSK_DTO)); |
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dwmci_writel(host, DWMCI_RINTSTS, mask); |
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ctrl = dwmci_readl(host, DWMCI_CTRL); |
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ctrl &= ~(DWMCI_DMA_EN); |
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dwmci_writel(host, DWMCI_CTRL, ctrl); |
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} |
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udelay(100); |
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return 0; |
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} |
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static int dwmci_setup_bus(struct dwmci_host *host, u32 freq) |
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{ |
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u32 div, status; |
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int timeout = 10000; |
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unsigned long sclk; |
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if (freq == host->clock) |
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return 0; |
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/*
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* If host->mmc_clk didn't define, |
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* then assume that host->bus_hz is source clock value. |
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* host->bus_hz should be set from user. |
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*/ |
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if (host->mmc_clk) |
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sclk = host->mmc_clk(host->dev_index); |
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else if (host->bus_hz) |
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sclk = host->bus_hz; |
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else { |
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printf("Didn't get source clock value..\n"); |
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return -EINVAL; |
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} |
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div = DIV_ROUND_UP(sclk, 2 * freq); |
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dwmci_writel(host, DWMCI_CLKENA, 0); |
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dwmci_writel(host, DWMCI_CLKSRC, 0); |
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dwmci_writel(host, DWMCI_CLKDIV, div); |
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dwmci_writel(host, DWMCI_CMD, DWMCI_CMD_PRV_DAT_WAIT | |
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DWMCI_CMD_UPD_CLK | DWMCI_CMD_START); |
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do { |
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status = dwmci_readl(host, DWMCI_CMD); |
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if (timeout-- < 0) { |
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printf("TIMEOUT error!!\n"); |
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return -ETIMEDOUT; |
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} |
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} while (status & DWMCI_CMD_START); |
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dwmci_writel(host, DWMCI_CLKENA, DWMCI_CLKEN_ENABLE | |
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DWMCI_CLKEN_LOW_PWR); |
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dwmci_writel(host, DWMCI_CMD, DWMCI_CMD_PRV_DAT_WAIT | |
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DWMCI_CMD_UPD_CLK | DWMCI_CMD_START); |
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timeout = 10000; |
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do { |
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status = dwmci_readl(host, DWMCI_CMD); |
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if (timeout-- < 0) { |
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printf("TIMEOUT error!!\n"); |
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return -ETIMEDOUT; |
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} |
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} while (status & DWMCI_CMD_START); |
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host->clock = freq; |
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return 0; |
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} |
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static void dwmci_set_ios(struct mmc *mmc) |
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{ |
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struct dwmci_host *host = (struct dwmci_host *)mmc->priv; |
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u32 ctype; |
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debug("Buswidth = %d, clock: %d\n",mmc->bus_width, mmc->clock); |
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dwmci_setup_bus(host, mmc->clock); |
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switch (mmc->bus_width) { |
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case 8: |
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ctype = DWMCI_CTYPE_8BIT; |
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break; |
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case 4: |
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ctype = DWMCI_CTYPE_4BIT; |
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break; |
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default: |
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ctype = DWMCI_CTYPE_1BIT; |
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break; |
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} |
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dwmci_writel(host, DWMCI_CTYPE, ctype); |
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if (host->clksel) |
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host->clksel(host); |
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} |
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static int dwmci_init(struct mmc *mmc) |
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{ |
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struct dwmci_host *host = (struct dwmci_host *)mmc->priv; |
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u32 fifo_size, fifoth_val; |
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dwmci_writel(host, DWMCI_PWREN, 1); |
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if (!dwmci_wait_reset(host, DWMCI_RESET_ALL)) { |
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debug("%s[%d] Fail-reset!!\n",__func__,__LINE__); |
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return -1; |
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} |
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dwmci_writel(host, DWMCI_RINTSTS, 0xFFFFFFFF); |
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dwmci_writel(host, DWMCI_INTMASK, 0); |
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dwmci_writel(host, DWMCI_TMOUT, 0xFFFFFFFF); |
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dwmci_writel(host, DWMCI_IDINTEN, 0); |
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dwmci_writel(host, DWMCI_BMOD, 1); |
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fifo_size = dwmci_readl(host, DWMCI_FIFOTH); |
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if (host->fifoth_val) |
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fifoth_val = host->fifoth_val; |
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else |
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fifoth_val = MSIZE(0x2) | RX_WMARK(fifo_size/2 -1) | |
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TX_WMARK(fifo_size/2); |
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dwmci_writel(host, DWMCI_FIFOTH, fifoth_val); |
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dwmci_writel(host, DWMCI_CLKENA, 0); |
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dwmci_writel(host, DWMCI_CLKSRC, 0); |
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return 0; |
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} |
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int add_dwmci(struct dwmci_host *host, u32 max_clk, u32 min_clk) |
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{ |
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struct mmc *mmc; |
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int err = 0; |
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mmc = malloc(sizeof(struct mmc)); |
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if (!mmc) { |
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printf("mmc malloc fail!\n"); |
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return -1; |
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} |
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mmc->priv = host; |
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host->mmc = mmc; |
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sprintf(mmc->name, "%s", host->name); |
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mmc->send_cmd = dwmci_send_cmd; |
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mmc->set_ios = dwmci_set_ios; |
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mmc->init = dwmci_init; |
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mmc->f_min = min_clk; |
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mmc->f_max = max_clk; |
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mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195; |
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mmc->host_caps = host->caps; |
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if (host->buswidth == 8) { |
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mmc->host_caps |= MMC_MODE_8BIT; |
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mmc->host_caps &= ~MMC_MODE_4BIT; |
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} else { |
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mmc->host_caps |= MMC_MODE_4BIT; |
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mmc->host_caps &= ~MMC_MODE_8BIT; |
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} |
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mmc->host_caps |= MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_HC; |
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err = mmc_register(mmc); |
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return err; |
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} |
@ -0,0 +1,191 @@ |
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/*
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* (C) Copyright 2012 SAMSUNG Electronics |
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* Jaehoon Chung <jh80.chung@samsung.com> |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
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* |
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*/ |
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#ifndef __DWMMC_HW_H |
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#define __DWMMC_HW_H |
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#include <asm/io.h> |
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#include <mmc.h> |
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#define DWMCI_CTRL 0x000 |
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#define DWMCI_PWREN 0x004 |
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#define DWMCI_CLKDIV 0x008 |
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#define DWMCI_CLKSRC 0x00C |
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#define DWMCI_CLKENA 0x010 |
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#define DWMCI_TMOUT 0x014 |
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#define DWMCI_CTYPE 0x018 |
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#define DWMCI_BLKSIZ 0x01C |
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#define DWMCI_BYTCNT 0x020 |
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#define DWMCI_INTMASK 0x024 |
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#define DWMCI_CMDARG 0x028 |
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#define DWMCI_CMD 0x02C |
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#define DWMCI_RESP0 0x030 |
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#define DWMCI_RESP1 0x034 |
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#define DWMCI_RESP2 0x038 |
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#define DWMCI_RESP3 0x03C |
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#define DWMCI_MINTSTS 0x040 |
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#define DWMCI_RINTSTS 0x044 |
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#define DWMCI_STATUS 0x048 |
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#define DWMCI_FIFOTH 0x04C |
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#define DWMCI_CDETECT 0x050 |
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#define DWMCI_WRTPRT 0x054 |
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#define DWMCI_GPIO 0x058 |
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#define DWMCI_TCMCNT 0x05C |
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#define DWMCI_TBBCNT 0x060 |
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#define DWMCI_DEBNCE 0x064 |
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#define DWMCI_USRID 0x068 |
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#define DWMCI_VERID 0x06C |
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#define DWMCI_HCON 0x070 |
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#define DWMCI_UHS_REG 0x074 |
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#define DWMCI_BMOD 0x080 |
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#define DWMCI_PLDMND 0x084 |
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#define DWMCI_DBADDR 0x088 |
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#define DWMCI_IDSTS 0x08C |
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#define DWMCI_IDINTEN 0x090 |
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#define DWMCI_DSCADDR 0x094 |
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#define DWMCI_BUFADDR 0x098 |
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#define DWMCI_DATA 0x200 |
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|
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/* Interrupt Mask register */ |
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#define DWMCI_INTMSK_ALL 0xffffffff |
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#define DWMCI_INTMSK_RE (1 << 1) |
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#define DWMCI_INTMSK_CDONE (1 << 2) |
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#define DWMCI_INTMSK_DTO (1 << 3) |
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#define DWMCI_INTMSK_TXDR (1 << 4) |
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#define DWMCI_INTMSK_RXDR (1 << 5) |
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#define DWMCI_INTMSK_DCRC (1 << 7) |
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#define DWMCI_INTMSK_RTO (1 << 8) |
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#define DWMCI_INTMSK_DRTO (1 << 9) |
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#define DWMCI_INTMSK_HTO (1 << 10) |
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#define DWMCI_INTMSK_FRUN (1 << 11) |
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#define DWMCI_INTMSK_HLE (1 << 12) |
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#define DWMCI_INTMSK_SBE (1 << 13) |
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|
#define DWMCI_INTMSK_ACD (1 << 14) |
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|
#define DWMCI_INTMSK_EBE (1 << 15) |
||||||
|
|
||||||
|
/* Raw interrupt Regsiter */ |
||||||
|
#define DWMCI_DATA_ERR (DWMCI_INTMSK_EBE | DWMCI_INTMSK_SBE | DWMCI_INTMSK_HLE |\ |
||||||
|
DWMCI_INTMSK_FRUN | DWMCI_INTMSK_EBE | DWMCI_INTMSK_DCRC) |
||||||
|
#define DWMCI_DATA_TOUT (DWMCI_INTMSK_HTO | DWMCI_INTMSK_DRTO) |
||||||
|
/* CTRL register */ |
||||||
|
#define DWMCI_CTRL_RESET (1 << 0) |
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|
#define DWMCI_CTRL_FIFO_RESET (1 << 1) |
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|
#define DWMCI_CTRL_DMA_RESET (1 << 2) |
||||||
|
#define DWMCI_DMA_EN (1 << 5) |
||||||
|
#define DWMCI_CTRL_SEND_AS_CCSD (1 << 10) |
||||||
|
#define DWMCI_IDMAC_EN (1 << 25) |
||||||
|
#define DWMCI_RESET_ALL (DWMCI_CTRL_RESET | DWMCI_CTRL_FIFO_RESET |\ |
||||||
|
DWMCI_CTRL_DMA_RESET) |
||||||
|
|
||||||
|
/* CMD register */ |
||||||
|
#define DWMCI_CMD_RESP_EXP (1 << 6) |
||||||
|
#define DWMCI_CMD_RESP_LENGTH (1 << 7) |
||||||
|
#define DWMCI_CMD_CHECK_CRC (1 << 8) |
||||||
|
#define DWMCI_CMD_DATA_EXP (1 << 9) |
||||||
|
#define DWMCI_CMD_RW (1 << 10) |
||||||
|
#define DWMCI_CMD_SEND_STOP (1 << 12) |
||||||
|
#define DWMCI_CMD_ABORT_STOP (1 << 14) |
||||||
|
#define DWMCI_CMD_PRV_DAT_WAIT (1 << 13) |
||||||
|
#define DWMCI_CMD_UPD_CLK (1 << 21) |
||||||
|
#define DWMCI_CMD_USE_HOLD_REG (1 << 29) |
||||||
|
#define DWMCI_CMD_START (1 << 31) |
||||||
|
|
||||||
|
/* CLKENA register */ |
||||||
|
#define DWMCI_CLKEN_ENABLE (1 << 0) |
||||||
|
#define DWMCI_CLKEN_LOW_PWR (1 << 16) |
||||||
|
|
||||||
|
/* Card-type registe */ |
||||||
|
#define DWMCI_CTYPE_1BIT 0 |
||||||
|
#define DWMCI_CTYPE_4BIT (1 << 0) |
||||||
|
#define DWMCI_CTYPE_8BIT (1 << 16) |
||||||
|
|
||||||
|
/* Status Register */ |
||||||
|
#define DWMCI_BUSY (1 << 9) |
||||||
|
|
||||||
|
/* FIFOTH Register */ |
||||||
|
#define MSIZE(x) ((x) << 28) |
||||||
|
#define RX_WMARK(x) ((x) << 16) |
||||||
|
#define TX_WMARK(x) (x) |
||||||
|
|
||||||
|
#define DWMCI_IDMAC_OWN (1 << 31) |
||||||
|
#define DWMCI_IDMAC_CH (1 << 4) |
||||||
|
#define DWMCI_IDMAC_FS (1 << 3) |
||||||
|
#define DWMCI_IDMAC_LD (1 << 2) |
||||||
|
|
||||||
|
/* Bus Mode Register */ |
||||||
|
#define DWMCI_BMOD_IDMAC_RESET (1 << 0) |
||||||
|
#define DWMCI_BMOD_IDMAC_FB (1 << 1) |
||||||
|
#define DWMCI_BMOD_IDMAC_EN (1 << 7) |
||||||
|
|
||||||
|
struct dwmci_host { |
||||||
|
char *name; |
||||||
|
void *ioaddr; |
||||||
|
unsigned int quirks; |
||||||
|
unsigned int caps; |
||||||
|
unsigned int version; |
||||||
|
unsigned int clock; |
||||||
|
unsigned int bus_hz; |
||||||
|
int dev_index; |
||||||
|
int buswidth; |
||||||
|
u32 fifoth_val; |
||||||
|
struct mmc *mmc; |
||||||
|
|
||||||
|
void (*clksel)(struct dwmci_host *host); |
||||||
|
unsigned int (*mmc_clk)(int dev_index); |
||||||
|
}; |
||||||
|
|
||||||
|
struct dwmci_idmac { |
||||||
|
u32 flags; |
||||||
|
u32 cnt; |
||||||
|
u32 addr; |
||||||
|
u32 next_addr; |
||||||
|
}; |
||||||
|
|
||||||
|
static inline void dwmci_writel(struct dwmci_host *host, int reg, u32 val) |
||||||
|
{ |
||||||
|
writel(val, host->ioaddr + reg); |
||||||
|
} |
||||||
|
|
||||||
|
static inline void dwmci_writew(struct dwmci_host *host, int reg, u16 val) |
||||||
|
{ |
||||||
|
writew(val, host->ioaddr + reg); |
||||||
|
} |
||||||
|
|
||||||
|
static inline void dwmci_writeb(struct dwmci_host *host, int reg, u8 val) |
||||||
|
{ |
||||||
|
writeb(val, host->ioaddr + reg); |
||||||
|
} |
||||||
|
static inline u32 dwmci_readl(struct dwmci_host *host, int reg) |
||||||
|
{ |
||||||
|
return readl(host->ioaddr + reg); |
||||||
|
} |
||||||
|
|
||||||
|
static inline u16 dwmci_readw(struct dwmci_host *host, int reg) |
||||||
|
{ |
||||||
|
return readw(host->ioaddr + reg); |
||||||
|
} |
||||||
|
|
||||||
|
static inline u8 dwmci_readb(struct dwmci_host *host, int reg) |
||||||
|
{ |
||||||
|
return readb(host->ioaddr + reg); |
||||||
|
} |
||||||
|
|
||||||
|
int add_dwmci(struct dwmci_host *host, u32 max_clk, u32 min_clk); |
||||||
|
#endif /* __DWMMC_HW_H */ |
Loading…
Reference in new issue