The CS_AUTOBOOT configurations have been broken for a long time. Kshitij Gupta is no longer at TI making these broken and orphaned boards, so remove. Signed-off-by: Tom Rini <trini@ti.com>master
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#
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# (C) Copyright 2000-2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk |
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LIB = $(obj)lib$(BOARD).o
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COBJS := omap1610innovator.o flash.o
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SOBJS := lowlevel_init.o
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS))
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SOBJS := $(addprefix $(obj),$(SOBJS))
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$(LIB): $(obj).depend $(OBJS) $(SOBJS) |
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$(call cmd_link_o_target, $(OBJS) $(SOBJS))
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#########################################################################
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk |
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sinclude $(obj).depend |
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#########################################################################
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@ -1,26 +0,0 @@ |
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#
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# (C) Copyright 2002
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# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
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# David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
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#
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# (C) Copyright 2003
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# Texas Instruments, <www.ti.com>
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# Kshitij Gupta <Kshitij@ti.com>
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#
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# TI Innovator board with OMAP1610 (ARM925EJS) cpu
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# see http://www.ti.com/ for more information on Texas Instruments
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#
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# Innovator has 1 bank of 256 MB SDRAM
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# Physical Address:
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# 1000'0000 to 2000'0000
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#
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#
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# Linux-Kernel is expected to be at 1000'8000, entry 1000'8000
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# (mem base + reserved)
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#
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# we load ourself to 1108'0000
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#
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#
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CONFIG_SYS_TEXT_BASE = 0x11080000
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@ -1,495 +0,0 @@ |
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/*
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* (C) Copyright 2001 |
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* Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net |
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* |
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* (C) Copyright 2001-2004 |
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
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* |
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* (C) Copyright 2003 |
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* Texas Instruments, <www.ti.com> |
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* Kshitij Gupta <Kshitij@ti.com> |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#include <common.h> |
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#include <linux/byteorder/swab.h> |
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#define PHYS_FLASH_SECT_SIZE 0x00020000 /* 256 KB sectors (x2) */ |
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flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ |
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/* Board support for 1 or 2 flash devices */ |
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#undef FLASH_PORT_WIDTH32 |
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#define FLASH_PORT_WIDTH16 |
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#ifdef FLASH_PORT_WIDTH16 |
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#define FLASH_PORT_WIDTH ushort |
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#define FLASH_PORT_WIDTHV vu_short |
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#define SWAP(x) __swab16(x) |
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#else |
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#define FLASH_PORT_WIDTH ulong |
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#define FLASH_PORT_WIDTHV vu_long |
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#define SWAP(x) __swab32(x) |
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#endif |
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#define FPW FLASH_PORT_WIDTH |
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#define FPWV FLASH_PORT_WIDTHV |
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#define mb() __asm__ __volatile__ ("" : : : "memory") |
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/* Flash Organization Structure */ |
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typedef struct OrgDef { |
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unsigned int sector_number; |
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unsigned int sector_size; |
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} OrgDef; |
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/* Flash Organizations */ |
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OrgDef OrgIntel_28F256L18T[] = { |
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{4, 32 * 1024}, /* 4 * 32kBytes sectors */ |
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{255, 128 * 1024}, /* 255 * 128kBytes sectors */ |
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}; |
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/*-----------------------------------------------------------------------
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* Functions |
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*/ |
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unsigned long flash_init (void); |
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static ulong flash_get_size (FPW * addr, flash_info_t * info); |
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static int write_data (flash_info_t * info, ulong dest, FPW data); |
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static void flash_get_offsets (ulong base, flash_info_t * info); |
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void inline spin_wheel (void); |
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void flash_print_info (flash_info_t * info); |
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void flash_unprotect_sectors (FPWV * addr); |
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int flash_erase (flash_info_t * info, int s_first, int s_last); |
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int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt); |
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void flash_unlock(flash_info_t * info); |
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/*-----------------------------------------------------------------------
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*/ |
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unsigned long flash_init (void) |
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{ |
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int i; |
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ulong size = 0; |
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for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) { |
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switch (i) { |
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case 0: |
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flash_get_size ((FPW *) CONFIG_SYS_FLASH_BASE, &flash_info[i]); |
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flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[i]); |
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/* to reset the lock bit */ |
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flash_unlock(&flash_info[i]); |
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break; |
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default: |
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panic ("configured too many flash banks!\n"); |
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break; |
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} |
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size += flash_info[i].size; |
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} |
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/* Protect monitor and environment sectors
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*/ |
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flash_protect (FLAG_PROTECT_SET, |
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CONFIG_SYS_FLASH_BASE, |
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CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1, &flash_info[0]); |
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flash_protect (FLAG_PROTECT_SET, |
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CONFIG_ENV_ADDR, |
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CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]); |
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return size; |
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} |
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/*-----------------------------------------------------------------------
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*/ |
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void flash_unlock(flash_info_t * info) |
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{ |
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int j; |
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for (j=2;j<CONFIG_SYS_MAX_FLASH_SECT;j++){ |
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FPWV *addr = (FPWV *) (info->start[j]); |
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flash_unprotect_sectors (addr); |
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*addr = (FPW) 0x00500050;/* clear status register */ |
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*addr = (FPW) 0x00FF00FF;/* resest to read mode */ |
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} |
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} |
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/*-----------------------------------------------------------------------
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*/ |
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static void flash_get_offsets (ulong base, flash_info_t * info) |
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{ |
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int i; |
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if (info->flash_id == FLASH_UNKNOWN) { |
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return; |
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} |
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if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) { |
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for (i = 0; i < info->sector_count; i++) { |
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if (i > 255) { |
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info->start[i] = base + (i * 0x8000); |
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info->protect[i] = 0; |
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} else { |
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info->start[i] = base + |
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(i * PHYS_FLASH_SECT_SIZE); |
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info->protect[i] = 0; |
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} |
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} |
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} |
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} |
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/*-----------------------------------------------------------------------
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*/ |
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void flash_print_info (flash_info_t * info) |
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{ |
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int i; |
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if (info->flash_id == FLASH_UNKNOWN) { |
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printf ("missing or unknown FLASH type\n"); |
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return; |
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} |
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switch (info->flash_id & FLASH_VENDMASK) { |
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case FLASH_MAN_INTEL: |
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printf ("INTEL "); |
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break; |
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default: |
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printf ("Unknown Vendor "); |
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break; |
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} |
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switch (info->flash_id & FLASH_TYPEMASK) { |
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case FLASH_28F256L18T: |
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printf ("FLASH 28F256L18T\n"); |
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break; |
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default: |
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printf ("Unknown Chip Type\n"); |
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break; |
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} |
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printf (" Size: %ld MB in %d Sectors\n", |
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info->size >> 20, info->sector_count); |
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printf (" Sector Start Addresses:"); |
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for (i = 0; i < info->sector_count; ++i) { |
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if ((i % 5) == 0) |
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printf ("\n "); |
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printf (" %08lX%s", |
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info->start[i], info->protect[i] ? " (RO)" : " "); |
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} |
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printf ("\n"); |
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return; |
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} |
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/*
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* The following code cannot be run from FLASH! |
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*/ |
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static ulong flash_get_size (FPW * addr, flash_info_t * info) |
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{ |
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volatile FPW value; |
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/* Write auto select command: read Manufacturer ID */ |
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addr[0x5555] = (FPW) 0x00AA00AA; |
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addr[0x2AAA] = (FPW) 0x00550055; |
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addr[0x5555] = (FPW) 0x00900090; |
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mb (); |
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value = addr[0]; |
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switch (value) { |
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case (FPW) INTEL_MANUFACT: |
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info->flash_id = FLASH_MAN_INTEL; |
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break; |
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default: |
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info->flash_id = FLASH_UNKNOWN; |
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info->sector_count = 0; |
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info->size = 0; |
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addr[0] = (FPW) 0x00FF00FF; /* restore read mode */ |
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return (0); /* no or unknown flash */ |
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} |
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mb (); |
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value = addr[1]; /* device ID */ |
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switch (value) { |
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case (FPW) (INTEL_ID_28F256L18T): |
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info->flash_id += FLASH_28F256L18T; |
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info->sector_count = 259; |
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info->size = 0x02000000; |
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break; /* => 32 MB */ |
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default: |
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info->flash_id = FLASH_UNKNOWN; |
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break; |
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} |
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if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) { |
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printf ("** ERROR: sector count %d > max (%d) **\n", |
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info->sector_count, CONFIG_SYS_MAX_FLASH_SECT); |
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info->sector_count = CONFIG_SYS_MAX_FLASH_SECT; |
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} |
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addr[0] = (FPW) 0x00FF00FF; /* restore read mode */ |
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return (info->size); |
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} |
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/* unprotects a sector for write and erase
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* on some intel parts, this unprotects the entire chip, but it |
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* wont hurt to call this additional times per sector... |
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*/ |
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void flash_unprotect_sectors (FPWV * addr) |
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{ |
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#define PD_FINTEL_WSMS_READY_MASK 0x0080 |
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*addr = (FPW) 0x00500050; /* clear status register */ |
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/* this sends the clear lock bit command */ |
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*addr = (FPW) 0x00600060; |
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*addr = (FPW) 0x00D000D0; |
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} |
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/*-----------------------------------------------------------------------
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*/ |
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int flash_erase (flash_info_t * info, int s_first, int s_last) |
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{ |
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int flag, prot, sect; |
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ulong type, start; |
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int rcode = 0; |
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if ((s_first < 0) || (s_first > s_last)) { |
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if (info->flash_id == FLASH_UNKNOWN) { |
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printf ("- missing\n"); |
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} else { |
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printf ("- no sectors to erase\n"); |
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} |
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return 1; |
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} |
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type = (info->flash_id & FLASH_VENDMASK); |
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if ((type != FLASH_MAN_INTEL)) { |
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printf ("Can't erase unknown flash type %08lx - aborted\n", |
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info->flash_id); |
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return 1; |
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} |
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prot = 0; |
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for (sect = s_first; sect <= s_last; ++sect) { |
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if (info->protect[sect]) { |
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prot++; |
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} |
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} |
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if (prot) { |
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printf ("- Warning: %d protected sectors will not be erased!\n", |
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prot); |
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} else { |
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printf ("\n"); |
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} |
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/* Disable interrupts which might cause a timeout here */ |
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flag = disable_interrupts (); |
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/* Start erase on unprotected sectors */ |
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for (sect = s_first; sect <= s_last; sect++) { |
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if (info->protect[sect] == 0) { /* not protected */ |
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FPWV *addr = (FPWV *) (info->start[sect]); |
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FPW status; |
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printf ("Erasing sector %2d ... ", sect); |
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flash_unprotect_sectors (addr); |
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/* arm simple, non interrupt dependent timer */ |
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start = get_timer(0); |
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*addr = (FPW) 0x00500050;/* clear status register */ |
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*addr = (FPW) 0x00200020;/* erase setup */ |
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*addr = (FPW) 0x00D000D0;/* erase confirm */ |
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while (((status = |
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*addr) & (FPW) 0x00800080) != |
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(FPW) 0x00800080) { |
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if (get_timer(start) > |
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CONFIG_SYS_FLASH_ERASE_TOUT) { |
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printf ("Timeout\n"); |
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/* suspend erase */ |
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*addr = (FPW) 0x00B000B0; |
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/* reset to read mode */ |
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*addr = (FPW) 0x00FF00FF; |
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rcode = 1; |
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break; |
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} |
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} |
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/* clear status register cmd. */ |
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*addr = (FPW) 0x00500050; |
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*addr = (FPW) 0x00FF00FF;/* resest to read mode */ |
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printf (" done\n"); |
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} |
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} |
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if (flag) |
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enable_interrupts(); |
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return rcode; |
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} |
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/*-----------------------------------------------------------------------
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* Copy memory to flash, returns: |
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* 0 - OK |
|
||||||
* 1 - write timeout |
|
||||||
* 2 - Flash not erased |
|
||||||
* 4 - Flash not identified |
|
||||||
*/ |
|
||||||
|
|
||||||
int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) |
|
||||||
{ |
|
||||||
ulong cp, wp; |
|
||||||
FPW data; |
|
||||||
int count, i, l, rc, port_width; |
|
||||||
|
|
||||||
if (info->flash_id == FLASH_UNKNOWN) { |
|
||||||
return 4; |
|
||||||
} |
|
||||||
/* get lower word aligned address */ |
|
||||||
#ifdef FLASH_PORT_WIDTH16 |
|
||||||
wp = (addr & ~1); |
|
||||||
port_width = 2; |
|
||||||
#else |
|
||||||
wp = (addr & ~3); |
|
||||||
port_width = 4; |
|
||||||
#endif |
|
||||||
|
|
||||||
/*
|
|
||||||
* handle unaligned start bytes |
|
||||||
*/ |
|
||||||
if ((l = addr - wp) != 0) { |
|
||||||
data = 0; |
|
||||||
for (i = 0, cp = wp; i < l; ++i, ++cp) { |
|
||||||
data = (data << 8) | (*(uchar *) cp); |
|
||||||
} |
|
||||||
for (; i < port_width && cnt > 0; ++i) { |
|
||||||
data = (data << 8) | *src++; |
|
||||||
--cnt; |
|
||||||
++cp; |
|
||||||
} |
|
||||||
for (; cnt == 0 && i < port_width; ++i, ++cp) { |
|
||||||
data = (data << 8) | (*(uchar *) cp); |
|
||||||
} |
|
||||||
|
|
||||||
if ((rc = write_data (info, wp, SWAP (data))) != 0) { |
|
||||||
return (rc); |
|
||||||
} |
|
||||||
wp += port_width; |
|
||||||
} |
|
||||||
|
|
||||||
/*
|
|
||||||
* handle word aligned part |
|
||||||
*/ |
|
||||||
count = 0; |
|
||||||
while (cnt >= port_width) { |
|
||||||
data = 0; |
|
||||||
for (i = 0; i < port_width; ++i) { |
|
||||||
data = (data << 8) | *src++; |
|
||||||
} |
|
||||||
if ((rc = write_data (info, wp, SWAP (data))) != 0) { |
|
||||||
return (rc); |
|
||||||
} |
|
||||||
wp += port_width; |
|
||||||
cnt -= port_width; |
|
||||||
if (count++ > 0x800) { |
|
||||||
spin_wheel (); |
|
||||||
count = 0; |
|
||||||
} |
|
||||||
} |
|
||||||
|
|
||||||
if (cnt == 0) { |
|
||||||
return (0); |
|
||||||
} |
|
||||||
|
|
||||||
/*
|
|
||||||
* handle unaligned tail bytes |
|
||||||
*/ |
|
||||||
data = 0; |
|
||||||
for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) { |
|
||||||
data = (data << 8) | *src++; |
|
||||||
--cnt; |
|
||||||
} |
|
||||||
for (; i < port_width; ++i, ++cp) { |
|
||||||
data = (data << 8) | (*(uchar *) cp); |
|
||||||
} |
|
||||||
|
|
||||||
return (write_data (info, wp, SWAP (data))); |
|
||||||
} |
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
* Write a word or halfword to Flash, returns: |
|
||||||
* 0 - OK |
|
||||||
* 1 - write timeout |
|
||||||
* 2 - Flash not erased |
|
||||||
*/ |
|
||||||
static int write_data (flash_info_t * info, ulong dest, FPW data) |
|
||||||
{ |
|
||||||
FPWV *addr = (FPWV *) dest; |
|
||||||
ulong status; |
|
||||||
int flag, rc = 0; |
|
||||||
ulong start; |
|
||||||
|
|
||||||
/* Check if Flash is (sufficiently) erased */ |
|
||||||
if ((*addr & data) != data) { |
|
||||||
printf("not erased at %08lx (%x)\n", (ulong) addr, *addr); |
|
||||||
return 2; |
|
||||||
} |
|
||||||
/* Disable interrupts which might cause a timeout here */ |
|
||||||
flag = disable_interrupts (); |
|
||||||
*addr = (FPW) 0x00400040; /* write setup */ |
|
||||||
*addr = data; |
|
||||||
|
|
||||||
/* arm simple, non interrupt dependent timer */ |
|
||||||
start = get_timer(0); |
|
||||||
|
|
||||||
/* wait while polling the status register */ |
|
||||||
while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { |
|
||||||
if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { |
|
||||||
rc = 1; |
|
||||||
goto done; |
|
||||||
} |
|
||||||
} |
|
||||||
done: |
|
||||||
if (flag) |
|
||||||
enable_interrupts(); |
|
||||||
|
|
||||||
*addr = (FPW) 0x00FF00FF; /* restore read mode */ |
|
||||||
return rc; |
|
||||||
} |
|
||||||
|
|
||||||
void inline spin_wheel (void) |
|
||||||
{ |
|
||||||
static int p = 0; |
|
||||||
static char w[] = "\\/-"; |
|
||||||
|
|
||||||
printf ("\010%c", w[p]); |
|
||||||
(++p == 3) ? (p = 0) : 0; |
|
||||||
} |
|
@ -1,452 +0,0 @@ |
|||||||
/* |
|
||||||
* Board specific setup info |
|
||||||
* |
|
||||||
* (C) Copyright 2003 |
|
||||||
* Texas Instruments, <www.ti.com> |
|
||||||
* Kshitij Gupta <Kshitij@ti.com>
|
|
||||||
* |
|
||||||
* Modified for OMAP 1610 H2 board by Nishant Kamat, Jan 2004 |
|
||||||
* |
|
||||||
* See file CREDITS for list of people who contributed to this |
|
||||||
* project. |
|
||||||
* |
|
||||||
* This program is free software; you can redistribute it and/or
|
|
||||||
* modify it under the terms of the GNU General Public License as |
|
||||||
* published by the Free Software Foundation; either version 2 of
|
|
||||||
* the License, or (at your option) any later version. |
|
||||||
* |
|
||||||
* This program is distributed in the hope that it will be useful, |
|
||||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
||||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
||||||
* GNU General Public License for more details. |
|
||||||
* |
|
||||||
* You should have received a copy of the GNU General Public License |
|
||||||
* along with this program; if not, write to the Free Software
|
|
||||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
|
||||||
* MA 02111-1307 USA |
|
||||||
*/ |
|
||||||
|
|
||||||
#include <config.h> |
|
||||||
#include <version.h> |
|
||||||
|
|
||||||
#if defined(CONFIG_OMAP1610) |
|
||||||
#include <./configs/omap1510.h> |
|
||||||
#endif |
|
||||||
|
|
||||||
|
|
||||||
_TEXT_BASE: |
|
||||||
.word CONFIG_SYS_TEXT_BASE /* sdram load addr from config.mk */ |
|
||||||
|
|
||||||
.globl lowlevel_init
|
|
||||||
lowlevel_init: |
|
||||||
|
|
||||||
|
|
||||||
/*------------------------------------------------------* |
|
||||||
*mask all IRQs by setting all bits in the INTMR default* |
|
||||||
*------------------------------------------------------*/ |
|
||||||
mov r1, #0xffffffff |
|
||||||
ldr r0, =REG_IHL1_MIR |
|
||||||
str r1, [r0] |
|
||||||
ldr r0, =REG_IHL2_MIR |
|
||||||
str r1, [r0] |
|
||||||
|
|
||||||
/*------------------------------------------------------* |
|
||||||
* Set up ARM CLM registers (IDLECT1) * |
|
||||||
*------------------------------------------------------*/ |
|
||||||
ldr r0, REG_ARM_IDLECT1 |
|
||||||
ldr r1, VAL_ARM_IDLECT1 |
|
||||||
str r1, [r0] |
|
||||||
|
|
||||||
/*------------------------------------------------------* |
|
||||||
* Set up ARM CLM registers (IDLECT2) * |
|
||||||
*------------------------------------------------------*/ |
|
||||||
ldr r0, REG_ARM_IDLECT2 |
|
||||||
ldr r1, VAL_ARM_IDLECT2 |
|
||||||
str r1, [r0] |
|
||||||
|
|
||||||
/*------------------------------------------------------* |
|
||||||
* Set up ARM CLM registers (IDLECT3) * |
|
||||||
*------------------------------------------------------*/ |
|
||||||
ldr r0, REG_ARM_IDLECT3 |
|
||||||
ldr r1, VAL_ARM_IDLECT3 |
|
||||||
str r1, [r0] |
|
||||||
|
|
||||||
#ifdef CONFIG_CS_AUTOBOOT /* do the setup depending on boot mode */ |
|
||||||
ldr r0, CONF_STATUS |
|
||||||
ldr r1, [r0] |
|
||||||
tst r1, #0x02 |
|
||||||
beq disable_wd /* booting from RAM, skip setup */ |
|
||||||
#endif |
|
||||||
|
|
||||||
mov r1, #0x01 /* PER_EN bit */ |
|
||||||
ldr r0, REG_ARM_RSTCT2 |
|
||||||
strh r1, [r0] /* CLKM; Peripheral reset. */
|
|
||||||
|
|
||||||
/* Set CLKM to Sync-Scalable */ |
|
||||||
/* I supposedly need to enable the dsp clock before switching */ |
|
||||||
mov r1, #0x0000 |
|
||||||
ldr r0, REG_ARM_SYSST |
|
||||||
strh r1, [r0] |
|
||||||
mov r0, #0x400 |
|
||||||
1: |
|
||||||
subs r0, r0, #0x1 /* wait for any bubbles to finish */ |
|
||||||
bne 1b |
|
||||||
ldr r1, VAL_ARM_CKCTL |
|
||||||
ldr r0, REG_ARM_CKCTL |
|
||||||
strh r1, [r0] |
|
||||||
|
|
||||||
/* a few nops to let settle */ |
|
||||||
nop |
|
||||||
nop |
|
||||||
nop |
|
||||||
nop |
|
||||||
nop |
|
||||||
nop |
|
||||||
nop |
|
||||||
nop |
|
||||||
nop |
|
||||||
nop |
|
||||||
|
|
||||||
/* setup DPLL 1 */ |
|
||||||
/* Ramp up the clock to 96Mhz */ |
|
||||||
ldr r1, VAL_DPLL1_CTL |
|
||||||
ldr r0, REG_DPLL1_CTL |
|
||||||
strh r1, [r0] |
|
||||||
ands r1, r1, #0x10 /* Check if PLL is enabled. */ |
|
||||||
beq lock_end /* Do not look for lock if BYPASS selected */ |
|
||||||
2: |
|
||||||
ldrh r1, [r0] |
|
||||||
ands r1, r1, #0x01 /* Check the LOCK bit.*/ |
|
||||||
beq 2b /* loop until bit goes hi. */ |
|
||||||
lock_end: |
|
||||||
|
|
||||||
|
|
||||||
/*------------------------------------------------------* |
|
||||||
* Turn off the watchdog during init... * |
|
||||||
*------------------------------------------------------*/ |
|
||||||
disable_wd: |
|
||||||
ldr r0, REG_WATCHDOG |
|
||||||
ldr r1, WATCHDOG_VAL1 |
|
||||||
str r1, [r0] |
|
||||||
ldr r1, WATCHDOG_VAL2 |
|
||||||
str r1, [r0] |
|
||||||
ldr r0, REG_WSPRDOG |
|
||||||
ldr r1, WSPRDOG_VAL1 |
|
||||||
str r1, [r0] |
|
||||||
ldr r0, REG_WWPSDOG |
|
||||||
|
|
||||||
watch1Wait: |
|
||||||
ldr r1, [r0] |
|
||||||
tst r1, #0x10 |
|
||||||
bne watch1Wait |
|
||||||
|
|
||||||
ldr r0, REG_WSPRDOG |
|
||||||
ldr r1, WSPRDOG_VAL2 |
|
||||||
str r1, [r0] |
|
||||||
ldr r0, REG_WWPSDOG |
|
||||||
watch2Wait: |
|
||||||
ldr r1, [r0] |
|
||||||
tst r1, #0x10 |
|
||||||
bne watch2Wait |
|
||||||
|
|
||||||
|
|
||||||
/* Set memory timings corresponding to the new clock speed */ |
|
||||||
|
|
||||||
/* Check execution location to determine current execution location |
|
||||||
* and branch to appropriate initialization code. |
|
||||||
*/ |
|
||||||
/* Load physical SDRAM base. */ |
|
||||||
mov r0, #0x10000000 |
|
||||||
/* Get current execution location. */ |
|
||||||
mov r1, pc |
|
||||||
/* Compare. */ |
|
||||||
cmp r1, r0 |
|
||||||
/* Skip over EMIF-fast initialization if running from SDRAM. */ |
|
||||||
bge skip_sdram |
|
||||||
|
|
||||||
/* |
|
||||||
* Delay for SDRAM initialization. |
|
||||||
*/ |
|
||||||
mov r3, #0x1800 /* value should be checked */ |
|
||||||
3: |
|
||||||
subs r3, r3, #0x1 /* Decrement count */ |
|
||||||
bne 3b |
|
||||||
|
|
||||||
|
|
||||||
/* |
|
||||||
* Set SDRAM control values. Disable refresh before MRS command. |
|
||||||
*/ |
|
||||||
|
|
||||||
/* mobile ddr operation */ |
|
||||||
ldr r0, REG_SDRAM_OPERATION |
|
||||||
mov r2, #07 |
|
||||||
str r2, [r0] |
|
||||||
|
|
||||||
/* config register */ |
|
||||||
ldr r0, REG_SDRAM_CONFIG |
|
||||||
ldr r1, SDRAM_CONFIG_VAL |
|
||||||
str r1, [r0] |
|
||||||
|
|
||||||
/* manual command register */ |
|
||||||
ldr r0, REG_SDRAM_MANUAL_CMD |
|
||||||
/* issue set cke high */ |
|
||||||
mov r1, #CMD_SDRAM_CKE_SET_HIGH |
|
||||||
str r1, [r0] |
|
||||||
/* issue nop */ |
|
||||||
mov r1, #CMD_SDRAM_NOP |
|
||||||
str r1, [r0] |
|
||||||
|
|
||||||
mov r2, #0x0100 |
|
||||||
waitMDDR1: |
|
||||||
subs r2, r2, #1 |
|
||||||
bne waitMDDR1 /* delay loop */ |
|
||||||
|
|
||||||
/* issue precharge */ |
|
||||||
mov r1, #CMD_SDRAM_PRECHARGE |
|
||||||
str r1, [r0] |
|
||||||
|
|
||||||
/* issue autorefresh x 2 */ |
|
||||||
mov r1, #CMD_SDRAM_AUTOREFRESH |
|
||||||
str r1, [r0] |
|
||||||
str r1, [r0] |
|
||||||
|
|
||||||
/* mrs register ddr mobile */ |
|
||||||
ldr r0, REG_SDRAM_MRS |
|
||||||
mov r1, #0x33 |
|
||||||
str r1, [r0] |
|
||||||
|
|
||||||
/* emrs1 low-power register */ |
|
||||||
ldr r0, REG_SDRAM_EMRS1 |
|
||||||
/* self refresh on all banks */ |
|
||||||
mov r1, #0 |
|
||||||
str r1, [r0] |
|
||||||
|
|
||||||
ldr r0, REG_DLL_URD_CONTROL |
|
||||||
ldr r1, DLL_URD_CONTROL_VAL |
|
||||||
str r1, [r0] |
|
||||||
|
|
||||||
ldr r0, REG_DLL_LRD_CONTROL |
|
||||||
ldr r1, DLL_LRD_CONTROL_VAL |
|
||||||
str r1, [r0] |
|
||||||
|
|
||||||
ldr r0, REG_DLL_WRT_CONTROL |
|
||||||
ldr r1, DLL_WRT_CONTROL_VAL |
|
||||||
str r1, [r0] |
|
||||||
|
|
||||||
/* delay loop */ |
|
||||||
mov r2, #0x0100 |
|
||||||
waitMDDR2: |
|
||||||
subs r2, r2, #1 |
|
||||||
bne waitMDDR2 |
|
||||||
|
|
||||||
/* |
|
||||||
* Delay for SDRAM initialization. |
|
||||||
*/ |
|
||||||
mov r3, #0x1800 |
|
||||||
4: |
|
||||||
subs r3, r3, #1 /* Decrement count. */ |
|
||||||
bne 4b |
|
||||||
b common_tc |
|
||||||
|
|
||||||
skip_sdram: |
|
||||||
|
|
||||||
ldr r0, REG_SDRAM_CONFIG |
|
||||||
ldr r1, SDRAM_CONFIG_VAL |
|
||||||
str r1, [r0] |
|
||||||
|
|
||||||
common_tc: |
|
||||||
/* slow interface */ |
|
||||||
ldr r1, VAL_TC_EMIFS_CS0_CONFIG |
|
||||||
ldr r0, REG_TC_EMIFS_CS0_CONFIG |
|
||||||
str r1, [r0] /* Chip Select 0 */ |
|
||||||
|
|
||||||
ldr r1, VAL_TC_EMIFS_CS1_CONFIG |
|
||||||
ldr r0, REG_TC_EMIFS_CS1_CONFIG |
|
||||||
str r1, [r0] /* Chip Select 1 */ |
|
||||||
ldr r1, VAL_TC_EMIFS_CS3_CONFIG |
|
||||||
ldr r0, REG_TC_EMIFS_CS3_CONFIG |
|
||||||
str r1, [r0] /* Chip Select 3 */ |
|
||||||
|
|
||||||
#ifdef CONFIG_H2_OMAP1610 |
|
||||||
/* inserting additional 2 clock cycle hold time for LAN */ |
|
||||||
ldr r0, REG_TC_EMIFS_CS1_ADVANCED |
|
||||||
ldr r1, VAL_TC_EMIFS_CS1_ADVANCED |
|
||||||
str r1, [r0] |
|
||||||
#endif |
|
||||||
/* Start MPU Timer 1 */ |
|
||||||
ldr r0, REG_MPU_LOAD_TIMER |
|
||||||
ldr r1, VAL_MPU_LOAD_TIMER |
|
||||||
str r1, [r0] |
|
||||||
|
|
||||||
ldr r0, REG_MPU_CNTL_TIMER |
|
||||||
ldr r1, VAL_MPU_CNTL_TIMER |
|
||||||
str r1, [r0] |
|
||||||
|
|
||||||
/* back to arch calling code */ |
|
||||||
mov pc, lr |
|
||||||
|
|
||||||
/* the literal pools origin */ |
|
||||||
.ltorg |
|
||||||
|
|
||||||
#ifdef CONFIG_CS_AUTOBOOT |
|
||||||
CONF_STATUS: |
|
||||||
.word 0xfffe1130 /* 32 bits */ |
|
||||||
#endif |
|
||||||
|
|
||||||
REG_TC_EMIFS_CONFIG: /* 32 bits */ |
|
||||||
.word 0xfffecc0c
|
|
||||||
REG_TC_EMIFS_CS0_CONFIG: /* 32 bits */ |
|
||||||
.word 0xfffecc10
|
|
||||||
REG_TC_EMIFS_CS1_CONFIG: /* 32 bits */ |
|
||||||
.word 0xfffecc14
|
|
||||||
REG_TC_EMIFS_CS2_CONFIG: /* 32 bits */ |
|
||||||
.word 0xfffecc18
|
|
||||||
REG_TC_EMIFS_CS3_CONFIG: /* 32 bits */ |
|
||||||
.word 0xfffecc1c
|
|
||||||
|
|
||||||
#ifdef CONFIG_H2_OMAP1610 |
|
||||||
REG_TC_EMIFS_CS1_ADVANCED: /* 32 bits */ |
|
||||||
.word 0xfffecc54
|
|
||||||
#endif |
|
||||||
|
|
||||||
/* MPU clock/reset/power mode control registers */ |
|
||||||
REG_ARM_CKCTL: /* 16 bits */ |
|
||||||
.word 0xfffece00
|
|
||||||
|
|
||||||
REG_ARM_IDLECT3: /* 16 bits */ |
|
||||||
.word 0xfffece24
|
|
||||||
REG_ARM_IDLECT2: /* 16 bits */ |
|
||||||
.word 0xfffece08
|
|
||||||
REG_ARM_IDLECT1: /* 16 bits */ |
|
||||||
.word 0xfffece04
|
|
||||||
|
|
||||||
REG_ARM_RSTCT2: /* 16 bits */ |
|
||||||
.word 0xfffece14
|
|
||||||
REG_ARM_SYSST: /* 16 bits */ |
|
||||||
.word 0xfffece18
|
|
||||||
/* DPLL control registers */ |
|
||||||
REG_DPLL1_CTL: /* 16 bits */ |
|
||||||
.word 0xfffecf00
|
|
||||||
|
|
||||||
/* Watch Dog register */ |
|
||||||
/* secure watchdog stop */ |
|
||||||
REG_WSPRDOG: |
|
||||||
.word 0xfffeb048
|
|
||||||
/* watchdog write pending */ |
|
||||||
REG_WWPSDOG: |
|
||||||
.word 0xfffeb034
|
|
||||||
|
|
||||||
WSPRDOG_VAL1: |
|
||||||
.word 0x0000aaaa
|
|
||||||
WSPRDOG_VAL2: |
|
||||||
.word 0x00005555
|
|
||||||
|
|
||||||
/* SDRAM config is: auto refresh enabled, 16 bit 4 bank, |
|
||||||
counter @8192 rows, 10 ns, 8 burst */
|
|
||||||
REG_SDRAM_CONFIG: |
|
||||||
.word 0xfffecc20
|
|
||||||
|
|
||||||
/* Operation register */ |
|
||||||
REG_SDRAM_OPERATION: |
|
||||||
.word 0xfffecc80
|
|
||||||
|
|
||||||
/* Manual command register */ |
|
||||||
REG_SDRAM_MANUAL_CMD: |
|
||||||
.word 0xfffecc84
|
|
||||||
|
|
||||||
/* SDRAM MRS (New) config is: CAS latency is 2, burst length 8 */ |
|
||||||
REG_SDRAM_MRS: |
|
||||||
.word 0xfffecc70
|
|
||||||
|
|
||||||
/* SDRAM MRS (New) config is: CAS latency is 2, burst length 8 */ |
|
||||||
REG_SDRAM_EMRS1: |
|
||||||
.word 0xfffecc78
|
|
||||||
|
|
||||||
/* WRT DLL register */ |
|
||||||
REG_DLL_WRT_CONTROL: |
|
||||||
.word 0xfffecc68
|
|
||||||
DLL_WRT_CONTROL_VAL: |
|
||||||
.word 0x03f00002
|
|
||||||
|
|
||||||
/* URD DLL register */ |
|
||||||
REG_DLL_URD_CONTROL: |
|
||||||
.word 0xfffeccc0
|
|
||||||
DLL_URD_CONTROL_VAL: |
|
||||||
.word 0x00800002
|
|
||||||
|
|
||||||
/* LRD DLL register */ |
|
||||||
REG_DLL_LRD_CONTROL: |
|
||||||
.word 0xfffecccc
|
|
||||||
|
|
||||||
REG_WATCHDOG: |
|
||||||
.word 0xfffec808
|
|
||||||
|
|
||||||
REG_MPU_LOAD_TIMER: |
|
||||||
.word 0xfffec504
|
|
||||||
REG_MPU_CNTL_TIMER: |
|
||||||
.word 0xfffec500
|
|
||||||
|
|
||||||
/* 96 MHz Samsung Mobile DDR */ |
|
||||||
SDRAM_CONFIG_VAL: |
|
||||||
.word 0x001200f4
|
|
||||||
|
|
||||||
DLL_LRD_CONTROL_VAL: |
|
||||||
.word 0x00800002
|
|
||||||
|
|
||||||
VAL_ARM_CKCTL: |
|
||||||
.word 0x3000
|
|
||||||
VAL_DPLL1_CTL: |
|
||||||
.word 0x2830
|
|
||||||
|
|
||||||
#ifdef CONFIG_INNOVATOROMAP1610 |
|
||||||
VAL_TC_EMIFS_CS0_CONFIG: |
|
||||||
.word 0x002130b0
|
|
||||||
VAL_TC_EMIFS_CS1_CONFIG: |
|
||||||
.word 0x00001131
|
|
||||||
VAL_TC_EMIFS_CS2_CONFIG: |
|
||||||
.word 0x000055f0
|
|
||||||
VAL_TC_EMIFS_CS3_CONFIG: |
|
||||||
.word 0x88011131
|
|
||||||
#endif |
|
||||||
|
|
||||||
#ifdef CONFIG_H2_OMAP1610 |
|
||||||
VAL_TC_EMIFS_CS0_CONFIG: |
|
||||||
.word 0x00203331
|
|
||||||
VAL_TC_EMIFS_CS1_CONFIG: |
|
||||||
.word 0x8180fff3
|
|
||||||
VAL_TC_EMIFS_CS2_CONFIG: |
|
||||||
.word 0xf800f22a
|
|
||||||
VAL_TC_EMIFS_CS3_CONFIG: |
|
||||||
.word 0x88011131
|
|
||||||
VAL_TC_EMIFS_CS1_ADVANCED: |
|
||||||
.word 0x00000022
|
|
||||||
#endif |
|
||||||
|
|
||||||
VAL_TC_EMIFF_SDRAM_CONFIG: |
|
||||||
.word 0x010290fc
|
|
||||||
VAL_TC_EMIFF_MRS: |
|
||||||
.word 0x00000027
|
|
||||||
|
|
||||||
VAL_ARM_IDLECT1: |
|
||||||
.word 0x00000400
|
|
||||||
|
|
||||||
VAL_ARM_IDLECT2: |
|
||||||
.word 0x00000886
|
|
||||||
VAL_ARM_IDLECT3: |
|
||||||
.word 0x00000015
|
|
||||||
|
|
||||||
WATCHDOG_VAL1: |
|
||||||
.word 0x000000f5
|
|
||||||
WATCHDOG_VAL2: |
|
||||||
.word 0x000000a0
|
|
||||||
|
|
||||||
VAL_MPU_LOAD_TIMER: |
|
||||||
.word 0xffffffff
|
|
||||||
VAL_MPU_CNTL_TIMER: |
|
||||||
.word 0xffffffa1
|
|
||||||
|
|
||||||
/* command values */ |
|
||||||
.equ CMD_SDRAM_NOP, 0x00000000 |
|
||||||
.equ CMD_SDRAM_PRECHARGE, 0x00000001 |
|
||||||
.equ CMD_SDRAM_AUTOREFRESH, 0x00000002 |
|
||||||
.equ CMD_SDRAM_CKE_SET_HIGH, 0x00000007 |
|
@ -1,309 +0,0 @@ |
|||||||
/*
|
|
||||||
* (C) Copyright 2002 |
|
||||||
* Sysgo Real-Time Solutions, GmbH <www.elinos.com> |
|
||||||
* Marius Groeger <mgroeger@sysgo.de> |
|
||||||
* |
|
||||||
* (C) Copyright 2002 |
|
||||||
* David Mueller, ELSOFT AG, <d.mueller@elsoft.ch> |
|
||||||
* |
|
||||||
* (C) Copyright 2003 |
|
||||||
* Texas Instruments, <www.ti.com> |
|
||||||
* Kshitij Gupta <Kshitij@ti.com> |
|
||||||
* |
|
||||||
* Modified for OMAP 1610 H2 board by Nishant Kamat, Jan 2004 |
|
||||||
* |
|
||||||
* See file CREDITS for list of people who contributed to this |
|
||||||
* project. |
|
||||||
* |
|
||||||
* This program is free software; you can redistribute it and/or |
|
||||||
* modify it under the terms of the GNU General Public License as |
|
||||||
* published by the Free Software Foundation; either version 2 of |
|
||||||
* the License, or (at your option) any later version. |
|
||||||
* |
|
||||||
* This program is distributed in the hope that it will be useful, |
|
||||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
||||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
||||||
* GNU General Public License for more details. |
|
||||||
* |
|
||||||
* You should have received a copy of the GNU General Public License |
|
||||||
* along with this program; if not, write to the Free Software |
|
||||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
|
||||||
* MA 02111-1307 USA |
|
||||||
*/ |
|
||||||
|
|
||||||
#include <common.h> |
|
||||||
#include <netdev.h> |
|
||||||
#if defined(CONFIG_OMAP1610) |
|
||||||
#include <./configs/omap1510.h> |
|
||||||
#endif |
|
||||||
|
|
||||||
DECLARE_GLOBAL_DATA_PTR; |
|
||||||
|
|
||||||
#ifdef CONFIG_CS_AUTOBOOT |
|
||||||
unsigned long omap_flash_base; |
|
||||||
#endif |
|
||||||
|
|
||||||
void flash__init (void); |
|
||||||
void ether__init (void); |
|
||||||
void set_muxconf_regs (void); |
|
||||||
void peripheral_power_enable (void); |
|
||||||
|
|
||||||
#define COMP_MODE_ENABLE ((unsigned int)0x0000EAEF) |
|
||||||
|
|
||||||
static inline void delay (unsigned long loops) |
|
||||||
{ |
|
||||||
__asm__ volatile ("1:\n" |
|
||||||
"subs %0, %1, #1\n" |
|
||||||
"bne 1b":"=r" (loops):"0" (loops)); |
|
||||||
} |
|
||||||
|
|
||||||
/*
|
|
||||||
* Miscellaneous platform dependent initialisations |
|
||||||
*/ |
|
||||||
|
|
||||||
int board_init (void) |
|
||||||
{ |
|
||||||
/* adress of boot parameters */ |
|
||||||
gd->bd->bi_boot_params = 0x10000100; |
|
||||||
|
|
||||||
/* Configure MUX settings */ |
|
||||||
set_muxconf_regs (); |
|
||||||
peripheral_power_enable (); |
|
||||||
|
|
||||||
/* this speeds up your boot a quite a bit. However to make it
|
|
||||||
* work, you need make sure your kernel startup flush bug is fixed. |
|
||||||
* ... rkw ... |
|
||||||
*/ |
|
||||||
icache_enable (); |
|
||||||
|
|
||||||
flash__init (); |
|
||||||
ether__init (); |
|
||||||
return 0; |
|
||||||
} |
|
||||||
|
|
||||||
|
|
||||||
int misc_init_r (void) |
|
||||||
{ |
|
||||||
/* currently empty */ |
|
||||||
return (0); |
|
||||||
} |
|
||||||
|
|
||||||
/******************************
|
|
||||||
Routine: |
|
||||||
Description: |
|
||||||
******************************/ |
|
||||||
void flash__init (void) |
|
||||||
{ |
|
||||||
#define EMIFS_GlB_Config_REG 0xfffecc0c |
|
||||||
unsigned int regval; |
|
||||||
|
|
||||||
#ifdef CONFIG_CS_AUTOBOOT |
|
||||||
/* Check swapping of CS0 and CS3, set flash base accordingly */ |
|
||||||
omap_flash_base = ((*((u32 *)OMAP_EMIFS_CONFIG_REG) & 0x02) == 0) ? |
|
||||||
PHYS_FLASH_1_BM0 : PHYS_FLASH_1_BM1; |
|
||||||
#endif |
|
||||||
regval = *((volatile unsigned int *) EMIFS_GlB_Config_REG); |
|
||||||
/* Turn off write protection for flash devices. */ |
|
||||||
regval = regval | 0x0001; |
|
||||||
*((volatile unsigned int *) EMIFS_GlB_Config_REG) = regval; |
|
||||||
} |
|
||||||
/*************************************************************
|
|
||||||
Routine:ether__init |
|
||||||
Description: take the Ethernet controller out of reset and wait |
|
||||||
for the EEPROM load to complete. |
|
||||||
*************************************************************/ |
|
||||||
void ether__init (void) |
|
||||||
{ |
|
||||||
#define ETH_CONTROL_REG 0x0400030b |
|
||||||
|
|
||||||
#ifdef CONFIG_H2_OMAP1610 |
|
||||||
#define LAN_RESET_REGISTER 0x0400001c |
|
||||||
|
|
||||||
/* The debug board on which the lan chip resides may not be powered
|
|
||||||
* ON at the same time as the OMAP chip. So wait in a loop until the |
|
||||||
* lan reset register (on the debug board) is available (powered on) |
|
||||||
* and reset the lan chip. |
|
||||||
*/ |
|
||||||
|
|
||||||
*((volatile unsigned short *) LAN_RESET_REGISTER) = 0x0000; |
|
||||||
do { |
|
||||||
*((volatile unsigned short *) LAN_RESET_REGISTER) = 0x0001; |
|
||||||
udelay (3); |
|
||||||
} while (*((volatile unsigned short *) LAN_RESET_REGISTER) != 0x0001); |
|
||||||
|
|
||||||
do { |
|
||||||
*((volatile unsigned short *) LAN_RESET_REGISTER) = 0x0000; |
|
||||||
udelay (3); |
|
||||||
} while (*((volatile unsigned short *) LAN_RESET_REGISTER) != 0x0000); |
|
||||||
#endif |
|
||||||
|
|
||||||
*((volatile unsigned char *) ETH_CONTROL_REG) &= ~0x01; |
|
||||||
udelay (3); |
|
||||||
} |
|
||||||
|
|
||||||
/******************************
|
|
||||||
Routine: |
|
||||||
Description: |
|
||||||
******************************/ |
|
||||||
int dram_init (void) |
|
||||||
{ |
|
||||||
gd->bd->bi_dram[0].start = PHYS_SDRAM_1; |
|
||||||
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; |
|
||||||
|
|
||||||
return 0; |
|
||||||
} |
|
||||||
|
|
||||||
/******************************************************
|
|
||||||
Routine: set_muxconf_regs |
|
||||||
Description: Setting up the configuration Mux registers |
|
||||||
specific to the hardware |
|
||||||
*******************************************************/ |
|
||||||
void set_muxconf_regs (void) |
|
||||||
{ |
|
||||||
volatile unsigned int *MuxConfReg; |
|
||||||
/* set each registers to its reset value; */ |
|
||||||
MuxConfReg = |
|
||||||
(volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_0); |
|
||||||
/* setup for UART1 */ |
|
||||||
*MuxConfReg &= ~(0x02000000); /* bit 25 */ |
|
||||||
/* setup for UART2 */ |
|
||||||
*MuxConfReg &= ~(0x01000000); /* bit 24 */ |
|
||||||
/* Disable Uwire CS Hi-Z */ |
|
||||||
*MuxConfReg |= 0x08000000; |
|
||||||
MuxConfReg = |
|
||||||
(volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_3); |
|
||||||
*MuxConfReg = 0x00000000; |
|
||||||
MuxConfReg = |
|
||||||
(volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_4); |
|
||||||
*MuxConfReg = 0x00000000; |
|
||||||
MuxConfReg = |
|
||||||
(volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_5); |
|
||||||
*MuxConfReg = 0x00000000; |
|
||||||
MuxConfReg = |
|
||||||
(volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_6); |
|
||||||
/*setup mux for UART3 */ |
|
||||||
*MuxConfReg |= 0x00000001; /* bit3, 1, 0 (mux0 5,5,26) */ |
|
||||||
*MuxConfReg &= ~0x0000003e; |
|
||||||
MuxConfReg = |
|
||||||
(volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_7); |
|
||||||
*MuxConfReg = 0x00000000; |
|
||||||
MuxConfReg = |
|
||||||
(volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_8); |
|
||||||
/* Disable Uwire CS Hi-Z */ |
|
||||||
*MuxConfReg |= 0x00001200; /*bit 9 for CS0 12 for CS3 */ |
|
||||||
MuxConfReg = |
|
||||||
(volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_9); |
|
||||||
/* Need to turn on bits 21 and 12 in FUNC_MUX_CTRL_9 so the */ |
|
||||||
/* hardware will actually use TX and RTS based on bit 25 in */ |
|
||||||
/* FUNC_MUX_CTRL_0. I told you this thing was screwy! */ |
|
||||||
*MuxConfReg |= 0x00201000; |
|
||||||
MuxConfReg = |
|
||||||
(volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_A); |
|
||||||
*MuxConfReg = 0x00000000; |
|
||||||
MuxConfReg = |
|
||||||
(volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_B); |
|
||||||
*MuxConfReg = 0x00000000; |
|
||||||
MuxConfReg = |
|
||||||
(volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_C); |
|
||||||
/* setup for UART2 */ |
|
||||||
/* Need to turn on bits 27 and 24 in FUNC_MUX_CTRL_C so the */ |
|
||||||
/* hardware will actually use TX and RTS based on bit 24 in */ |
|
||||||
/* FUNC_MUX_CTRL_0. */ |
|
||||||
*MuxConfReg |= 0x09000000; |
|
||||||
MuxConfReg = |
|
||||||
(volatile unsigned int *) ((unsigned int) PULL_DWN_CTRL_0); |
|
||||||
*MuxConfReg = 0x00000000; |
|
||||||
MuxConfReg = |
|
||||||
(volatile unsigned int *) ((unsigned int) PULL_DWN_CTRL_1); |
|
||||||
*MuxConfReg = 0x00000000; |
|
||||||
/* mux setup for SD/MMC driver */ |
|
||||||
MuxConfReg = |
|
||||||
(volatile unsigned int *) ((unsigned int) PULL_DWN_CTRL_2); |
|
||||||
*MuxConfReg &= 0xFFFE0FFF; |
|
||||||
MuxConfReg = |
|
||||||
(volatile unsigned int *) ((unsigned int) PULL_DWN_CTRL_3); |
|
||||||
*MuxConfReg = 0x00000000; |
|
||||||
MuxConfReg = |
|
||||||
(volatile unsigned int *) ((unsigned int) MOD_CONF_CTRL_0); |
|
||||||
/* bit 13 for MMC2 XOR_CLK */ |
|
||||||
*MuxConfReg &= ~(0x00002000); |
|
||||||
/* bit 29 for UART 1 */ |
|
||||||
*MuxConfReg &= ~(0x00002000); |
|
||||||
MuxConfReg = |
|
||||||
(volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_0); |
|
||||||
/* Configure for USB. Turn on VBUS_CTRL and VBUS_MODE. */ |
|
||||||
*MuxConfReg |= 0x000C0000; |
|
||||||
MuxConfReg = |
|
||||||
(volatile unsigned int *) ((unsigned int)USB_TRANSCEIVER_CTRL); |
|
||||||
*MuxConfReg &= ~(0x00000070); |
|
||||||
*MuxConfReg &= ~(0x00000008); |
|
||||||
*MuxConfReg |= 0x00000003; |
|
||||||
*MuxConfReg |= 0x00000180; |
|
||||||
MuxConfReg = |
|
||||||
(volatile unsigned int *) ((unsigned int) MOD_CONF_CTRL_0); |
|
||||||
/* bit 17, software controls VBUS */ |
|
||||||
*MuxConfReg &= ~(0x00020000); |
|
||||||
/* Enable USB 48 and 12M clocks */ |
|
||||||
*MuxConfReg |= 0x00000200; |
|
||||||
*MuxConfReg &= ~(0x00000180); |
|
||||||
/*2.75V for MMCSDIO1 */ |
|
||||||
MuxConfReg = |
|
||||||
(volatile unsigned int *) ((unsigned int) VOLTAGE_CTRL_0); |
|
||||||
*MuxConfReg = 0x00001FE7; |
|
||||||
MuxConfReg = |
|
||||||
(volatile unsigned int *) ((unsigned int) PU_PD_SEL_0); |
|
||||||
*MuxConfReg = 0x00000000; |
|
||||||
MuxConfReg = |
|
||||||
(volatile unsigned int *) ((unsigned int) PU_PD_SEL_1); |
|
||||||
*MuxConfReg = 0x00000000; |
|
||||||
MuxConfReg = |
|
||||||
(volatile unsigned int *) ((unsigned int) PU_PD_SEL_2); |
|
||||||
*MuxConfReg = 0x00000000; |
|
||||||
MuxConfReg = |
|
||||||
(volatile unsigned int *) ((unsigned int) PU_PD_SEL_3); |
|
||||||
*MuxConfReg = 0x00000000; |
|
||||||
MuxConfReg = |
|
||||||
(volatile unsigned int *) ((unsigned int) PU_PD_SEL_4); |
|
||||||
*MuxConfReg = 0x00000000; |
|
||||||
MuxConfReg = |
|
||||||
(volatile unsigned int *) ((unsigned int) PULL_DWN_CTRL_4); |
|
||||||
*MuxConfReg = 0x00000000; |
|
||||||
/* Turn on UART2 48 MHZ clock */ |
|
||||||
MuxConfReg = |
|
||||||
(volatile unsigned int *) ((unsigned int) MOD_CONF_CTRL_0); |
|
||||||
*MuxConfReg |= 0x40000000; |
|
||||||
MuxConfReg = |
|
||||||
(volatile unsigned int *) ((unsigned int) USB_OTG_CTRL); |
|
||||||
/* setup for USB VBus detection OMAP161x */ |
|
||||||
*MuxConfReg |= 0x00040000; /* bit 18 */ |
|
||||||
MuxConfReg = |
|
||||||
(volatile unsigned int *) ((unsigned int) PU_PD_SEL_2); |
|
||||||
/* PullUps for SD/MMC driver */ |
|
||||||
*MuxConfReg |= ~(0xFFFE0FFF); |
|
||||||
MuxConfReg = |
|
||||||
(volatile unsigned int *) ((unsigned int)COMP_MODE_CTRL_0); |
|
||||||
*MuxConfReg = COMP_MODE_ENABLE; |
|
||||||
} |
|
||||||
|
|
||||||
/******************************************************
|
|
||||||
Routine: peripheral_power_enable |
|
||||||
Description: Enable the power for UART1 |
|
||||||
*******************************************************/ |
|
||||||
void peripheral_power_enable (void) |
|
||||||
{ |
|
||||||
#define UART1_48MHZ_ENABLE ((unsigned short)0x0200) |
|
||||||
#define SW_CLOCK_REQUEST ((volatile unsigned short *)0xFFFE0834) |
|
||||||
|
|
||||||
*SW_CLOCK_REQUEST |= UART1_48MHZ_ENABLE; |
|
||||||
} |
|
||||||
|
|
||||||
#ifdef CONFIG_CMD_NET |
|
||||||
int board_eth_init(bd_t *bis) |
|
||||||
{ |
|
||||||
int rc = 0; |
|
||||||
#ifdef CONFIG_LAN91C96 |
|
||||||
rc = lan91c96_initialize(0, CONFIG_LAN91C96_BASE); |
|
||||||
#endif |
|
||||||
return rc; |
|
||||||
} |
|
||||||
#endif |
|
@ -1,197 +0,0 @@ |
|||||||
/*
|
|
||||||
* (C) Copyright 2004 |
|
||||||
* Texas Instruments. |
|
||||||
* Kshitij Gupta <kshitij@ti.com> |
|
||||||
* Configuration settings for the TI OMAP 1610 H2 board. |
|
||||||
* |
|
||||||
* See file CREDITS for list of people who contributed to this |
|
||||||
* project. |
|
||||||
* |
|
||||||
* This program is free software; you can redistribute it and/or |
|
||||||
* modify it under the terms of the GNU General Public License as |
|
||||||
* published by the Free Software Foundation; either version 2 of |
|
||||||
* the License, or (at your option) any later version. |
|
||||||
* |
|
||||||
* This program is distributed in the hope that it will be useful, |
|
||||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
||||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
||||||
* GNU General Public License for more details. |
|
||||||
* |
|
||||||
* You should have received a copy of the GNU General Public License |
|
||||||
* along with this program; if not, write to the Free Software |
|
||||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
|
||||||
* MA 02111-1307 USA |
|
||||||
*/ |
|
||||||
|
|
||||||
#ifndef __CONFIG_H |
|
||||||
#define __CONFIG_H |
|
||||||
|
|
||||||
/*
|
|
||||||
* High Level Configuration Options |
|
||||||
* (easy to change) |
|
||||||
*/ |
|
||||||
#define CONFIG_ARM926EJS 1 /* This is an arm926ejs CPU core */ |
|
||||||
#define CONFIG_OMAP 1 /* in a TI OMAP core */ |
|
||||||
#define CONFIG_OMAP1610 1 /* which is in a 1610 */ |
|
||||||
#define CONFIG_H2_OMAP1610 1 /* on an H2 Board */ |
|
||||||
|
|
||||||
#define CONFIG_MACH_TYPE MACH_TYPE_OMAP_H2 |
|
||||||
|
|
||||||
/* input clock of PLL */ |
|
||||||
/* the OMAP1610 H2 has 12MHz input clock */ |
|
||||||
#define CONFIG_SYS_CLK_FREQ 12000000 |
|
||||||
|
|
||||||
#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ |
|
||||||
|
|
||||||
#define CONFIG_MISC_INIT_R |
|
||||||
|
|
||||||
#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ |
|
||||||
#define CONFIG_SETUP_MEMORY_TAGS 1 |
|
||||||
#define CONFIG_INITRD_TAG 1 |
|
||||||
|
|
||||||
/*
|
|
||||||
* Size of malloc() pool |
|
||||||
*/ |
|
||||||
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) |
|
||||||
|
|
||||||
/*
|
|
||||||
* Hardware drivers |
|
||||||
*/ |
|
||||||
#define CONFIG_LAN91C96 |
|
||||||
#define CONFIG_LAN91C96_BASE 0x04000300 |
|
||||||
#define CONFIG_LAN91C96_EXT_PHY |
|
||||||
|
|
||||||
/*
|
|
||||||
* NS16550 Configuration |
|
||||||
*/ |
|
||||||
#define CONFIG_SYS_NS16550 |
|
||||||
#define CONFIG_SYS_NS16550_SERIAL |
|
||||||
#define CONFIG_SYS_NS16550_REG_SIZE (-4) |
|
||||||
#define CONFIG_SYS_NS16550_CLK (48000000) /* can be 12M/32Khz or 48Mhz */ |
|
||||||
#define CONFIG_SYS_NS16550_COM1 0xfffb0000 /* uart1, bluetooth uart */ |
|
||||||
|
|
||||||
/*
|
|
||||||
* select serial console configuration |
|
||||||
*/ |
|
||||||
#define CONFIG_SERIAL1 1 /* we use SERIAL 1 on OMAP1610 H2 */ |
|
||||||
|
|
||||||
/* allow to overwrite serial and ethaddr */ |
|
||||||
#define CONFIG_ENV_OVERWRITE |
|
||||||
#define CONFIG_CONS_INDEX 1 |
|
||||||
#define CONFIG_BAUDRATE 115200 |
|
||||||
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } |
|
||||||
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Command line configuration. |
|
||||||
*/ |
|
||||||
#include <config_cmd_default.h> |
|
||||||
|
|
||||||
#define CONFIG_CMD_DHCP |
|
||||||
|
|
||||||
|
|
||||||
/*
|
|
||||||
* BOOTP options |
|
||||||
*/ |
|
||||||
#define CONFIG_BOOTP_SUBNETMASK |
|
||||||
#define CONFIG_BOOTP_GATEWAY |
|
||||||
#define CONFIG_BOOTP_HOSTNAME |
|
||||||
#define CONFIG_BOOTP_BOOTPATH |
|
||||||
|
|
||||||
|
|
||||||
#include <configs/omap1510.h> |
|
||||||
|
|
||||||
#define CONFIG_BOOTDELAY 3 |
|
||||||
#define CONFIG_BOOTARGS "console=ttyS0,115200n8 noinitrd root=/dev/nfs ip=dhcp" |
|
||||||
#define CONFIG_BOOTCOMMAND "bootp;tftp;bootm" |
|
||||||
#define CONFIG_SYS_AUTOLOAD "n" /* No autoload */ |
|
||||||
|
|
||||||
#if defined(CONFIG_CMD_KGDB) |
|
||||||
#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ |
|
||||||
#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */ |
|
||||||
#endif |
|
||||||
|
|
||||||
/*
|
|
||||||
* Miscellaneous configurable options |
|
||||||
*/ |
|
||||||
#define CONFIG_SYS_LONGHELP /* undef to save memory */ |
|
||||||
#define CONFIG_SYS_PROMPT "OMAP1610 H2 # " /* Monitor Command Prompt */ |
|
||||||
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
|
||||||
/* Print Buffer Size */ |
|
||||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) |
|
||||||
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ |
|
||||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ |
|
||||||
|
|
||||||
#define CONFIG_SYS_MEMTEST_START 0x10000000 /* memtest works on */ |
|
||||||
#define CONFIG_SYS_MEMTEST_END 0x12000000 /* 32 MB in DRAM */ |
|
||||||
|
|
||||||
#define CONFIG_SYS_LOAD_ADDR 0x10000000 /* default load address */ |
|
||||||
|
|
||||||
/* The 1610 has 6 timers, they can be driven by the RefClk (12Mhz) or by
|
|
||||||
* DPLL1. This time is further subdivided by a local divisor. |
|
||||||
*/ |
|
||||||
#define CONFIG_SYS_TIMERBASE 0xFFFEC500 /* use timer 1 */ |
|
||||||
#define CONFIG_SYS_PTV 7 /* 2^(PTV+1), divide by 256 */ |
|
||||||
#define CONFIG_SYS_HZ ((CONFIG_SYS_CLK_FREQ)/(2 << CONFIG_SYS_PTV)) |
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
* Stack sizes |
|
||||||
* |
|
||||||
* The stack sizes are set up in start.S using the settings below |
|
||||||
*/ |
|
||||||
#define CONFIG_STACKSIZE (128*1024) /* regular stack */ |
|
||||||
#ifdef CONFIG_USE_IRQ |
|
||||||
#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ |
|
||||||
#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ |
|
||||||
#endif |
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
* Physical Memory Map |
|
||||||
*/ |
|
||||||
#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ |
|
||||||
#define PHYS_SDRAM_1 0x10000000 /* SDRAM Bank #1 */ |
|
||||||
#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */ |
|
||||||
|
|
||||||
#define PHYS_FLASH_1_BM1 0x00000000 /* Flash Bank #1 if booting from flash */ |
|
||||||
#define PHYS_FLASH_1_BM0 0x0C000000 /* Flash Bank #1 if booting from RAM */ |
|
||||||
|
|
||||||
#ifdef CONFIG_CS_AUTOBOOT /* Determine CS assignment in runtime */ |
|
||||||
|
|
||||||
#ifndef __ASSEMBLY__ |
|
||||||
extern unsigned long omap_flash_base; /* set in flash__init */ |
|
||||||
#endif |
|
||||||
#define CONFIG_SYS_FLASH_BASE omap_flash_base |
|
||||||
|
|
||||||
#elif defined(CONFIG_CS0_BOOT) |
|
||||||
|
|
||||||
#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1_BM0 |
|
||||||
|
|
||||||
#else |
|
||||||
|
|
||||||
#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1_BM1 |
|
||||||
|
|
||||||
#endif |
|
||||||
|
|
||||||
#define PHYS_SRAM 0x20000000 |
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
* FLASH and environment organization |
|
||||||
*/ |
|
||||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
|
||||||
#define PHYS_FLASH_SIZE 0x02000000 /* 32MB */ |
|
||||||
#define CONFIG_SYS_MAX_FLASH_SECT (259) /* max number of sectors on one chip */ |
|
||||||
/* addr of environment */ |
|
||||||
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x020000) |
|
||||||
|
|
||||||
/* timeout values are in ticks */ |
|
||||||
#define CONFIG_SYS_FLASH_ERASE_TOUT (20*CONFIG_SYS_HZ) /* Timeout for Flash Erase */ |
|
||||||
#define CONFIG_SYS_FLASH_WRITE_TOUT (20*CONFIG_SYS_HZ) /* Timeout for Flash Write */ |
|
||||||
|
|
||||||
#define CONFIG_ENV_IS_IN_FLASH 1 |
|
||||||
#define CONFIG_ENV_SIZE 0x20000 /* Total Size of Environment Sector */ |
|
||||||
#define CONFIG_ENV_OFFSET 0x20000 /* environment starts here */ |
|
||||||
|
|
||||||
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 |
|
||||||
#define CONFIG_SYS_INIT_SP_ADDR PHYS_SRAM |
|
||||||
|
|
||||||
#endif /* __CONFIG_H */ |
|
@ -1,202 +0,0 @@ |
|||||||
/*
|
|
||||||
* (C) Copyright 2003 |
|
||||||
* Texas Instruments. |
|
||||||
* Kshitij Gupta <kshitij@ti.com> |
|
||||||
* Configuation settings for the TI OMAP Innovator board. |
|
||||||
* |
|
||||||
* See file CREDITS for list of people who contributed to this |
|
||||||
* project. |
|
||||||
* |
|
||||||
* This program is free software; you can redistribute it and/or |
|
||||||
* modify it under the terms of the GNU General Public License as |
|
||||||
* published by the Free Software Foundation; either version 2 of |
|
||||||
* the License, or (at your option) any later version. |
|
||||||
* |
|
||||||
* This program is distributed in the hope that it will be useful, |
|
||||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
||||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
||||||
* GNU General Public License for more details. |
|
||||||
* |
|
||||||
* You should have received a copy of the GNU General Public License |
|
||||||
* along with this program; if not, write to the Free Software |
|
||||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
|
||||||
* MA 02111-1307 USA |
|
||||||
*/ |
|
||||||
|
|
||||||
#ifndef __CONFIG_H |
|
||||||
#define __CONFIG_H |
|
||||||
|
|
||||||
/*
|
|
||||||
* High Level Configuration Options |
|
||||||
* (easy to change) |
|
||||||
*/ |
|
||||||
#define CONFIG_ARM926EJS 1 /* This is an arm926ejs CPU core */ |
|
||||||
#define CONFIG_OMAP 1 /* in a TI OMAP core */ |
|
||||||
#define CONFIG_OMAP1610 1 /* which is in a 1610 */ |
|
||||||
#define CONFIG_INNOVATOROMAP1610 1 /* a Innovator Board */ |
|
||||||
|
|
||||||
#define CONFIG_MACH_TYPE MACH_TYPE_OMAP_INNOVATOR |
|
||||||
|
|
||||||
/* input clock of PLL */ |
|
||||||
/* the OMAP1610 Innovator has 12MHz input clock */ |
|
||||||
#define CONFIG_SYS_CLK_FREQ 12000000 |
|
||||||
|
|
||||||
#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ |
|
||||||
|
|
||||||
#define CONFIG_MISC_INIT_R |
|
||||||
|
|
||||||
#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ |
|
||||||
#define CONFIG_SETUP_MEMORY_TAGS 1 |
|
||||||
|
|
||||||
/*
|
|
||||||
* Size of malloc() pool |
|
||||||
*/ |
|
||||||
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) |
|
||||||
|
|
||||||
/*
|
|
||||||
* Hardware drivers |
|
||||||
*/ |
|
||||||
/*
|
|
||||||
*/ |
|
||||||
#define CONFIG_LAN91C96 |
|
||||||
#define CONFIG_LAN91C96_BASE 0x04000300 |
|
||||||
#define CONFIG_LAN91C96_EXT_PHY |
|
||||||
|
|
||||||
/*
|
|
||||||
* NS16550 Configuration |
|
||||||
*/ |
|
||||||
#define CONFIG_SYS_NS16550 |
|
||||||
#define CONFIG_SYS_NS16550_SERIAL |
|
||||||
#define CONFIG_SYS_NS16550_REG_SIZE (-4) |
|
||||||
#define CONFIG_SYS_NS16550_CLK (48000000) /* can be 12M/32Khz or 48Mhz */ |
|
||||||
#define CONFIG_SYS_NS16550_COM1 0xfffb0000 /* uart1, bluetooth uart on helen */ |
|
||||||
|
|
||||||
/*
|
|
||||||
* select serial console configuration |
|
||||||
*/ |
|
||||||
#define CONFIG_SERIAL1 1 /* we use SERIAL 1 on OMAP1610 Innovator */ |
|
||||||
|
|
||||||
/* allow to overwrite serial and ethaddr */ |
|
||||||
#define CONFIG_ENV_OVERWRITE |
|
||||||
#define CONFIG_CONS_INDEX 1 |
|
||||||
#define CONFIG_BAUDRATE 115200 |
|
||||||
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } |
|
||||||
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Command line configuration. |
|
||||||
*/ |
|
||||||
#include <config_cmd_default.h> |
|
||||||
|
|
||||||
#define CONFIG_CMD_DHCP |
|
||||||
|
|
||||||
|
|
||||||
/*
|
|
||||||
* BOOTP options |
|
||||||
*/ |
|
||||||
#define CONFIG_BOOTP_SUBNETMASK |
|
||||||
#define CONFIG_BOOTP_GATEWAY |
|
||||||
#define CONFIG_BOOTP_HOSTNAME |
|
||||||
#define CONFIG_BOOTP_BOOTPATH |
|
||||||
|
|
||||||
|
|
||||||
#include <configs/omap1510.h> |
|
||||||
|
|
||||||
#define CONFIG_BOOTDELAY 3 |
|
||||||
#define CONFIG_BOOTARGS "mem=32M console=ttyS0,115200n8 noinitrd \ |
|
||||||
root=/dev/nfs rw nfsroot=157.87.82.48:\
|
|
||||||
/home/a0875451/mwd/myfs/target ip=dhcp" |
|
||||||
#define CONFIG_NETMASK 255.255.254.0 /* talk on MY local net */ |
|
||||||
#define CONFIG_IPADDR 156.117.97.156 /* static IP I currently own */ |
|
||||||
#define CONFIG_SERVERIP 156.117.97.139 /* current IP of my dev pc */ |
|
||||||
#define CONFIG_BOOTFILE "uImage" /* file to load */ |
|
||||||
|
|
||||||
#if defined(CONFIG_CMD_KGDB) |
|
||||||
#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ |
|
||||||
#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */ |
|
||||||
#endif |
|
||||||
|
|
||||||
/*
|
|
||||||
* Miscellaneous configurable options |
|
||||||
*/ |
|
||||||
#define CONFIG_SYS_LONGHELP /* undef to save memory */ |
|
||||||
#define CONFIG_SYS_PROMPT "OMAP1610 Innovator # " /* Monitor Command Prompt */ |
|
||||||
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
|
||||||
/* Print Buffer Size */ |
|
||||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) |
|
||||||
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ |
|
||||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ |
|
||||||
|
|
||||||
#define CONFIG_SYS_MEMTEST_START 0x10000000 /* memtest works on */ |
|
||||||
#define CONFIG_SYS_MEMTEST_END 0x12000000 /* 32 MB in DRAM */ |
|
||||||
|
|
||||||
#define CONFIG_SYS_LOAD_ADDR 0x10000000 /* default load address */ |
|
||||||
|
|
||||||
/* The 1610 has 6 timers, they can be driven by the RefClk (12Mhz) or by
|
|
||||||
* DPLL1. This time is further subdivided by a local divisor. |
|
||||||
*/ |
|
||||||
#define CONFIG_SYS_TIMERBASE 0xFFFEC500 /* use timer 1 */ |
|
||||||
#define CONFIG_SYS_PTV 7 /* 2^(PTV+1), divide by 256 */ |
|
||||||
#define CONFIG_SYS_HZ ((CONFIG_SYS_CLK_FREQ)/(2 << CONFIG_SYS_PTV)) |
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
* Stack sizes |
|
||||||
* |
|
||||||
* The stack sizes are set up in start.S using the settings below |
|
||||||
*/ |
|
||||||
#define CONFIG_STACKSIZE (128*1024) /* regular stack */ |
|
||||||
#ifdef CONFIG_USE_IRQ |
|
||||||
#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ |
|
||||||
#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ |
|
||||||
#endif |
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
* Physical Memory Map |
|
||||||
*/ |
|
||||||
#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ |
|
||||||
#define PHYS_SDRAM_1 0x10000000 /* SDRAM Bank #1 */ |
|
||||||
#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */ |
|
||||||
|
|
||||||
#define PHYS_FLASH_1_BM1 0x00000000 /* Flash Bank #1 if booting from flash */ |
|
||||||
#define PHYS_FLASH_1_BM0 0x0C000000 /* Flash Bank #1 if booting from RAM */ |
|
||||||
|
|
||||||
#ifdef CONFIG_CS_AUTOBOOT /* Determine CS assignment in runtime */ |
|
||||||
|
|
||||||
#ifndef __ASSEMBLY__ |
|
||||||
extern unsigned long omap_flash_base; /* set in flash__init */ |
|
||||||
#endif |
|
||||||
#define CONFIG_SYS_FLASH_BASE omap_flash_base |
|
||||||
|
|
||||||
#elif defined(CONFIG_CS0_BOOT) |
|
||||||
|
|
||||||
#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1_BM0 |
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#else |
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#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1_BM1 |
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||||||
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#endif |
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#define PHYS_SRAM 0x20000000 |
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||||||
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||||||
/*-----------------------------------------------------------------------
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||||||
* FLASH and environment organization |
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||||||
*/ |
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||||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
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||||||
#define PHYS_FLASH_SIZE 0x02000000 /* 32MB */ |
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||||||
#define CONFIG_SYS_MAX_FLASH_SECT (259) /* max number of sectors on one chip */ |
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||||||
/* addr of environment */ |
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||||||
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x020000) |
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||||||
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||||||
/* timeout values are in ticks */ |
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||||||
#define CONFIG_SYS_FLASH_ERASE_TOUT (20*CONFIG_SYS_HZ) /* Timeout for Flash Erase */ |
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||||||
#define CONFIG_SYS_FLASH_WRITE_TOUT (20*CONFIG_SYS_HZ) /* Timeout for Flash Write */ |
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||||||
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||||||
#define CONFIG_ENV_IS_IN_FLASH 1 |
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||||||
#define CONFIG_ENV_SIZE 0x20000 /* Total Size of Environment Sector */ |
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||||||
#define CONFIG_ENV_OFFSET 0x20000 /* environment starts here */ |
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||||||
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||||||
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 |
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||||||
#define CONFIG_SYS_INIT_SP_ADDR PHYS_SRAM |
|
||||||
|
|
||||||
#endif /* __CONFIG_H */ |
|
Loading…
Reference in new issue