@ -50,15 +50,13 @@
# define CONFIG_SYS_MCKR1_VAL \
# define CONFIG_SYS_MCKR1_VAL \
( AT91_PMC_MCKR_CSS_SLOW | \
( AT91_PMC_MCKR_CSS_SLOW | \
AT91_PMC_MCKR_PRES_1 | \
AT91_PMC_MCKR_PRES_1 | \
AT91_PMC_MCKR_MDIV_2 | \
AT91_PMC_MCKR_MDIV_2 )
AT91_PMC_MCKR_PLLADIV_1 )
/* PCK/2 = MCK Master Clock from PLLA */
/* PCK/2 = MCK Master Clock from PLLA */
# define CONFIG_SYS_MCKR2_VAL \
# define CONFIG_SYS_MCKR2_VAL \
( AT91_PMC_MCKR_CSS_PLLA | \
( AT91_PMC_MCKR_CSS_PLLA | \
AT91_PMC_MCKR_PRES_1 | \
AT91_PMC_MCKR_PRES_1 | \
AT91_PMC_MCKR_MDIV_2 | \
AT91_PMC_MCKR_MDIV_2 )
AT91_PMC_MCKR_PLLADIV_1 )
/* define PDC[31:16] as DATA[31:16] */
/* define PDC[31:16] as DATA[31:16] */
# define CONFIG_SYS_PIOC_PDR_VAL1 0xFFFF0000
# define CONFIG_SYS_PIOC_PDR_VAL1 0xFFFF0000