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@ -10,9 +10,11 @@ |
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*/ |
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*/ |
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#include <asm/arch/clock.h> |
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#include <asm/arch/clock.h> |
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#include <asm/arch/crm_regs.h> |
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#include <asm/arch/iomux.h> |
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#include <asm/arch/iomux.h> |
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#include <asm/arch/imx-regs.h> |
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#include <asm/arch/imx-regs.h> |
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#include <asm/arch/mx6-pins.h> |
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#include <asm/arch/mx6-pins.h> |
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#include <asm/arch/mxc_hdmi.h> |
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#include <asm/arch/sys_proto.h> |
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#include <asm/arch/sys_proto.h> |
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#include <asm/gpio.h> |
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#include <asm/gpio.h> |
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#include <asm/imx-common/iomux-v3.h> |
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#include <asm/imx-common/iomux-v3.h> |
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@ -21,9 +23,11 @@ |
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#include <asm/sizes.h> |
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#include <asm/sizes.h> |
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#include <common.h> |
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#include <common.h> |
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#include <fsl_esdhc.h> |
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#include <fsl_esdhc.h> |
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#include <ipu_pixfmt.h> |
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#include <mmc.h> |
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#include <mmc.h> |
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#include <miiphy.h> |
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#include <miiphy.h> |
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#include <netdev.h> |
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#include <netdev.h> |
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#include <linux/fb.h> |
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DECLARE_GLOBAL_DATA_PTR; |
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DECLARE_GLOBAL_DATA_PTR; |
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@ -206,6 +210,88 @@ int board_phy_config(struct phy_device *phydev) |
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return 0; |
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return 0; |
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} |
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} |
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#if defined(CONFIG_VIDEO_IPUV3) |
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static void enable_hdmi(void) |
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{ |
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struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR; |
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u8 reg; |
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reg = readb(&hdmi->phy_conf0); |
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reg |= HDMI_PHY_CONF0_PDZ_MASK; |
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writeb(reg, &hdmi->phy_conf0); |
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udelay(3000); |
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reg |= HDMI_PHY_CONF0_ENTMDS_MASK; |
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writeb(reg, &hdmi->phy_conf0); |
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udelay(3000); |
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reg |= HDMI_PHY_CONF0_GEN2_TXPWRON_MASK; |
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writeb(reg, &hdmi->phy_conf0); |
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writeb(HDMI_MC_PHYRSTZ_ASSERT, &hdmi->mc_phyrstz); |
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} |
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static struct fb_videomode const hdmi = { |
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.name = "HDMI", |
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.refresh = 60, |
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.xres = 1024, |
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.yres = 768, |
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.pixclock = 15385, |
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.left_margin = 220, |
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.right_margin = 40, |
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.upper_margin = 21, |
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.lower_margin = 7, |
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.hsync_len = 60, |
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.vsync_len = 10, |
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.sync = FB_SYNC_EXT, |
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.vmode = FB_VMODE_NONINTERLACED |
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}; |
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int board_video_skip(void) |
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{ |
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int ret; |
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ret = ipuv3_fb_init(&hdmi, 0, IPU_PIX_FMT_RGB24); |
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if (ret) |
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printf("HDMI cannot be configured: %d\n", ret); |
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enable_hdmi(); |
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return ret; |
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} |
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static void setup_display(void) |
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{ |
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struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; |
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struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR; |
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int reg; |
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/* Turn on IPU clock */ |
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reg = readl(&mxc_ccm->CCGR3); |
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reg |= MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET; |
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writel(reg, &mxc_ccm->CCGR3); |
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/* Turn on HDMI PHY clock */ |
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reg = readl(&mxc_ccm->CCGR2); |
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reg |= MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK |
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| MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK; |
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writel(reg, &mxc_ccm->CCGR2); |
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/* clear HDMI PHY reset */ |
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writeb(HDMI_MC_PHYRSTZ_DEASSERT, &hdmi->mc_phyrstz); |
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reg = readl(&mxc_ccm->chsccdr); |
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reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK |
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| MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK |
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| MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK); |
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reg |= (CHSCCDR_CLK_SEL_LDB_DI0 |
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<< MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET) |
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| (CHSCCDR_PODF_DIVIDE_BY_3 |
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<< MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET) |
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| (CHSCCDR_IPU_PRE_CLK_540M_PFD |
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<< MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET); |
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writel(reg, &mxc_ccm->chsccdr); |
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} |
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#endif /* CONFIG_VIDEO_IPUV3 */ |
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int board_eth_init(bd_t *bis) |
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int board_eth_init(bd_t *bis) |
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{ |
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{ |
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int ret; |
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int ret; |
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@ -222,9 +308,21 @@ int board_eth_init(bd_t *bis) |
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int board_early_init_f(void) |
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int board_early_init_f(void) |
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{ |
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{ |
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setup_iomux_uart(); |
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setup_iomux_uart(); |
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#if defined(CONFIG_VIDEO_IPUV3) |
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setup_display(); |
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#endif |
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return 0; |
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return 0; |
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} |
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} |
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/*
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* Do not overwrite the console |
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* Use always serial for U-Boot console |
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*/ |
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int overwrite_console(void) |
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{ |
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return 1; |
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} |
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#ifdef CONFIG_CMD_BMODE |
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#ifdef CONFIG_CMD_BMODE |
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static const struct boot_mode board_boot_modes[] = { |
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static const struct boot_mode board_boot_modes[] = { |
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/* 4 bit bus width */ |
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/* 4 bit bus width */ |
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