@ -228,11 +228,13 @@ static ulong rockchip_mmc_get_clk(struct rk3036_cru *cru, uint clk_general_rate,
switch ( periph ) {
case HCLK_EMMC :
case SCLK_EMMC :
con = readl ( & cru - > cru_clksel_con [ 12 ] ) ;
mux = ( con > > EMMC_PLL_SHIFT ) & EMMC_PLL_MASK ;
div = ( con > > EMMC_DIV_SHIFT ) & EMMC_DIV_MASK ;
break ;
case HCLK_SDIO :
case SCLK_SDIO :
con = readl ( & cru - > cru_clksel_con [ 12 ] ) ;
mux = ( con > > MMC0_PLL_SHIFT ) & MMC0_PLL_MASK ;
div = ( con > > MMC0_DIV_SHIFT ) & MMC0_DIV_MASK ;
@ -265,6 +267,7 @@ static ulong rockchip_mmc_set_clk(struct rk3036_cru *cru, uint clk_general_rate,
switch ( periph ) {
case HCLK_EMMC :
case SCLK_EMMC :
rk_clrsetreg ( & cru - > cru_clksel_con [ 12 ] ,
EMMC_PLL_MASK < < EMMC_PLL_SHIFT |
EMMC_DIV_MASK < < EMMC_DIV_SHIFT ,
@ -272,6 +275,7 @@ static ulong rockchip_mmc_set_clk(struct rk3036_cru *cru, uint clk_general_rate,
( src_clk_div - 1 ) < < EMMC_DIV_SHIFT ) ;
break ;
case HCLK_SDIO :
case SCLK_SDIO :
rk_clrsetreg ( & cru - > cru_clksel_con [ 11 ] ,
MMC0_PLL_MASK < < MMC0_PLL_SHIFT |
MMC0_DIV_MASK < < MMC0_DIV_SHIFT ,
@ -307,6 +311,7 @@ static ulong rk3036_clk_set_rate(struct clk *clk, ulong rate)
case 0 . . . 63 :
return 0 ;
case HCLK_EMMC :
case SCLK_EMMC :
new_rate = rockchip_mmc_set_clk ( priv - > cru , gclk_rate ,
clk - > id , rate ) ;
break ;