sunxi: add UART0 setup for H6

The UART0 on H6 is available at PH bank (and PF bank, but the PF one is
muxed with SD card).

Add pinmux configuration.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
lime2-spi
Icenowy Zheng 6 years ago committed by Jagan Teki
parent 10196c9627
commit 7f51a4020e
  1. 1
      arch/arm/include/asm/arch-sunxi/gpio.h
  2. 4
      arch/arm/mach-sunxi/board.c

@ -198,6 +198,7 @@ enum sunxi_gpio_number {
#define SUN6I_GPH_TWI2 2 #define SUN6I_GPH_TWI2 2
#define SUN6I_GPH_UART0 2 #define SUN6I_GPH_UART0 2
#define SUN9I_GPH_UART0 2 #define SUN9I_GPH_UART0 2
#define SUN50I_H6_GPH_UART0 2
#define SUNXI_GPI_SDC3 2 #define SUNXI_GPI_SDC3 2
#define SUN7I_GPI_TWI3 3 #define SUN7I_GPI_TWI3 3

@ -107,6 +107,10 @@ static int gpio_init(void)
sunxi_gpio_set_cfgpin(SUNXI_GPB(8), SUN50I_GPB_UART0); sunxi_gpio_set_cfgpin(SUNXI_GPB(8), SUN50I_GPB_UART0);
sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN50I_GPB_UART0); sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN50I_GPB_UART0);
sunxi_gpio_set_pull(SUNXI_GPB(9), SUNXI_GPIO_PULL_UP); sunxi_gpio_set_pull(SUNXI_GPB(9), SUNXI_GPIO_PULL_UP);
#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN50I_H6)
sunxi_gpio_set_cfgpin(SUNXI_GPH(0), SUN50I_H6_GPH_UART0);
sunxi_gpio_set_cfgpin(SUNXI_GPH(1), SUN50I_H6_GPH_UART0);
sunxi_gpio_set_pull(SUNXI_GPH(1), SUNXI_GPIO_PULL_UP);
#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_A83T) #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_A83T)
sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN8I_A83T_GPB_UART0); sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN8I_A83T_GPB_UART0);
sunxi_gpio_set_cfgpin(SUNXI_GPB(10), SUN8I_A83T_GPB_UART0); sunxi_gpio_set_cfgpin(SUNXI_GPB(10), SUN8I_A83T_GPB_UART0);

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