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am33xx: convert defines from am33xx-specific to generic names

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Eliminate AM33xx specific names to prepare for TI814x support
within AM33xx-land.

Signed-off-by: Matt Porter <mporter@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
master
Matt Porter 12 years ago committed by Tom Rini
parent 98f92001b3
commit 81df2bab46
4 changed files with 13 additions and 13 deletions
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  1. 4
      arch/arm/cpu/armv7/am33xx/board.c
  2. 10
      arch/arm/include/asm/arch-am33xx/hardware.h
  3. 6
      board/phytec/pcm051/board.c
  4. 6
      board/ti/am335x/board.c

4
arch/arm/cpu/armv7/am33xx/board.c
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@ -141,11 +141,11 @@ int arch_misc_init(void)
{ {
#ifdef CONFIG_AM335X_USB0 #ifdef CONFIG_AM335X_USB0
musb_register(&otg0_plat, &otg0_board_data, musb_register(&otg0_plat, &otg0_board_data,
(void *)AM335X_USB0_OTG_BASE); (void *)USB0_OTG_BASE);
#endif #endif
#ifdef CONFIG_AM335X_USB1 #ifdef CONFIG_AM335X_USB1
musb_register(&otg1_plat, &otg1_board_data, musb_register(&otg1_plat, &otg1_board_data,
(void *)AM335X_USB1_OTG_BASE); (void *)USB1_OTG_BASE);
#endif #endif
return 0; return 0;
} }

10
arch/arm/include/asm/arch-am33xx/hardware.h
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@ -84,14 +84,14 @@
#define GPMC_BASE 0x50000000 #define GPMC_BASE 0x50000000
/* CPSW Config space */ /* CPSW Config space */
#define AM335X_CPSW_BASE 0x4A100000 #define CPSW_BASE 0x4A100000
#define AM335X_CPSW_MDIO_BASE 0x4A101000 #define CPSW_MDIO_BASE 0x4A101000
/* RTC base address */ /* RTC base address */
#define AM335X_RTC_BASE 0x44E3E000 #define RTC_BASE 0x44E3E000
/* OTG */ /* OTG */
#define AM335X_USB0_OTG_BASE 0x47401000 #define USB0_OTG_BASE 0x47401000
#define AM335X_USB1_OTG_BASE 0x47401800 #define USB1_OTG_BASE 0x47401800
#endif /* __AM33XX_HARDWARE_H */ #endif /* __AM33XX_HARDWARE_H */

6
board/phytec/pcm051/board.c
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@ -61,7 +61,7 @@ static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
static void rtc32k_enable(void) static void rtc32k_enable(void)
{ {
struct rtc_regs *rtc = (struct rtc_regs *)AM335X_RTC_BASE; struct rtc_regs *rtc = (struct rtc_regs *)RTC_BASE;
/* /*
* Unlock the RTC's registers. For more details please see the * Unlock the RTC's registers. For more details please see the
@ -199,8 +199,8 @@ static struct cpsw_slave_data cpsw_slaves[] = {
}; };
static struct cpsw_platform_data cpsw_data = { static struct cpsw_platform_data cpsw_data = {
.mdio_base = AM335X_CPSW_MDIO_BASE, .mdio_base = CPSW_MDIO_BASE,
.cpsw_base = AM335X_CPSW_BASE, .cpsw_base = CPSW_BASE,
.mdio_div = 0xff, .mdio_div = 0xff,
.channels = 8, .channels = 8,
.cpdma_reg_ofs = 0x800, .cpdma_reg_ofs = 0x800,

6
board/ti/am335x/board.c
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@ -134,7 +134,7 @@ static int read_eeprom(void)
static void rtc32k_enable(void) static void rtc32k_enable(void)
{ {
struct rtc_regs *rtc = (struct rtc_regs *)AM335X_RTC_BASE; struct rtc_regs *rtc = (struct rtc_regs *)RTC_BASE;
/* /*
* Unlock the RTC's registers. For more details please see the * Unlock the RTC's registers. For more details please see the
@ -414,8 +414,8 @@ static struct cpsw_slave_data cpsw_slaves[] = {
}; };
static struct cpsw_platform_data cpsw_data = { static struct cpsw_platform_data cpsw_data = {
.mdio_base = AM335X_CPSW_MDIO_BASE, .mdio_base = CPSW_MDIO_BASE,
.cpsw_base = AM335X_CPSW_BASE, .cpsw_base = CPSW_BASE,
.mdio_div = 0xff, .mdio_div = 0xff,
.channels = 8, .channels = 8,
.cpdma_reg_ofs = 0x800, .cpdma_reg_ofs = 0x800,

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