Some of the LPC code is common to several Intel LPC devices. Move it into a common location. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>master
Simon Glass
8 years ago
committed by
Bin Meng
parent
bb096b9fad
commit
8c30b57130
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/*
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* Copyright (c) 2016 Google, Inc |
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* |
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* SPDX-License-Identifier: GPL-2.0 |
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*/ |
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#include <common.h> |
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#include <dm.h> |
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#include <errno.h> |
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#include <fdtdec.h> |
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#include <pch.h> |
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#include <pci.h> |
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#include <asm/intel_regs.h> |
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#include <asm/io.h> |
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#include <asm/lpc_common.h> |
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DECLARE_GLOBAL_DATA_PTR; |
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/* Enable Prefetching and Caching */ |
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static void enable_spi_prefetch(struct udevice *pch) |
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{ |
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u8 reg8; |
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dm_pci_read_config8(pch, 0xdc, ®8); |
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reg8 &= ~(3 << 2); |
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reg8 |= (2 << 2); /* Prefetching and Caching Enabled */ |
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dm_pci_write_config8(pch, 0xdc, reg8); |
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} |
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static void enable_port80_on_lpc(struct udevice *pch) |
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{ |
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/* Enable port 80 POST on LPC */ |
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dm_pci_write_config32(pch, PCH_RCBA_BASE, RCB_BASE_ADDRESS | 1); |
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clrbits_le32(RCB_REG(GCS), 4); |
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} |
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/**
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* lpc_early_init() - set up LPC serial ports and other early things |
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* |
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* @dev: LPC device |
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* @return 0 if OK, -ve on error |
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*/ |
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int lpc_common_early_init(struct udevice *dev) |
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{ |
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struct udevice *pch = dev->parent; |
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struct reg_info { |
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u32 base; |
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u32 size; |
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} values[4], *ptr; |
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int count; |
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int i; |
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count = fdtdec_get_int_array_count(gd->fdt_blob, dev->of_offset, |
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"intel,gen-dec", (u32 *)values, |
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sizeof(values) / sizeof(u32)); |
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if (count < 0) |
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return -EINVAL; |
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/* Set COM1/COM2 decode range */ |
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dm_pci_write_config16(pch, LPC_IO_DEC, 0x0010); |
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/* Enable PS/2 Keyboard/Mouse, EC areas and COM1 */ |
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dm_pci_write_config16(pch, LPC_EN, KBC_LPC_EN | MC_LPC_EN | |
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GAMEL_LPC_EN | COMA_LPC_EN); |
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/* Write all registers but use 0 if we run out of data */ |
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count = count * sizeof(u32) / sizeof(values[0]); |
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for (i = 0, ptr = values; i < ARRAY_SIZE(values); i++, ptr++) { |
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u32 reg = 0; |
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if (i < count) |
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reg = ptr->base | PCI_COMMAND_IO | (ptr->size << 16); |
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dm_pci_write_config32(pch, LPC_GENX_DEC(i), reg); |
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} |
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enable_spi_prefetch(pch); |
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/* This is already done in start.S, but let's do it in C */ |
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enable_port80_on_lpc(pch); |
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return 0; |
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} |
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int lpc_set_spi_protect(struct udevice *dev, int bios_ctrl, bool protect) |
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{ |
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uint8_t bios_cntl; |
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/* Adjust the BIOS write protect and SMM BIOS Write Protect Disable */ |
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dm_pci_read_config8(dev, bios_ctrl, &bios_cntl); |
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if (protect) { |
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bios_cntl &= ~BIOS_CTRL_BIOSWE; |
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bios_cntl |= BIT(5); |
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} else { |
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bios_cntl |= BIOS_CTRL_BIOSWE; |
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bios_cntl &= ~BIT(5); |
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} |
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dm_pci_write_config8(dev, bios_ctrl, bios_cntl); |
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return 0; |
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} |
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@ -0,0 +1,59 @@ |
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/*
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* Copyright (c) 2016 Google, Inc |
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* |
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* SPDX-License-Identifier: GPL-2.0 |
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*/ |
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#ifndef __ASM_LPC_COMMON_H |
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#define __ASM_LPC_COMMON_H |
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#define PCH_RCBA_BASE 0xf0 |
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#define RC 0x3400 /* 32bit */ |
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#define GCS 0x3410 /* 32bit */ |
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#define PMBASE 0x40 |
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#define ACPI_CNTL 0x44 |
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#define LPC_IO_DEC 0x80 /* IO Decode Ranges Register */ |
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#define COMB_DEC_RANGE (1 << 4) /* 0x2f8-0x2ff (COM2) */ |
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#define COMA_DEC_RANGE (0 << 0) /* 0x3f8-0x3ff (COM1) */ |
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#define LPC_EN 0x82 /* LPC IF Enables Register */ |
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#define CNF2_LPC_EN (1 << 13) /* 0x4e/0x4f */ |
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#define CNF1_LPC_EN (1 << 12) /* 0x2e/0x2f */ |
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#define MC_LPC_EN (1 << 11) /* 0x62/0x66 */ |
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#define KBC_LPC_EN (1 << 10) /* 0x60/0x64 */ |
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#define GAMEH_LPC_EN (1 << 9) /* 0x208/0x20f */ |
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#define GAMEL_LPC_EN (1 << 8) /* 0x200/0x207 */ |
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#define FDD_LPC_EN (1 << 3) /* LPC_IO_DEC[12] */ |
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#define LPT_LPC_EN (1 << 2) /* LPC_IO_DEC[9:8] */ |
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#define COMB_LPC_EN (1 << 1) /* LPC_IO_DEC[6:4] */ |
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#define COMA_LPC_EN (1 << 0) /* LPC_IO_DEC[3:2] */ |
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#define LPC_GEN1_DEC 0x84 /* LPC IF Generic Decode Range 1 */ |
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#define LPC_GEN2_DEC 0x88 /* LPC IF Generic Decode Range 2 */ |
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#define LPC_GEN3_DEC 0x8c /* LPC IF Generic Decode Range 3 */ |
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#define LPC_GEN4_DEC 0x90 /* LPC IF Generic Decode Range 4 */ |
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#define LPC_GENX_DEC(x) (0x84 + 4 * (x)) |
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#define GEN_DEC_RANGE_256B 0xfc0000 /* 256 Bytes */ |
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#define GEN_DEC_RANGE_128B 0x7c0000 /* 128 Bytes */ |
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#define GEN_DEC_RANGE_64B 0x3c0000 /* 64 Bytes */ |
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#define GEN_DEC_RANGE_32B 0x1c0000 /* 32 Bytes */ |
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#define GEN_DEC_RANGE_16B 0x0c0000 /* 16 Bytes */ |
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#define GEN_DEC_RANGE_8B 0x040000 /* 8 Bytes */ |
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#define GEN_DEC_RANGE_4B 0x000000 /* 4 Bytes */ |
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#define GEN_DEC_RANGE_EN (1 << 0) /* Range Enable */ |
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/**
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* lpc_common_early_init() - Set up common LPC init |
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* |
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* This sets up the legacy decode areas, GEN_DEC, SPI prefetch and Port80. It |
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* also puts the RCB in the correct place so that RCB_REG() works. |
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* |
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* @dev: LPC device (a child of the PCH) |
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* @return 0 on success, -ve on error |
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*/ |
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int lpc_common_early_init(struct udevice *dev); |
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int lpc_set_spi_protect(struct udevice *dev, int bios_ctrl, bool protect); |
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#endif |
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