Wolfgang Denk
17 years ago
commit
912810eeca
@ -1,57 +0,0 @@ |
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/* |
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* (C) Copyright 2002 |
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* Gary Jennejohn, DENX Software Engineering, <gj@denx.de> |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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|
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OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") |
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/*OUTPUT_FORMAT("elf32-arm", "elf32-arm", "elf32-arm")*/ |
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OUTPUT_ARCH(arm) |
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ENTRY(_start) |
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SECTIONS |
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{ |
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. = 0x00000000; |
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|
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. = ALIGN(4); |
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.text : |
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{ |
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cpu/arm926ejs/start.o (.text) |
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*(.text) |
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} |
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|
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. = ALIGN(4); |
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.rodata : { *(.rodata) } |
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|
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. = ALIGN(4); |
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.data : { *(.data) } |
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|
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. = ALIGN(4); |
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.got : { *(.got) } |
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|
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. = .; |
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__u_boot_cmd_start = .; |
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.u_boot_cmd : { *(.u_boot_cmd) } |
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__u_boot_cmd_end = .; |
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|
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. = ALIGN(4); |
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__bss_start = .; |
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.bss : { *(.bss) } |
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_end = .; |
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} |
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@ -0,0 +1,57 @@ |
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#
|
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# (C) Copyright 2003-2008
|
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
|
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# (C) Copyright 2008
|
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# Stelian Pop <stelian.pop@leadtechdesign.com>
|
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# Lead Tech Design <www.leadtechdesign.com>
|
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#
|
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# See file CREDITS for list of people who contributed to this
|
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# project.
|
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#
|
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# This program is free software; you can redistribute it and/or
|
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# modify it under the terms of the GNU General Public License as
|
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# published by the Free Software Foundation; either version 2 of
|
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# the License, or (at your option) any later version.
|
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#
|
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# This program is distributed in the hope that it will be useful,
|
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
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# GNU General Public License for more details.
|
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#
|
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# You should have received a copy of the GNU General Public License
|
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# along with this program; if not, write to the Free Software
|
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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|
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include $(TOPDIR)/config.mk |
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LIB = $(obj)lib$(BOARD).a
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|
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COBJS-y += at91sam9261ek.o
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COBJS-y += led.o
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COBJS-y += partition.o
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COBJS-$(CONFIG_CMD_NAND) += nand.o
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|
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SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS-y))
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SOBJS := $(addprefix $(obj),$(SOBJS))
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|
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$(LIB): $(obj).depend $(OBJS) $(SOBJS) |
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$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
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|
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clean: |
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rm -f $(SOBJS) $(OBJS)
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|
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distclean: clean |
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rm -f $(LIB) core *.bak .depend
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|
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#########################################################################
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|
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk |
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|
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sinclude $(obj).depend |
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|
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#########################################################################
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@ -0,0 +1,258 @@ |
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/*
|
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* (C) Copyright 2007-2008 |
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* Stelian Pop <stelian.pop@leadtechdesign.com> |
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* Lead Tech Design <www.leadtechdesign.com> |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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|
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#include <common.h> |
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#include <asm/arch/at91sam9261.h> |
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#include <asm/arch/at91sam9261_matrix.h> |
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#include <asm/arch/at91sam9_smc.h> |
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#include <asm/arch/at91_pmc.h> |
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#include <asm/arch/at91_rstc.h> |
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#include <asm/arch/gpio.h> |
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#include <asm/arch/io.h> |
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#include <lcd.h> |
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#include <atmel_lcdc.h> |
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#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_DRIVER_DM9000) |
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#include <net.h> |
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#endif |
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|
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DECLARE_GLOBAL_DATA_PTR; |
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|
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/* ------------------------------------------------------------------------- */ |
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/*
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* Miscelaneous platform dependent initialisations |
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*/ |
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|
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static void at91sam9261ek_serial_hw_init(void) |
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{ |
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#ifdef CONFIG_USART0 |
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at91_set_A_periph(AT91_PIN_PC8, 1); /* TXD0 */ |
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at91_set_A_periph(AT91_PIN_PC9, 0); /* RXD0 */ |
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at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US0); |
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#endif |
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|
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#ifdef CONFIG_USART1 |
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at91_set_A_periph(AT91_PIN_PC12, 1); /* TXD1 */ |
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at91_set_A_periph(AT91_PIN_PC13, 0); /* RXD1 */ |
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at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US1); |
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#endif |
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|
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#ifdef CONFIG_USART2 |
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at91_set_A_periph(AT91_PIN_PC14, 1); /* TXD2 */ |
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at91_set_A_periph(AT91_PIN_PC15, 0); /* RXD2 */ |
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at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US2); |
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#endif |
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|
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#ifdef CONFIG_USART3 /* DBGU */ |
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at91_set_A_periph(AT91_PIN_PA9, 0); /* DRXD */ |
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at91_set_A_periph(AT91_PIN_PA10, 1); /* DTXD */ |
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at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_SYS); |
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#endif |
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} |
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|
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#ifdef CONFIG_CMD_NAND |
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static void at91sam9261ek_nand_hw_init(void) |
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{ |
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unsigned long csa; |
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|
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/* Enable CS3 */ |
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csa = at91_sys_read(AT91_MATRIX_EBICSA); |
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at91_sys_write(AT91_MATRIX_EBICSA, |
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csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA); |
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|
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/* Configure SMC CS3 for NAND/SmartMedia */ |
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at91_sys_write(AT91_SMC_SETUP(3), |
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AT91_SMC_NWESETUP_(0) | AT91_SMC_NCS_WRSETUP_(0) | |
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AT91_SMC_NRDSETUP_(0) | AT91_SMC_NCS_RDSETUP_(0)); |
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at91_sys_write(AT91_SMC_PULSE(3), |
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AT91_SMC_NWEPULSE_(2) | AT91_SMC_NCS_WRPULSE_(5) | |
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AT91_SMC_NRDPULSE_(2) | AT91_SMC_NCS_RDPULSE_(5)); |
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at91_sys_write(AT91_SMC_CYCLE(3), |
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AT91_SMC_NWECYCLE_(7) | AT91_SMC_NRDCYCLE_(7)); |
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at91_sys_write(AT91_SMC_MODE(3), |
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AT91_SMC_READMODE | AT91_SMC_WRITEMODE | |
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AT91_SMC_EXNWMODE_DISABLE | |
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#ifdef CFG_NAND_DBW_16 |
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AT91_SMC_DBW_16 | |
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#else /* CFG_NAND_DBW_8 */ |
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AT91_SMC_DBW_8 | |
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#endif |
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AT91_SMC_TDF_(1)); |
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|
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at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9261_ID_PIOC); |
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|
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/* Configure RDY/BSY */ |
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at91_set_gpio_input(AT91_PIN_PC15, 1); |
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|
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/* Enable NandFlash */ |
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at91_set_gpio_output(AT91_PIN_PC14, 1); |
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|
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at91_set_A_periph(AT91_PIN_PC0, 0); /* NANDOE */ |
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at91_set_A_periph(AT91_PIN_PC1, 0); /* NANDWE */ |
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} |
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#endif |
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|
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#ifdef CONFIG_HAS_DATAFLASH |
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static void at91sam9261ek_spi_hw_init(void) |
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{ |
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at91_set_A_periph(AT91_PIN_PA3, 0); /* SPI0_NPCS0 */ |
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|
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at91_set_A_periph(AT91_PIN_PA0, 0); /* SPI0_MISO */ |
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at91_set_A_periph(AT91_PIN_PA1, 0); /* SPI0_MOSI */ |
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at91_set_A_periph(AT91_PIN_PA2, 0); /* SPI0_SPCK */ |
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|
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/* Enable clock */ |
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at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9261_ID_SPI0); |
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} |
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#endif |
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|
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#ifdef CONFIG_DRIVER_DM9000 |
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static void at91sam9261ek_dm9000_hw_init(void) |
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{ |
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/* Configure SMC CS2 for DM9000 */ |
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at91_sys_write(AT91_SMC_SETUP(2), |
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AT91_SMC_NWESETUP_(2) | AT91_SMC_NCS_WRSETUP_(0) | |
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AT91_SMC_NRDSETUP_(2) | AT91_SMC_NCS_RDSETUP_(0)); |
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at91_sys_write(AT91_SMC_PULSE(2), |
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AT91_SMC_NWEPULSE_(4) | AT91_SMC_NCS_WRPULSE_(8) | |
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AT91_SMC_NRDPULSE_(4) | AT91_SMC_NCS_RDPULSE_(8)); |
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at91_sys_write(AT91_SMC_CYCLE(2), |
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AT91_SMC_NWECYCLE_(16) | AT91_SMC_NRDCYCLE_(16)); |
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at91_sys_write(AT91_SMC_MODE(2), |
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AT91_SMC_READMODE | AT91_SMC_WRITEMODE | |
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AT91_SMC_EXNWMODE_DISABLE | |
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AT91_SMC_BAT_WRITE | AT91_SMC_DBW_16 | |
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AT91_SMC_TDF_(1)); |
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|
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/* Configure Reset signal as output */ |
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at91_set_gpio_output(AT91_PIN_PC10, 0); |
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|
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/* Configure Interrupt pin as input, no pull-up */ |
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at91_set_gpio_input(AT91_PIN_PC11, 0); |
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} |
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#endif |
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|
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#ifdef CONFIG_LCD |
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vidinfo_t panel_info = { |
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vl_col: 240, |
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vl_row: 320, |
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vl_clk: 4965000, |
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vl_sync: ATMEL_LCDC_INVLINE_INVERTED | |
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ATMEL_LCDC_INVFRAME_INVERTED, |
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vl_bpix: 3, |
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vl_tft: 1, |
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vl_hsync_len: 5, |
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vl_left_margin: 1, |
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vl_right_margin:33, |
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vl_vsync_len: 1, |
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vl_upper_margin:1, |
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vl_lower_margin:0, |
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mmio: AT91SAM9261_LCDC_BASE, |
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}; |
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|
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void lcd_enable(void) |
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{ |
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at91_set_gpio_value(AT91_PIN_PA12, 0); /* power up */ |
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} |
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|
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void lcd_disable(void) |
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{ |
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at91_set_gpio_value(AT91_PIN_PA12, 1); /* power down */ |
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} |
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|
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static void at91sam9261ek_lcd_hw_init(void) |
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{ |
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at91_set_A_periph(AT91_PIN_PB1, 0); /* LCDHSYNC */ |
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at91_set_A_periph(AT91_PIN_PB2, 0); /* LCDDOTCK */ |
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at91_set_A_periph(AT91_PIN_PB3, 0); /* LCDDEN */ |
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at91_set_A_periph(AT91_PIN_PB4, 0); /* LCDCC */ |
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at91_set_A_periph(AT91_PIN_PB7, 0); /* LCDD2 */ |
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at91_set_A_periph(AT91_PIN_PB8, 0); /* LCDD3 */ |
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at91_set_A_periph(AT91_PIN_PB9, 0); /* LCDD4 */ |
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at91_set_A_periph(AT91_PIN_PB10, 0); /* LCDD5 */ |
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at91_set_A_periph(AT91_PIN_PB11, 0); /* LCDD6 */ |
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at91_set_A_periph(AT91_PIN_PB12, 0); /* LCDD7 */ |
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at91_set_A_periph(AT91_PIN_PB15, 0); /* LCDD10 */ |
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at91_set_A_periph(AT91_PIN_PB16, 0); /* LCDD11 */ |
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at91_set_A_periph(AT91_PIN_PB17, 0); /* LCDD12 */ |
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at91_set_A_periph(AT91_PIN_PB18, 0); /* LCDD13 */ |
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at91_set_A_periph(AT91_PIN_PB19, 0); /* LCDD14 */ |
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at91_set_A_periph(AT91_PIN_PB20, 0); /* LCDD15 */ |
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at91_set_B_periph(AT91_PIN_PB23, 0); /* LCDD18 */ |
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at91_set_B_periph(AT91_PIN_PB24, 0); /* LCDD19 */ |
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at91_set_B_periph(AT91_PIN_PB25, 0); /* LCDD20 */ |
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at91_set_B_periph(AT91_PIN_PB26, 0); /* LCDD21 */ |
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at91_set_B_periph(AT91_PIN_PB27, 0); /* LCDD22 */ |
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at91_set_B_periph(AT91_PIN_PB28, 0); /* LCDD23 */ |
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|
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at91_sys_write(AT91_PMC_SCER, AT91_PMC_HCK1); |
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|
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gd->fb_base = AT91SAM9261_SRAM_BASE; |
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} |
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#endif |
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|
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int board_init(void) |
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{ |
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/* Enable Ctrlc */ |
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console_init_f(); |
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|
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/* arch number of AT91SAM9261EK-Board */ |
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gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9261EK; |
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/* adress of boot parameters */ |
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gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; |
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|
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at91sam9261ek_serial_hw_init(); |
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#ifdef CONFIG_CMD_NAND |
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at91sam9261ek_nand_hw_init(); |
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#endif |
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#ifdef CONFIG_HAS_DATAFLASH |
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at91sam9261ek_spi_hw_init(); |
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#endif |
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#ifdef CONFIG_DRIVER_DM9000 |
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at91sam9261ek_dm9000_hw_init(); |
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#endif |
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#ifdef CONFIG_LCD |
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at91sam9261ek_lcd_hw_init(); |
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#endif |
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return 0; |
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} |
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|
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int dram_init(void) |
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{ |
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gd->bd->bi_dram[0].start = PHYS_SDRAM; |
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gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE; |
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return 0; |
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} |
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|
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#ifdef CONFIG_RESET_PHY_R |
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void reset_phy(void) |
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{ |
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#ifdef CONFIG_DRIVER_DM9000 |
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/*
|
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* Initialize ethernet HW addr prior to starting Linux, |
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* needed for nfsroot |
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*/ |
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eth_init(gd->bd); |
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#endif |
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} |
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#endif |
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@ -0,0 +1 @@ |
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TEXT_BASE = 0x23f00000
|
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@ -0,0 +1,78 @@ |
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/*
|
||||
* (C) Copyright 2007-2008 |
||||
* Stelian Pop <stelian.pop@leadtechdesign.com> |
||||
* Lead Tech Design <www.leadtechdesign.com> |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
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#include <common.h> |
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#include <asm/arch/at91sam9261.h> |
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#include <asm/arch/at91_pmc.h> |
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#include <asm/arch/gpio.h> |
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#include <asm/arch/io.h> |
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|
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#define RED_LED AT91_PIN_PA23 /* this is the power led */ |
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#define GREEN_LED AT91_PIN_PA13 /* this is the user1 led */ |
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#define YELLOW_LED AT91_PIN_PA14 /* this is the user2 led */ |
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|
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void red_LED_on(void) |
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{ |
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at91_set_gpio_value(RED_LED, 1); |
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} |
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|
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void red_LED_off(void) |
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{ |
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at91_set_gpio_value(RED_LED, 0); |
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} |
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|
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void green_LED_on(void) |
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{ |
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at91_set_gpio_value(GREEN_LED, 0); |
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} |
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|
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void green_LED_off(void) |
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{ |
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at91_set_gpio_value(GREEN_LED, 1); |
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} |
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|
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void yellow_LED_on(void) |
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{ |
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at91_set_gpio_value(YELLOW_LED, 0); |
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} |
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|
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void yellow_LED_off(void) |
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{ |
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at91_set_gpio_value(YELLOW_LED, 1); |
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} |
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|
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|
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void coloured_LED_init(void) |
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{ |
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/* Enable clock */ |
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at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9261_ID_PIOA); |
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|
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at91_set_gpio_output(RED_LED, 1); |
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at91_set_gpio_output(GREEN_LED, 1); |
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at91_set_gpio_output(YELLOW_LED, 1); |
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|
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at91_set_gpio_value(RED_LED, 0); |
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at91_set_gpio_value(GREEN_LED, 1); |
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at91_set_gpio_value(YELLOW_LED, 1); |
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} |
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@ -0,0 +1,79 @@ |
||||
/*
|
||||
* (C) Copyright 2007-2008 |
||||
* Stelian Pop <stelian.pop@leadtechdesign.com> |
||||
* Lead Tech Design <www.leadtechdesign.com> |
||||
* |
||||
* (C) Copyright 2006 ATMEL Rousset, Lacressonniere Nicolas |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <asm/arch/at91sam9261.h> |
||||
#include <asm/arch/gpio.h> |
||||
#include <asm/arch/at91_pio.h> |
||||
|
||||
#include <nand.h> |
||||
|
||||
/*
|
||||
* hardware specific access to control-lines |
||||
*/ |
||||
#define MASK_ALE (1 << 22) /* our ALE is AD22 */ |
||||
#define MASK_CLE (1 << 21) /* our CLE is AD21 */ |
||||
|
||||
static void at91sam9261ek_nand_hwcontrol(struct mtd_info *mtd, int cmd) |
||||
{ |
||||
struct nand_chip *this = mtd->priv; |
||||
ulong IO_ADDR_W = (ulong) this->IO_ADDR_W; |
||||
|
||||
IO_ADDR_W &= ~(MASK_ALE|MASK_CLE); |
||||
switch (cmd) { |
||||
case NAND_CTL_SETCLE: |
||||
IO_ADDR_W |= MASK_CLE; |
||||
break; |
||||
case NAND_CTL_SETALE: |
||||
IO_ADDR_W |= MASK_ALE; |
||||
break; |
||||
case NAND_CTL_CLRNCE: |
||||
at91_set_gpio_value(AT91_PIN_PC14, 1); |
||||
break; |
||||
case NAND_CTL_SETNCE: |
||||
at91_set_gpio_value(AT91_PIN_PC14, 0); |
||||
break; |
||||
} |
||||
this->IO_ADDR_W = (void *) IO_ADDR_W; |
||||
} |
||||
|
||||
static int at91sam9261ek_nand_ready(struct mtd_info *mtd) |
||||
{ |
||||
return at91_get_gpio_value(AT91_PIN_PC15); |
||||
} |
||||
|
||||
int board_nand_init(struct nand_chip *nand) |
||||
{ |
||||
nand->eccmode = NAND_ECC_SOFT; |
||||
#ifdef CFG_NAND_DBW_16 |
||||
nand->options = NAND_BUSWIDTH_16; |
||||
#endif |
||||
nand->hwcontrol = at91sam9261ek_nand_hwcontrol; |
||||
nand->dev_ready = at91sam9261ek_nand_ready; |
||||
nand->chip_delay = 20; |
||||
|
||||
return 0; |
||||
} |
||||
@ -0,0 +1,40 @@ |
||||
/*
|
||||
* (C) Copyright 2008 |
||||
* Ulf Samuelsson <ulf@atmel.com> |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
* |
||||
*/ |
||||
#include <common.h> |
||||
#include <config.h> |
||||
#include <asm/hardware.h> |
||||
#include <dataflash.h> |
||||
|
||||
AT91S_DATAFLASH_INFO dataflash_info[CFG_MAX_DATAFLASH_BANKS]; |
||||
|
||||
struct dataflash_addr cs[CFG_MAX_DATAFLASH_BANKS] = { |
||||
{CFG_DATAFLASH_LOGIC_ADDR_CS0, 0}, /* Logical adress, CS */ |
||||
{CFG_DATAFLASH_LOGIC_ADDR_CS3, 3} |
||||
}; |
||||
|
||||
/*define the area offsets*/ |
||||
dataflash_protect_t area_list[NB_DATAFLASH_AREA] = { |
||||
{0x00000000, 0x000041FF, FLAG_PROTECT_SET, 0, "Bootstrap"}, |
||||
{0x00004200, 0x000083FF, FLAG_PROTECT_CLEAR, 0, "Environment"}, |
||||
{0x00008400, 0x00041FFF, FLAG_PROTECT_SET, 0, "U-Boot"}, |
||||
{0x00042000, 0x00251FFF, FLAG_PROTECT_CLEAR, 0, "Kernel"}, |
||||
{0x00252000, 0xFFFFFFFF, FLAG_PROTECT_CLEAR, 0, "FS"}, |
||||
}; |
||||
@ -0,0 +1,57 @@ |
||||
#
|
||||
# (C) Copyright 2003-2008
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# (C) Copyright 2008
|
||||
# Stelian Pop <stelian.pop@leadtechdesign.com>
|
||||
# Lead Tech Design <www.leadtechdesign.com>
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
include $(TOPDIR)/config.mk |
||||
|
||||
LIB = $(obj)lib$(BOARD).a
|
||||
|
||||
COBJS-y += at91sam9263ek.o
|
||||
COBJS-y += led.o
|
||||
COBJS-y += partition.o
|
||||
COBJS-$(CONFIG_CMD_NAND) += nand.o
|
||||
|
||||
SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS-y))
|
||||
SOBJS := $(addprefix $(obj),$(SOBJS))
|
||||
|
||||
$(LIB): $(obj).depend $(OBJS) $(SOBJS) |
||||
$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
|
||||
|
||||
clean: |
||||
rm -f $(SOBJS) $(OBJS)
|
||||
|
||||
distclean: clean |
||||
rm -f $(LIB) core *.bak .depend
|
||||
|
||||
#########################################################################
|
||||
|
||||
# defines $(obj).depend target
|
||||
include $(SRCTREE)/rules.mk |
||||
|
||||
sinclude $(obj).depend |
||||
|
||||
#########################################################################
|
||||
@ -0,0 +1,305 @@ |
||||
/*
|
||||
* (C) Copyright 2007-2008 |
||||
* Stelian Pop <stelian.pop@leadtechdesign.com> |
||||
* Lead Tech Design <www.leadtechdesign.com> |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <asm/sizes.h> |
||||
#include <asm/arch/at91sam9263.h> |
||||
#include <asm/arch/at91sam9263_matrix.h> |
||||
#include <asm/arch/at91sam9_smc.h> |
||||
#include <asm/arch/at91_pmc.h> |
||||
#include <asm/arch/at91_rstc.h> |
||||
#include <asm/arch/gpio.h> |
||||
#include <asm/arch/io.h> |
||||
#include <lcd.h> |
||||
#include <atmel_lcdc.h> |
||||
#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB) |
||||
#include <net.h> |
||||
#endif |
||||
|
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
/* ------------------------------------------------------------------------- */ |
||||
/*
|
||||
* Miscelaneous platform dependent initialisations |
||||
*/ |
||||
|
||||
static void at91sam9263ek_serial_hw_init(void) |
||||
{ |
||||
#ifdef CONFIG_USART0 |
||||
at91_set_A_periph(AT91_PIN_PA26, 1); /* TXD0 */ |
||||
at91_set_A_periph(AT91_PIN_PA27, 0); /* RXD0 */ |
||||
at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US0); |
||||
#endif |
||||
|
||||
#ifdef CONFIG_USART1 |
||||
at91_set_A_periph(AT91_PIN_PD0, 1); /* TXD1 */ |
||||
at91_set_A_periph(AT91_PIN_PD1, 0); /* RXD1 */ |
||||
at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US1); |
||||
#endif |
||||
|
||||
#ifdef CONFIG_USART2 |
||||
at91_set_A_periph(AT91_PIN_PD2, 1); /* TXD2 */ |
||||
at91_set_A_periph(AT91_PIN_PD3, 0); /* RXD2 */ |
||||
at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US2); |
||||
#endif |
||||
|
||||
#ifdef CONFIG_USART3 /* DBGU */ |
||||
at91_set_A_periph(AT91_PIN_PC30, 0); /* DRXD */ |
||||
at91_set_A_periph(AT91_PIN_PC31, 1); /* DTXD */ |
||||
at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_SYS); |
||||
#endif |
||||
} |
||||
|
||||
#ifdef CONFIG_CMD_NAND |
||||
static void at91sam9263ek_nand_hw_init(void) |
||||
{ |
||||
unsigned long csa; |
||||
|
||||
/* Enable CS3 */ |
||||
csa = at91_sys_read(AT91_MATRIX_EBI0CSA); |
||||
at91_sys_write(AT91_MATRIX_EBI0CSA, |
||||
csa | AT91_MATRIX_EBI0_CS3A_SMC_SMARTMEDIA); |
||||
|
||||
/* Configure SMC CS3 for NAND/SmartMedia */ |
||||
at91_sys_write(AT91_SMC_SETUP(3), |
||||
AT91_SMC_NWESETUP_(0) | AT91_SMC_NCS_WRSETUP_(0) | |
||||
AT91_SMC_NRDSETUP_(0) | AT91_SMC_NCS_RDSETUP_(0)); |
||||
at91_sys_write(AT91_SMC_PULSE(3), |
||||
AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) | |
||||
AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3)); |
||||
at91_sys_write(AT91_SMC_CYCLE(3), |
||||
AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5)); |
||||
at91_sys_write(AT91_SMC_MODE(3), |
||||
AT91_SMC_READMODE | AT91_SMC_WRITEMODE | |
||||
AT91_SMC_EXNWMODE_DISABLE | |
||||
#ifdef CFG_NAND_DBW_16 |
||||
AT91_SMC_DBW_16 | |
||||
#else /* CFG_NAND_DBW_8 */ |
||||
AT91_SMC_DBW_8 | |
||||
#endif |
||||
AT91_SMC_TDF_(2)); |
||||
|
||||
at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_PIOA | |
||||
1 << AT91SAM9263_ID_PIOCDE); |
||||
|
||||
/* Configure RDY/BSY */ |
||||
at91_set_gpio_input(AT91_PIN_PA22, 1); |
||||
|
||||
/* Enable NandFlash */ |
||||
at91_set_gpio_output(AT91_PIN_PD15, 1); |
||||
} |
||||
#endif |
||||
|
||||
#ifdef CONFIG_HAS_DATAFLASH |
||||
static void at91sam9263ek_spi_hw_init(void) |
||||
{ |
||||
at91_set_B_periph(AT91_PIN_PA5, 0); /* SPI0_NPCS0 */ |
||||
|
||||
at91_set_B_periph(AT91_PIN_PA0, 0); /* SPI0_MISO */ |
||||
at91_set_B_periph(AT91_PIN_PA1, 0); /* SPI0_MOSI */ |
||||
at91_set_B_periph(AT91_PIN_PA2, 0); /* SPI0_SPCK */ |
||||
|
||||
/* Enable clock */ |
||||
at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_SPI0); |
||||
} |
||||
#endif |
||||
|
||||
#ifdef CONFIG_MACB |
||||
static void at91sam9263ek_macb_hw_init(void) |
||||
{ |
||||
/* Enable clock */ |
||||
at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_EMAC); |
||||
|
||||
/*
|
||||
* Disable pull-up on: |
||||
* RXDV (PC25) => PHY normal mode (not Test mode) |
||||
* ERX0 (PE25) => PHY ADDR0 |
||||
* ERX1 (PE26) => PHY ADDR1 => PHYADDR = 0x0 |
||||
* |
||||
* PHY has internal pull-down |
||||
*/ |
||||
writel(pin_to_mask(AT91_PIN_PC25), |
||||
pin_to_controller(AT91_PIN_PC0) + PIO_PUDR); |
||||
writel(pin_to_mask(AT91_PIN_PE25) | |
||||
pin_to_mask(AT91_PIN_PE26), |
||||
pin_to_controller(AT91_PIN_PE0) + PIO_PUDR); |
||||
|
||||
/* Need to reset PHY -> 500ms reset */ |
||||
at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY | |
||||
AT91_RSTC_ERSTL | (0x0D << 8) | |
||||
AT91_RSTC_URSTEN); |
||||
|
||||
at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_EXTRST); |
||||
|
||||
/* Wait for end hardware reset */ |
||||
while (!(at91_sys_read(AT91_RSTC_SR) & AT91_RSTC_NRSTL)); |
||||
|
||||
/* Re-enable pull-up */ |
||||
writel(pin_to_mask(AT91_PIN_PC25), |
||||
pin_to_controller(AT91_PIN_PC0) + PIO_PUER); |
||||
writel(pin_to_mask(AT91_PIN_PE25) | |
||||
pin_to_mask(AT91_PIN_PE26), |
||||
pin_to_controller(AT91_PIN_PE0) + PIO_PUER); |
||||
|
||||
at91_set_A_periph(AT91_PIN_PE21, 0); /* ETXCK_EREFCK */ |
||||
at91_set_B_periph(AT91_PIN_PC25, 0); /* ERXDV */ |
||||
at91_set_A_periph(AT91_PIN_PE25, 0); /* ERX0 */ |
||||
at91_set_A_periph(AT91_PIN_PE26, 0); /* ERX1 */ |
||||
at91_set_A_periph(AT91_PIN_PE27, 0); /* ERXER */ |
||||
at91_set_A_periph(AT91_PIN_PE28, 0); /* ETXEN */ |
||||
at91_set_A_periph(AT91_PIN_PE23, 0); /* ETX0 */ |
||||
at91_set_A_periph(AT91_PIN_PE24, 0); /* ETX1 */ |
||||
at91_set_A_periph(AT91_PIN_PE30, 0); /* EMDIO */ |
||||
at91_set_A_periph(AT91_PIN_PE29, 0); /* EMDC */ |
||||
|
||||
#ifndef CONFIG_RMII |
||||
at91_set_A_periph(AT91_PIN_PE22, 0); /* ECRS */ |
||||
at91_set_B_periph(AT91_PIN_PC26, 0); /* ECOL */ |
||||
at91_set_B_periph(AT91_PIN_PC22, 0); /* ERX2 */ |
||||
at91_set_B_periph(AT91_PIN_PC23, 0); /* ERX3 */ |
||||
at91_set_B_periph(AT91_PIN_PC27, 0); /* ERXCK */ |
||||
at91_set_B_periph(AT91_PIN_PC20, 0); /* ETX2 */ |
||||
at91_set_B_periph(AT91_PIN_PC21, 0); /* ETX3 */ |
||||
at91_set_B_periph(AT91_PIN_PC24, 0); /* ETXER */ |
||||
#endif |
||||
|
||||
} |
||||
#endif |
||||
|
||||
#ifdef CONFIG_USB_OHCI_NEW |
||||
static void at91sam9263ek_uhp_hw_init(void) |
||||
{ |
||||
/* Enable VBus on UHP ports */ |
||||
at91_set_gpio_output(AT91_PIN_PA21, 0); |
||||
at91_set_gpio_output(AT91_PIN_PA24, 0); |
||||
} |
||||
#endif |
||||
|
||||
#ifdef CONFIG_LCD |
||||
vidinfo_t panel_info = { |
||||
vl_col: 240, |
||||
vl_row: 320, |
||||
vl_clk: 4965000, |
||||
vl_sync: ATMEL_LCDC_INVLINE_INVERTED | |
||||
ATMEL_LCDC_INVFRAME_INVERTED, |
||||
vl_bpix: 3, |
||||
vl_tft: 1, |
||||
vl_hsync_len: 5, |
||||
vl_left_margin: 1, |
||||
vl_right_margin:33, |
||||
vl_vsync_len: 1, |
||||
vl_upper_margin:1, |
||||
vl_lower_margin:0, |
||||
mmio: AT91SAM9263_LCDC_BASE, |
||||
}; |
||||
|
||||
void lcd_enable(void) |
||||
{ |
||||
at91_set_gpio_value(AT91_PIN_PA30, 1); /* power up */ |
||||
} |
||||
|
||||
void lcd_disable(void) |
||||
{ |
||||
at91_set_gpio_value(AT91_PIN_PA30, 0); /* power down */ |
||||
} |
||||
|
||||
static void at91sam9263ek_lcd_hw_init(void) |
||||
{ |
||||
at91_set_A_periph(AT91_PIN_PC1, 0); /* LCDHSYNC */ |
||||
at91_set_A_periph(AT91_PIN_PC2, 0); /* LCDDOTCK */ |
||||
at91_set_A_periph(AT91_PIN_PC3, 0); /* LCDDEN */ |
||||
at91_set_B_periph(AT91_PIN_PB9, 0); /* LCDCC */ |
||||
at91_set_A_periph(AT91_PIN_PC6, 0); /* LCDD2 */ |
||||
at91_set_A_periph(AT91_PIN_PC7, 0); /* LCDD3 */ |
||||
at91_set_A_periph(AT91_PIN_PC8, 0); /* LCDD4 */ |
||||
at91_set_A_periph(AT91_PIN_PC9, 0); /* LCDD5 */ |
||||
at91_set_A_periph(AT91_PIN_PC10, 0); /* LCDD6 */ |
||||
at91_set_A_periph(AT91_PIN_PC11, 0); /* LCDD7 */ |
||||
at91_set_A_periph(AT91_PIN_PC14, 0); /* LCDD10 */ |
||||
at91_set_A_periph(AT91_PIN_PC15, 0); /* LCDD11 */ |
||||
at91_set_A_periph(AT91_PIN_PC16, 0); /* LCDD12 */ |
||||
at91_set_B_periph(AT91_PIN_PC12, 0); /* LCDD13 */ |
||||
at91_set_A_periph(AT91_PIN_PC18, 0); /* LCDD14 */ |
||||
at91_set_A_periph(AT91_PIN_PC19, 0); /* LCDD15 */ |
||||
at91_set_A_periph(AT91_PIN_PC22, 0); /* LCDD18 */ |
||||
at91_set_A_periph(AT91_PIN_PC23, 0); /* LCDD19 */ |
||||
at91_set_A_periph(AT91_PIN_PC24, 0); /* LCDD20 */ |
||||
at91_set_B_periph(AT91_PIN_PC17, 0); /* LCDD21 */ |
||||
at91_set_A_periph(AT91_PIN_PC26, 0); /* LCDD22 */ |
||||
at91_set_A_periph(AT91_PIN_PC27, 0); /* LCDD23 */ |
||||
|
||||
at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_LCDC); |
||||
|
||||
gd->fb_base = AT91SAM9263_SRAM0_BASE; |
||||
} |
||||
#endif |
||||
|
||||
int board_init(void) |
||||
{ |
||||
/* Enable Ctrlc */ |
||||
console_init_f(); |
||||
|
||||
/* arch number of AT91SAM9263EK-Board */ |
||||
gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9263EK; |
||||
/* adress of boot parameters */ |
||||
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; |
||||
|
||||
at91sam9263ek_serial_hw_init(); |
||||
#ifdef CONFIG_CMD_NAND |
||||
at91sam9263ek_nand_hw_init(); |
||||
#endif |
||||
#ifdef CONFIG_HAS_DATAFLASH |
||||
at91sam9263ek_spi_hw_init(); |
||||
#endif |
||||
#ifdef CONFIG_MACB |
||||
at91sam9263ek_macb_hw_init(); |
||||
#endif |
||||
#ifdef CONFIG_USB_OHCI_NEW |
||||
at91sam9263ek_uhp_hw_init(); |
||||
#endif |
||||
#ifdef CONFIG_LCD |
||||
at91sam9263ek_lcd_hw_init(); |
||||
#endif |
||||
return 0; |
||||
} |
||||
|
||||
int dram_init(void) |
||||
{ |
||||
gd->bd->bi_dram[0].start = PHYS_SDRAM; |
||||
gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE; |
||||
return 0; |
||||
} |
||||
|
||||
#ifdef CONFIG_RESET_PHY_R |
||||
void reset_phy(void) |
||||
{ |
||||
#ifdef CONFIG_MACB |
||||
/*
|
||||
* Initialize ethernet HW addr prior to starting Linux, |
||||
* needed for nfsroot |
||||
*/ |
||||
eth_init(gd->bd); |
||||
#endif |
||||
} |
||||
#endif |
||||
@ -0,0 +1 @@ |
||||
TEXT_BASE = 0x23f00000
|
||||
@ -0,0 +1,78 @@ |
||||
/*
|
||||
* (C) Copyright 2007-2008 |
||||
* Stelian Pop <stelian.pop@leadtechdesign.com> |
||||
* Lead Tech Design <www.leadtechdesign.com> |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <asm/arch/at91sam9263.h> |
||||
#include <asm/arch/at91_pmc.h> |
||||
#include <asm/arch/gpio.h> |
||||
#include <asm/arch/io.h> |
||||
|
||||
#define RED_LED AT91_PIN_PB7 /* this is the power led */ |
||||
#define GREEN_LED AT91_PIN_PB8 /* this is the user1 led */ |
||||
#define YELLOW_LED AT91_PIN_PC29 /* this is the user2 led */ |
||||
|
||||
void red_LED_on(void) |
||||
{ |
||||
at91_set_gpio_value(RED_LED, 1); |
||||
} |
||||
|
||||
void red_LED_off(void) |
||||
{ |
||||
at91_set_gpio_value(RED_LED, 0); |
||||
} |
||||
|
||||
void green_LED_on(void) |
||||
{ |
||||
at91_set_gpio_value(GREEN_LED, 0); |
||||
} |
||||
|
||||
void green_LED_off(void) |
||||
{ |
||||
at91_set_gpio_value(GREEN_LED, 1); |
||||
} |
||||
|
||||
void yellow_LED_on(void) |
||||
{ |
||||
at91_set_gpio_value(YELLOW_LED, 0); |
||||
} |
||||
|
||||
void yellow_LED_off(void) |
||||
{ |
||||
at91_set_gpio_value(YELLOW_LED, 1); |
||||
} |
||||
|
||||
void coloured_LED_init(void) |
||||
{ |
||||
/* Enable clock */ |
||||
at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_PIOB | |
||||
1 << AT91SAM9263_ID_PIOCDE); |
||||
|
||||
at91_set_gpio_output(RED_LED, 1); |
||||
at91_set_gpio_output(GREEN_LED, 1); |
||||
at91_set_gpio_output(YELLOW_LED, 1); |
||||
|
||||
at91_set_gpio_value(RED_LED, 0); |
||||
at91_set_gpio_value(GREEN_LED, 1); |
||||
at91_set_gpio_value(YELLOW_LED, 1); |
||||
} |
||||
@ -0,0 +1,79 @@ |
||||
/*
|
||||
* (C) Copyright 2007-2008 |
||||
* Stelian Pop <stelian.pop@leadtechdesign.com> |
||||
* Lead Tech Design <www.leadtechdesign.com> |
||||
* |
||||
* (C) Copyright 2006 ATMEL Rousset, Lacressonniere Nicolas |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <asm/arch/at91sam9263.h> |
||||
#include <asm/arch/gpio.h> |
||||
#include <asm/arch/at91_pio.h> |
||||
|
||||
#include <nand.h> |
||||
|
||||
/*
|
||||
* hardware specific access to control-lines |
||||
*/ |
||||
#define MASK_ALE (1 << 21) /* our ALE is AD21 */ |
||||
#define MASK_CLE (1 << 22) /* our CLE is AD22 */ |
||||
|
||||
static void at91sam9263ek_nand_hwcontrol(struct mtd_info *mtd, int cmd) |
||||
{ |
||||
struct nand_chip *this = mtd->priv; |
||||
ulong IO_ADDR_W = (ulong) this->IO_ADDR_W; |
||||
|
||||
IO_ADDR_W &= ~(MASK_ALE|MASK_CLE); |
||||
switch (cmd) { |
||||
case NAND_CTL_SETCLE: |
||||
IO_ADDR_W |= MASK_CLE; |
||||
break; |
||||
case NAND_CTL_SETALE: |
||||
IO_ADDR_W |= MASK_ALE; |
||||
break; |
||||
case NAND_CTL_CLRNCE: |
||||
at91_set_gpio_value(AT91_PIN_PD15, 1); |
||||
break; |
||||
case NAND_CTL_SETNCE: |
||||
at91_set_gpio_value(AT91_PIN_PD15, 0); |
||||
break; |
||||
} |
||||
this->IO_ADDR_W = (void *) IO_ADDR_W; |
||||
} |
||||
|
||||
static int at91sam9263ek_nand_ready(struct mtd_info *mtd) |
||||
{ |
||||
return at91_get_gpio_value(AT91_PIN_PA22); |
||||
} |
||||
|
||||
int board_nand_init(struct nand_chip *nand) |
||||
{ |
||||
nand->eccmode = NAND_ECC_SOFT; |
||||
#ifdef CFG_NAND_DBW_16 |
||||
nand->options = NAND_BUSWIDTH_16; |
||||
#endif |
||||
nand->hwcontrol = at91sam9263ek_nand_hwcontrol; |
||||
nand->dev_ready = at91sam9263ek_nand_ready; |
||||
nand->chip_delay = 20; |
||||
|
||||
return 0; |
||||
} |
||||
@ -0,0 +1,39 @@ |
||||
/*
|
||||
* (C) Copyright 2008 |
||||
* Ulf Samuelsson <ulf@atmel.com> |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
* |
||||
*/ |
||||
#include <common.h> |
||||
#include <config.h> |
||||
#include <asm/hardware.h> |
||||
#include <dataflash.h> |
||||
|
||||
AT91S_DATAFLASH_INFO dataflash_info[CFG_MAX_DATAFLASH_BANKS]; |
||||
|
||||
struct dataflash_addr cs[CFG_MAX_DATAFLASH_BANKS] = { |
||||
{CFG_DATAFLASH_LOGIC_ADDR_CS0, 0}, /* Logical adress, CS */ |
||||
}; |
||||
|
||||
/*define the area offsets*/ |
||||
dataflash_protect_t area_list[NB_DATAFLASH_AREA] = { |
||||
{0x00000000, 0x000041FF, FLAG_PROTECT_SET, 0, "Bootstrap"}, |
||||
{0x00004200, 0x000083FF, FLAG_PROTECT_CLEAR, 0, "Environment"}, |
||||
{0x00008400, 0x00041FFF, FLAG_PROTECT_SET, 0, "U-Boot"}, |
||||
{0x00042000, 0x00251FFF, FLAG_PROTECT_CLEAR, 0, "Kernel"}, |
||||
{0x00252000, 0xFFFFFFFF, FLAG_PROTECT_CLEAR, 0, "FS"}, |
||||
}; |
||||
@ -0,0 +1,57 @@ |
||||
#
|
||||
# (C) Copyright 2003-2008
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# (C) Copyright 2008
|
||||
# Stelian Pop <stelian.pop@leadtechdesign.com>
|
||||
# Lead Tech Design <www.leadtechdesign.com>
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
include $(TOPDIR)/config.mk |
||||
|
||||
LIB = $(obj)lib$(BOARD).a
|
||||
|
||||
COBJS-y += at91sam9rlek.o
|
||||
COBJS-y += led.o
|
||||
COBJS-y += partition.o
|
||||
COBJS-$(CONFIG_CMD_NAND) += nand.o
|
||||
|
||||
SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS-y))
|
||||
SOBJS := $(addprefix $(obj),$(SOBJS))
|
||||
|
||||
$(LIB): $(obj).depend $(OBJS) $(SOBJS) |
||||
$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
|
||||
|
||||
clean: |
||||
rm -f $(SOBJS) $(OBJS)
|
||||
|
||||
distclean: clean |
||||
rm -f $(LIB) core *.bak .depend
|
||||
|
||||
#########################################################################
|
||||
|
||||
# defines $(obj).depend target
|
||||
include $(SRCTREE)/rules.mk |
||||
|
||||
sinclude $(obj).depend |
||||
|
||||
#########################################################################
|
||||
@ -0,0 +1,215 @@ |
||||
/*
|
||||
* (C) Copyright 2007-2008 |
||||
* Stelian Pop <stelian.pop@leadtechdesign.com> |
||||
* Lead Tech Design <www.leadtechdesign.com> |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <asm/arch/at91sam9rl.h> |
||||
#include <asm/arch/at91sam9rl_matrix.h> |
||||
#include <asm/arch/at91sam9_smc.h> |
||||
#include <asm/arch/at91_pmc.h> |
||||
#include <asm/arch/at91_rstc.h> |
||||
#include <asm/arch/gpio.h> |
||||
#include <asm/arch/io.h> |
||||
#include <lcd.h> |
||||
#include <atmel_lcdc.h> |
||||
#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB) |
||||
#include <net.h> |
||||
#endif |
||||
|
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
/* ------------------------------------------------------------------------- */ |
||||
/*
|
||||
* Miscelaneous platform dependent initialisations |
||||
*/ |
||||
|
||||
static void at91sam9rlek_serial_hw_init(void) |
||||
{ |
||||
#ifdef CONFIG_USART0 |
||||
at91_set_A_periph(AT91_PIN_PA6, 1); /* TXD0 */ |
||||
at91_set_A_periph(AT91_PIN_PA7, 0); /* RXD0 */ |
||||
at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US0); |
||||
#endif |
||||
|
||||
#ifdef CONFIG_USART1 |
||||
at91_set_A_periph(AT91_PIN_PA11, 1); /* TXD1 */ |
||||
at91_set_A_periph(AT91_PIN_PA12, 0); /* RXD1 */ |
||||
at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US1); |
||||
#endif |
||||
|
||||
#ifdef CONFIG_USART2 |
||||
at91_set_A_periph(AT91_PIN_PA13, 1); /* TXD2 */ |
||||
at91_set_A_periph(AT91_PIN_PA14, 0); /* RXD2 */ |
||||
at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US2); |
||||
#endif |
||||
|
||||
#ifdef CONFIG_USART3 /* DBGU */ |
||||
at91_set_A_periph(AT91_PIN_PA21, 0); /* DRXD */ |
||||
at91_set_A_periph(AT91_PIN_PA22, 1); /* DTXD */ |
||||
at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_SYS); |
||||
#endif |
||||
} |
||||
|
||||
#ifdef CONFIG_CMD_NAND |
||||
static void at91sam9rlek_nand_hw_init(void) |
||||
{ |
||||
unsigned long csa; |
||||
|
||||
/* Enable CS3 */ |
||||
csa = at91_sys_read(AT91_MATRIX_EBICSA); |
||||
at91_sys_write(AT91_MATRIX_EBICSA, |
||||
csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA); |
||||
|
||||
/* Configure SMC CS3 for NAND/SmartMedia */ |
||||
at91_sys_write(AT91_SMC_SETUP(3), |
||||
AT91_SMC_NWESETUP_(0) | AT91_SMC_NCS_WRSETUP_(0) | |
||||
AT91_SMC_NRDSETUP_(0) | AT91_SMC_NCS_RDSETUP_(0)); |
||||
at91_sys_write(AT91_SMC_PULSE(3), |
||||
AT91_SMC_NWEPULSE_(2) | AT91_SMC_NCS_WRPULSE_(5) | |
||||
AT91_SMC_NRDPULSE_(2) | AT91_SMC_NCS_RDPULSE_(5)); |
||||
at91_sys_write(AT91_SMC_CYCLE(3), |
||||
AT91_SMC_NWECYCLE_(7) | AT91_SMC_NRDCYCLE_(7)); |
||||
at91_sys_write(AT91_SMC_MODE(3), |
||||
AT91_SMC_READMODE | AT91_SMC_WRITEMODE | |
||||
AT91_SMC_EXNWMODE_DISABLE | |
||||
#ifdef CFG_NAND_DBW_16 |
||||
AT91_SMC_DBW_16 | |
||||
#else /* CFG_NAND_DBW_8 */ |
||||
AT91_SMC_DBW_8 | |
||||
#endif |
||||
AT91_SMC_TDF_(1)); |
||||
|
||||
at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9RL_ID_PIOD); |
||||
|
||||
/* Configure RDY/BSY */ |
||||
at91_set_gpio_input(AT91_PIN_PD17, 1); |
||||
|
||||
/* Enable NandFlash */ |
||||
at91_set_gpio_output(AT91_PIN_PB6, 1); |
||||
|
||||
at91_set_A_periph(AT91_PIN_PB4, 0); /* NANDOE */ |
||||
at91_set_A_periph(AT91_PIN_PB5, 0); /* NANDWE */ |
||||
} |
||||
#endif |
||||
|
||||
#ifdef CONFIG_HAS_DATAFLASH |
||||
static void at91sam9rlek_spi_hw_init(void) |
||||
{ |
||||
at91_set_A_periph(AT91_PIN_PA28, 0); /* SPI0_NPCS0 */ |
||||
|
||||
at91_set_A_periph(AT91_PIN_PA25, 0); /* SPI0_MISO */ |
||||
at91_set_A_periph(AT91_PIN_PA26, 0); /* SPI0_MOSI */ |
||||
at91_set_A_periph(AT91_PIN_PA27, 0); /* SPI0_SPCK */ |
||||
|
||||
/* Enable clock */ |
||||
at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9RL_ID_SPI); |
||||
} |
||||
#endif |
||||
|
||||
#ifdef CONFIG_LCD |
||||
vidinfo_t panel_info = { |
||||
vl_col: 240, |
||||
vl_row: 320, |
||||
vl_clk: 4965000, |
||||
vl_sync: ATMEL_LCDC_INVLINE_INVERTED | |
||||
ATMEL_LCDC_INVFRAME_INVERTED, |
||||
vl_bpix: 3, |
||||
vl_tft: 1, |
||||
vl_hsync_len: 5, |
||||
vl_left_margin: 1, |
||||
vl_right_margin:33, |
||||
vl_vsync_len: 1, |
||||
vl_upper_margin:1, |
||||
vl_lower_margin:0, |
||||
mmio: AT91SAM9RL_LCDC_BASE, |
||||
}; |
||||
|
||||
void lcd_enable(void) |
||||
{ |
||||
at91_set_gpio_value(AT91_PIN_PA30, 0); /* power up */ |
||||
} |
||||
|
||||
void lcd_disable(void) |
||||
{ |
||||
at91_set_gpio_value(AT91_PIN_PA30, 1); /* power down */ |
||||
} |
||||
static void at91sam9rlek_lcd_hw_init(void) |
||||
{ |
||||
at91_set_B_periph(AT91_PIN_PC1, 0); /* LCDPWR */ |
||||
at91_set_A_periph(AT91_PIN_PC5, 0); /* LCDHSYNC */ |
||||
at91_set_A_periph(AT91_PIN_PC6, 0); /* LCDDOTCK */ |
||||
at91_set_A_periph(AT91_PIN_PC7, 0); /* LCDDEN */ |
||||
at91_set_A_periph(AT91_PIN_PC3, 0); /* LCDCC */ |
||||
at91_set_B_periph(AT91_PIN_PC9, 0); /* LCDD3 */ |
||||
at91_set_B_periph(AT91_PIN_PC10, 0); /* LCDD4 */ |
||||
at91_set_B_periph(AT91_PIN_PC11, 0); /* LCDD5 */ |
||||
at91_set_B_periph(AT91_PIN_PC12, 0); /* LCDD6 */ |
||||
at91_set_B_periph(AT91_PIN_PC13, 0); /* LCDD7 */ |
||||
at91_set_B_periph(AT91_PIN_PC15, 0); /* LCDD11 */ |
||||
at91_set_B_periph(AT91_PIN_PC16, 0); /* LCDD12 */ |
||||
at91_set_B_periph(AT91_PIN_PC17, 0); /* LCDD13 */ |
||||
at91_set_B_periph(AT91_PIN_PC18, 0); /* LCDD14 */ |
||||
at91_set_B_periph(AT91_PIN_PC19, 0); /* LCDD15 */ |
||||
at91_set_B_periph(AT91_PIN_PC20, 0); /* LCDD18 */ |
||||
at91_set_B_periph(AT91_PIN_PC21, 0); /* LCDD19 */ |
||||
at91_set_B_periph(AT91_PIN_PC22, 0); /* LCDD20 */ |
||||
at91_set_B_periph(AT91_PIN_PC23, 0); /* LCDD21 */ |
||||
at91_set_B_periph(AT91_PIN_PC24, 0); /* LCDD22 */ |
||||
at91_set_B_periph(AT91_PIN_PC25, 0); /* LCDD23 */ |
||||
|
||||
at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9RL_ID_LCDC); |
||||
|
||||
gd->fb_base = 0; |
||||
} |
||||
#endif |
||||
|
||||
|
||||
int board_init(void) |
||||
{ |
||||
/* Enable Ctrlc */ |
||||
console_init_f(); |
||||
|
||||
/* arch number of AT91SAM9RLEK-Board */ |
||||
gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9RLEK; |
||||
/* adress of boot parameters */ |
||||
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; |
||||
|
||||
at91sam9rlek_serial_hw_init(); |
||||
#ifdef CONFIG_CMD_NAND |
||||
at91sam9rlek_nand_hw_init(); |
||||
#endif |
||||
#ifdef CONFIG_HAS_DATAFLASH |
||||
at91sam9rlek_spi_hw_init(); |
||||
#endif |
||||
#ifdef CONFIG_LCD |
||||
at91sam9rlek_lcd_hw_init(); |
||||
#endif |
||||
return 0; |
||||
} |
||||
|
||||
int dram_init(void) |
||||
{ |
||||
gd->bd->bi_dram[0].start = PHYS_SDRAM; |
||||
gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE; |
||||
return 0; |
||||
} |
||||
@ -0,0 +1 @@ |
||||
TEXT_BASE = 0x23f00000
|
||||
@ -0,0 +1,77 @@ |
||||
/*
|
||||
* (C) Copyright 2007-2008 |
||||
* Stelian Pop <stelian.pop@leadtechdesign.com> |
||||
* Lead Tech Design <www.leadtechdesign.com> |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <asm/arch/at91sam9rl.h> |
||||
#include <asm/arch/at91_pmc.h> |
||||
#include <asm/arch/gpio.h> |
||||
#include <asm/arch/io.h> |
||||
|
||||
#define RED_LED AT91_PIN_PD14 /* this is the power led */ |
||||
#define GREEN_LED AT91_PIN_PD15 /* this is the user1 led */ |
||||
#define YELLOW_LED AT91_PIN_PD16 /* this is the user2 led */ |
||||
|
||||
void red_LED_on(void) |
||||
{ |
||||
at91_set_gpio_value(RED_LED, 1); |
||||
} |
||||
|
||||
void red_LED_off(void) |
||||
{ |
||||
at91_set_gpio_value(RED_LED, 0); |
||||
} |
||||
|
||||
void green_LED_on(void) |
||||
{ |
||||
at91_set_gpio_value(GREEN_LED, 0); |
||||
} |
||||
|
||||
void green_LED_off(void) |
||||
{ |
||||
at91_set_gpio_value(GREEN_LED, 1); |
||||
} |
||||
|
||||
void yellow_LED_on(void) |
||||
{ |
||||
at91_set_gpio_value(YELLOW_LED, 0); |
||||
} |
||||
|
||||
void yellow_LED_off(void) |
||||
{ |
||||
at91_set_gpio_value(YELLOW_LED, 1); |
||||
} |
||||
|
||||
void coloured_LED_init(void) |
||||
{ |
||||
/* Enable clock */ |
||||
at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9RL_ID_PIOD); |
||||
|
||||
at91_set_gpio_output(RED_LED, 1); |
||||
at91_set_gpio_output(GREEN_LED, 1); |
||||
at91_set_gpio_output(YELLOW_LED, 1); |
||||
|
||||
at91_set_gpio_value(RED_LED, 0); |
||||
at91_set_gpio_value(GREEN_LED, 1); |
||||
at91_set_gpio_value(YELLOW_LED, 1); |
||||
} |
||||
@ -0,0 +1,79 @@ |
||||
/*
|
||||
* (C) Copyright 2007-2008 |
||||
* Stelian Pop <stelian.pop@leadtechdesign.com> |
||||
* Lead Tech Design <www.leadtechdesign.com> |
||||
* |
||||
* (C) Copyright 2006 ATMEL Rousset, Lacressonniere Nicolas |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <asm/arch/at91sam9rl.h> |
||||
#include <asm/arch/gpio.h> |
||||
#include <asm/arch/at91_pio.h> |
||||
|
||||
#include <nand.h> |
||||
|
||||
/*
|
||||
* hardware specific access to control-lines |
||||
*/ |
||||
#define MASK_ALE (1 << 21) /* our ALE is AD21 */ |
||||
#define MASK_CLE (1 << 22) /* our CLE is AD22 */ |
||||
|
||||
static void at91sam9rlek_nand_hwcontrol(struct mtd_info *mtd, int cmd) |
||||
{ |
||||
struct nand_chip *this = mtd->priv; |
||||
ulong IO_ADDR_W = (ulong) this->IO_ADDR_W; |
||||
|
||||
IO_ADDR_W &= ~(MASK_ALE|MASK_CLE); |
||||
switch (cmd) { |
||||
case NAND_CTL_SETCLE: |
||||
IO_ADDR_W |= MASK_CLE; |
||||
break; |
||||
case NAND_CTL_SETALE: |
||||
IO_ADDR_W |= MASK_ALE; |
||||
break; |
||||
case NAND_CTL_CLRNCE: |
||||
at91_set_gpio_value(AT91_PIN_PB6, 1); |
||||
break; |
||||
case NAND_CTL_SETNCE: |
||||
at91_set_gpio_value(AT91_PIN_PB6, 0); |
||||
break; |
||||
} |
||||
this->IO_ADDR_W = (void *) IO_ADDR_W; |
||||
} |
||||
|
||||
static int at91sam9rlek_nand_ready(struct mtd_info *mtd) |
||||
{ |
||||
return at91_get_gpio_value(AT91_PIN_PD17); |
||||
} |
||||
|
||||
int board_nand_init(struct nand_chip *nand) |
||||
{ |
||||
nand->eccmode = NAND_ECC_SOFT; |
||||
#ifdef CFG_NAND_DBW_16 |
||||
nand->options = NAND_BUSWIDTH_16; |
||||
#endif |
||||
nand->hwcontrol = at91sam9rlek_nand_hwcontrol; |
||||
nand->dev_ready = at91sam9rlek_nand_ready; |
||||
nand->chip_delay = 20; |
||||
|
||||
return 0; |
||||
} |
||||
@ -0,0 +1,39 @@ |
||||
/*
|
||||
* (C) Copyright 2008 |
||||
* Ulf Samuelsson <ulf@atmel.com> |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
* |
||||
*/ |
||||
#include <common.h> |
||||
#include <config.h> |
||||
#include <asm/hardware.h> |
||||
#include <dataflash.h> |
||||
|
||||
AT91S_DATAFLASH_INFO dataflash_info[CFG_MAX_DATAFLASH_BANKS]; |
||||
|
||||
struct dataflash_addr cs[CFG_MAX_DATAFLASH_BANKS] = { |
||||
{CFG_DATAFLASH_LOGIC_ADDR_CS0, 0}, /* Logical adress, CS */ |
||||
}; |
||||
|
||||
/*define the area offsets*/ |
||||
dataflash_protect_t area_list[NB_DATAFLASH_AREA] = { |
||||
{0x00000000, 0x000041FF, FLAG_PROTECT_SET, 0, "Bootstrap"}, |
||||
{0x00004200, 0x000083FF, FLAG_PROTECT_CLEAR, 0, "Environment"}, |
||||
{0x00008400, 0x00041FFF, FLAG_PROTECT_SET, 0, "U-Boot"}, |
||||
{0x00042000, 0x00251FFF, FLAG_PROTECT_CLEAR, 0, "Kernel"}, |
||||
{0x00252000, 0xFFFFFFFF, FLAG_PROTECT_CLEAR, 0, "FS"}, |
||||
}; |
||||
@ -1,2 +1,3 @@ |
||||
PLATFORM_CPPFLAGS += -march=armv5te
|
||||
PLATFORM_CPPFLAGS += $(call cc-option,-mtune=arm926ejs,)
|
||||
LDSCRIPT := $(SRCTREE)/cpu/arm926ejs/at91sam9/u-boot.lds
|
||||
|
||||
@ -0,0 +1,160 @@ |
||||
/*
|
||||
* Driver for AT91/AT32 LCD Controller |
||||
* |
||||
* Copyright (C) 2007 Atmel Corporation |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <asm/io.h> |
||||
#include <asm/arch/hardware.h> |
||||
#include <asm/arch/gpio.h> |
||||
#include <asm/arch/clk.h> |
||||
#include <lcd.h> |
||||
#include <atmel_lcdc.h> |
||||
|
||||
int lcd_line_length; |
||||
int lcd_color_fg; |
||||
int lcd_color_bg; |
||||
|
||||
void *lcd_base; /* Start of framebuffer memory */ |
||||
void *lcd_console_address; /* Start of console buffer */ |
||||
|
||||
short console_col; |
||||
short console_row; |
||||
|
||||
/* configurable parameters */ |
||||
#define ATMEL_LCDC_CVAL_DEFAULT 0xc8 |
||||
#define ATMEL_LCDC_DMA_BURST_LEN 8 |
||||
|
||||
#if defined(CONFIG_AT91SAM9263) || defined(CONFIG_AT91CAP9) |
||||
#define ATMEL_LCDC_FIFO_SIZE 2048 |
||||
#else |
||||
#define ATMEL_LCDC_FIFO_SIZE 512 |
||||
#endif |
||||
|
||||
#define lcdc_readl(mmio, reg) __raw_readl((mmio)+(reg)) |
||||
#define lcdc_writel(mmio, reg, val) __raw_writel((val), (mmio)+(reg)) |
||||
|
||||
void lcd_setcolreg(ushort regno, ushort red, ushort green, ushort blue) |
||||
{ |
||||
#if defined(CONFIG_ATMEL_LCD_BGR555) |
||||
lcdc_writel(panel_info.mmio, ATMEL_LCDC_LUT(regno), |
||||
(red >> 3) | ((green & 0xf8) << 2) | ((blue & 0xf8) << 7)); |
||||
#else |
||||
lcdc_writel(panel_info.mmio, ATMEL_LCDC_LUT(regno), |
||||
(blue >> 3) | ((green & 0xfc) << 3) | ((red & 0xf8) << 8)); |
||||
#endif |
||||
} |
||||
|
||||
void lcd_ctrl_init(void *lcdbase) |
||||
{ |
||||
unsigned long value; |
||||
|
||||
/* Turn off the LCD controller and the DMA controller */ |
||||
lcdc_writel(panel_info.mmio, ATMEL_LCDC_PWRCON, |
||||
1 << ATMEL_LCDC_GUARDT_OFFSET); |
||||
|
||||
/* Wait for the LCDC core to become idle */ |
||||
while (lcdc_readl(panel_info.mmio, ATMEL_LCDC_PWRCON) & ATMEL_LCDC_BUSY) |
||||
udelay(10); |
||||
|
||||
lcdc_writel(panel_info.mmio, ATMEL_LCDC_DMACON, 0); |
||||
|
||||
/* Reset LCDC DMA */ |
||||
lcdc_writel(panel_info.mmio, ATMEL_LCDC_DMACON, ATMEL_LCDC_DMARST); |
||||
|
||||
/* ...set frame size and burst length = 8 words (?) */ |
||||
value = (panel_info.vl_col * panel_info.vl_row * |
||||
NBITS(panel_info.vl_bpix)) / 32; |
||||
value |= ((ATMEL_LCDC_DMA_BURST_LEN - 1) << ATMEL_LCDC_BLENGTH_OFFSET); |
||||
lcdc_writel(panel_info.mmio, ATMEL_LCDC_DMAFRMCFG, value); |
||||
|
||||
/* Set pixel clock */ |
||||
value = get_lcdc_clk_rate(0) / panel_info.vl_clk; |
||||
if (get_lcdc_clk_rate(0) % panel_info.vl_clk) |
||||
value++; |
||||
value = (value / 2) - 1; |
||||
|
||||
if (!value) { |
||||
lcdc_writel(panel_info.mmio, ATMEL_LCDC_LCDCON1, ATMEL_LCDC_BYPASS); |
||||
} else |
||||
lcdc_writel(panel_info.mmio, ATMEL_LCDC_LCDCON1, |
||||
value << ATMEL_LCDC_CLKVAL_OFFSET); |
||||
|
||||
/* Initialize control register 2 */ |
||||
value = ATMEL_LCDC_MEMOR_LITTLE | ATMEL_LCDC_CLKMOD_ALWAYSACTIVE; |
||||
if (panel_info.vl_tft) |
||||
value |= ATMEL_LCDC_DISTYPE_TFT; |
||||
|
||||
if (!(panel_info.vl_sync & ATMEL_LCDC_INVLINE_INVERTED)) |
||||
value |= ATMEL_LCDC_INVLINE_INVERTED; |
||||
if (!(panel_info.vl_sync & ATMEL_LCDC_INVFRAME_INVERTED)) |
||||
value |= ATMEL_LCDC_INVFRAME_INVERTED; |
||||
value |= (panel_info.vl_bpix << 5); |
||||
lcdc_writel(panel_info.mmio, ATMEL_LCDC_LCDCON2, value); |
||||
|
||||
/* Vertical timing */ |
||||
value = (panel_info.vl_vsync_len - 1) << ATMEL_LCDC_VPW_OFFSET; |
||||
value |= panel_info.vl_upper_margin << ATMEL_LCDC_VBP_OFFSET; |
||||
value |= panel_info.vl_lower_margin; |
||||
lcdc_writel(panel_info.mmio, ATMEL_LCDC_TIM1, value); |
||||
|
||||
/* Horizontal timing */ |
||||
value = (panel_info.vl_right_margin - 1) << ATMEL_LCDC_HFP_OFFSET; |
||||
value |= (panel_info.vl_hsync_len - 1) << ATMEL_LCDC_HPW_OFFSET; |
||||
value |= (panel_info.vl_left_margin - 1); |
||||
lcdc_writel(panel_info.mmio, ATMEL_LCDC_TIM2, value); |
||||
|
||||
/* Display size */ |
||||
value = (panel_info.vl_col - 1) << ATMEL_LCDC_HOZVAL_OFFSET; |
||||
value |= panel_info.vl_row - 1; |
||||
lcdc_writel(panel_info.mmio, ATMEL_LCDC_LCDFRMCFG, value); |
||||
|
||||
/* FIFO Threshold: Use formula from data sheet */ |
||||
value = ATMEL_LCDC_FIFO_SIZE - (2 * ATMEL_LCDC_DMA_BURST_LEN + 3); |
||||
lcdc_writel(panel_info.mmio, ATMEL_LCDC_FIFO, value); |
||||
|
||||
/* Toggle LCD_MODE every frame */ |
||||
lcdc_writel(panel_info.mmio, ATMEL_LCDC_MVAL, 0); |
||||
|
||||
/* Disable all interrupts */ |
||||
lcdc_writel(panel_info.mmio, ATMEL_LCDC_IDR, ~0UL); |
||||
|
||||
/* Set contrast */ |
||||
value = ATMEL_LCDC_PS_DIV8 | |
||||
ATMEL_LCDC_POL_POSITIVE | |
||||
ATMEL_LCDC_ENA_PWMENABLE; |
||||
lcdc_writel(panel_info.mmio, ATMEL_LCDC_CONTRAST_CTR, value); |
||||
lcdc_writel(panel_info.mmio, ATMEL_LCDC_CONTRAST_VAL, ATMEL_LCDC_CVAL_DEFAULT); |
||||
|
||||
/* Set framebuffer DMA base address and pixel offset */ |
||||
lcdc_writel(panel_info.mmio, ATMEL_LCDC_DMABADDR1, (u_long)lcdbase); |
||||
|
||||
lcdc_writel(panel_info.mmio, ATMEL_LCDC_DMACON, ATMEL_LCDC_DMAEN); |
||||
lcdc_writel(panel_info.mmio, ATMEL_LCDC_PWRCON, |
||||
(1 << ATMEL_LCDC_GUARDT_OFFSET) | ATMEL_LCDC_PWR); |
||||
} |
||||
|
||||
ulong calc_fbsize(void) |
||||
{ |
||||
return ((panel_info.vl_col * panel_info.vl_row * |
||||
NBITS(panel_info.vl_bpix)) / 8) + PAGE_SIZE; |
||||
} |
||||
@ -0,0 +1,105 @@ |
||||
/*
|
||||
* [origin: Linux kernel include/asm-arm/arch-at91/at91sam9261.h] |
||||
* |
||||
* Copyright (C) SAN People |
||||
* |
||||
* Common definitions. |
||||
* Based on AT91SAM9261 datasheet revision E. (Preliminary) |
||||
* |
||||
* This program is free software; you can redistribute it and/or modify |
||||
* it under the terms of the GNU General Public License as published by |
||||
* the Free Software Foundation; either version 2 of the License, or |
||||
* (at your option) any later version. |
||||
*/ |
||||
|
||||
#ifndef AT91SAM9261_H |
||||
#define AT91SAM9261_H |
||||
|
||||
/*
|
||||
* Peripheral identifiers/interrupts. |
||||
*/ |
||||
#define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */ |
||||
#define AT91_ID_SYS 1 /* System Peripherals */ |
||||
#define AT91SAM9261_ID_PIOA 2 /* Parallel IO Controller A */ |
||||
#define AT91SAM9261_ID_PIOB 3 /* Parallel IO Controller B */ |
||||
#define AT91SAM9261_ID_PIOC 4 /* Parallel IO Controller C */ |
||||
#define AT91SAM9261_ID_US0 6 /* USART 0 */ |
||||
#define AT91SAM9261_ID_US1 7 /* USART 1 */ |
||||
#define AT91SAM9261_ID_US2 8 /* USART 2 */ |
||||
#define AT91SAM9261_ID_MCI 9 /* Multimedia Card Interface */ |
||||
#define AT91SAM9261_ID_UDP 10 /* USB Device Port */ |
||||
#define AT91SAM9261_ID_TWI 11 /* Two-Wire Interface */ |
||||
#define AT91SAM9261_ID_SPI0 12 /* Serial Peripheral Interface 0 */ |
||||
#define AT91SAM9261_ID_SPI1 13 /* Serial Peripheral Interface 1 */ |
||||
#define AT91SAM9261_ID_SSC0 14 /* Serial Synchronous Controller 0 */ |
||||
#define AT91SAM9261_ID_SSC1 15 /* Serial Synchronous Controller 1 */ |
||||
#define AT91SAM9261_ID_SSC2 16 /* Serial Synchronous Controller 2 */ |
||||
#define AT91SAM9261_ID_TC0 17 /* Timer Counter 0 */ |
||||
#define AT91SAM9261_ID_TC1 18 /* Timer Counter 1 */ |
||||
#define AT91SAM9261_ID_TC2 19 /* Timer Counter 2 */ |
||||
#define AT91SAM9261_ID_UHP 20 /* USB Host port */ |
||||
#define AT91SAM9261_ID_LCDC 21 /* LDC Controller */ |
||||
#define AT91SAM9261_ID_IRQ0 29 /* Advanced Interrupt Controller (IRQ0) */ |
||||
#define AT91SAM9261_ID_IRQ1 30 /* Advanced Interrupt Controller (IRQ1) */ |
||||
#define AT91SAM9261_ID_IRQ2 31 /* Advanced Interrupt Controller (IRQ2) */ |
||||
|
||||
|
||||
/*
|
||||
* User Peripheral physical base addresses. |
||||
*/ |
||||
#define AT91SAM9261_BASE_TCB0 0xfffa0000 |
||||
#define AT91SAM9261_BASE_TC0 0xfffa0000 |
||||
#define AT91SAM9261_BASE_TC1 0xfffa0040 |
||||
#define AT91SAM9261_BASE_TC2 0xfffa0080 |
||||
#define AT91SAM9261_BASE_UDP 0xfffa4000 |
||||
#define AT91SAM9261_BASE_MCI 0xfffa8000 |
||||
#define AT91SAM9261_BASE_TWI 0xfffac000 |
||||
#define AT91SAM9261_BASE_US0 0xfffb0000 |
||||
#define AT91SAM9261_BASE_US1 0xfffb4000 |
||||
#define AT91SAM9261_BASE_US2 0xfffb8000 |
||||
#define AT91SAM9261_BASE_SSC0 0xfffbc000 |
||||
#define AT91SAM9261_BASE_SSC1 0xfffc0000 |
||||
#define AT91SAM9261_BASE_SSC2 0xfffc4000 |
||||
#define AT91SAM9261_BASE_SPI0 0xfffc8000 |
||||
#define AT91SAM9261_BASE_SPI1 0xfffcc000 |
||||
#define AT91_BASE_SYS 0xffffea00 |
||||
|
||||
|
||||
/*
|
||||
* System Peripherals (offset from AT91_BASE_SYS) |
||||
*/ |
||||
#define AT91_SDRAMC (0xffffea00 - AT91_BASE_SYS) |
||||
#define AT91_SMC (0xffffec00 - AT91_BASE_SYS) |
||||
#define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS) |
||||
#define AT91_AIC (0xfffff000 - AT91_BASE_SYS) |
||||
#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS) |
||||
#define AT91_PIOA (0xfffff400 - AT91_BASE_SYS) |
||||
#define AT91_PIOB (0xfffff600 - AT91_BASE_SYS) |
||||
#define AT91_PIOC (0xfffff800 - AT91_BASE_SYS) |
||||
#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) |
||||
#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS) |
||||
#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS) |
||||
#define AT91_RTT (0xfffffd20 - AT91_BASE_SYS) |
||||
#define AT91_PIT (0xfffffd30 - AT91_BASE_SYS) |
||||
#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS) |
||||
#define AT91_GPBR (0xfffffd50 - AT91_BASE_SYS) |
||||
|
||||
#define AT91_USART0 AT91SAM9261_BASE_US0 |
||||
#define AT91_USART1 AT91SAM9261_BASE_US1 |
||||
#define AT91_USART2 AT91SAM9261_BASE_US2 |
||||
|
||||
|
||||
/*
|
||||
* Internal Memory. |
||||
*/ |
||||
#define AT91SAM9261_SRAM_BASE 0x00300000 /* Internal SRAM base address */ |
||||
#define AT91SAM9261_SRAM_SIZE 0x00028000 /* Internal SRAM size (160Kb) */ |
||||
|
||||
#define AT91SAM9261_ROM_BASE 0x00400000 /* Internal ROM base address */ |
||||
#define AT91SAM9261_ROM_SIZE SZ_32K /* Internal ROM size (32Kb) */ |
||||
|
||||
#define AT91SAM9261_UHP_BASE 0x00500000 /* USB Host controller */ |
||||
#define AT91SAM9261_LCDC_BASE 0x00600000 /* LDC controller */ |
||||
|
||||
|
||||
#endif |
||||
@ -0,0 +1,64 @@ |
||||
/*
|
||||
* [origin: Linux kernel include/asm-arm/arch-at91/at91sam9261_matrix.h] |
||||
* |
||||
* Copyright (C) 2007 Atmel Corporation. |
||||
* |
||||
* Memory Controllers (MATRIX, EBI) - System peripherals registers. |
||||
* Based on AT91SAM9261 datasheet revision D. |
||||
* |
||||
* This program is free software; you can redistribute it and/or modify |
||||
* it under the terms of the GNU General Public License as published by |
||||
* the Free Software Foundation; either version 2 of the License, or |
||||
* (at your option) any later version. |
||||
*/ |
||||
|
||||
#ifndef AT91SAM9261_MATRIX_H |
||||
#define AT91SAM9261_MATRIX_H |
||||
|
||||
#define AT91_MATRIX_MCFG (AT91_MATRIX + 0x00) /* Master Configuration Register */ |
||||
#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */ |
||||
#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */ |
||||
|
||||
#define AT91_MATRIX_SCFG0 (AT91_MATRIX + 0x04) /* Slave Configuration Register 0 */ |
||||
#define AT91_MATRIX_SCFG1 (AT91_MATRIX + 0x08) /* Slave Configuration Register 1 */ |
||||
#define AT91_MATRIX_SCFG2 (AT91_MATRIX + 0x0C) /* Slave Configuration Register 2 */ |
||||
#define AT91_MATRIX_SCFG3 (AT91_MATRIX + 0x10) /* Slave Configuration Register 3 */ |
||||
#define AT91_MATRIX_SCFG4 (AT91_MATRIX + 0x14) /* Slave Configuration Register 4 */ |
||||
#define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */ |
||||
#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */ |
||||
#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16) |
||||
#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16) |
||||
#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16) |
||||
#define AT91_MATRIX_FIXED_DEFMSTR (7 << 18) /* Fixed Index of Default Master */ |
||||
|
||||
#define AT91_MATRIX_TCR (AT91_MATRIX + 0x24) /* TCM Configuration Register */ |
||||
#define AT91_MATRIX_ITCM_SIZE (0xf << 0) /* Size of ITCM enabled memory block */ |
||||
#define AT91_MATRIX_ITCM_0 (0 << 0) |
||||
#define AT91_MATRIX_ITCM_16 (5 << 0) |
||||
#define AT91_MATRIX_ITCM_32 (6 << 0) |
||||
#define AT91_MATRIX_ITCM_64 (7 << 0) |
||||
#define AT91_MATRIX_DTCM_SIZE (0xf << 4) /* Size of DTCM enabled memory block */ |
||||
#define AT91_MATRIX_DTCM_0 (0 << 4) |
||||
#define AT91_MATRIX_DTCM_16 (5 << 4) |
||||
#define AT91_MATRIX_DTCM_32 (6 << 4) |
||||
#define AT91_MATRIX_DTCM_64 (7 << 4) |
||||
|
||||
#define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x30) /* EBI Chip Select Assignment Register */ |
||||
#define AT91_MATRIX_CS1A (1 << 1) /* Chip Select 1 Assignment */ |
||||
#define AT91_MATRIX_CS1A_SMC (0 << 1) |
||||
#define AT91_MATRIX_CS1A_SDRAMC (1 << 1) |
||||
#define AT91_MATRIX_CS3A (1 << 3) /* Chip Select 3 Assignment */ |
||||
#define AT91_MATRIX_CS3A_SMC (0 << 3) |
||||
#define AT91_MATRIX_CS3A_SMC_SMARTMEDIA (1 << 3) |
||||
#define AT91_MATRIX_CS4A (1 << 4) /* Chip Select 4 Assignment */ |
||||
#define AT91_MATRIX_CS4A_SMC (0 << 4) |
||||
#define AT91_MATRIX_CS4A_SMC_CF1 (1 << 4) |
||||
#define AT91_MATRIX_CS5A (1 << 5) /* Chip Select 5 Assignment */ |
||||
#define AT91_MATRIX_CS5A_SMC (0 << 5) |
||||
#define AT91_MATRIX_CS5A_SMC_CF2 (1 << 5) |
||||
#define AT91_MATRIX_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */ |
||||
|
||||
#define AT91_MATRIX_USBPUCR (AT91_MATRIX + 0x34) /* USB Pad Pull-Up Control Register */ |
||||
#define AT91_MATRIX_USBPUCR_PUON (1 << 30) /* USB Device PAD Pull-up Enable */ |
||||
|
||||
#endif |
||||
@ -0,0 +1,127 @@ |
||||
/*
|
||||
* [origin: Linux kernel include/asm-arm/arch-at91/at91sam9263.h] |
||||
* |
||||
* (C) 2007 Atmel Corporation. |
||||
* |
||||
* Common definitions. |
||||
* Based on AT91SAM9263 datasheet revision B (Preliminary). |
||||
* |
||||
* This program is free software; you can redistribute it and/or modify |
||||
* it under the terms of the GNU General Public License as published by |
||||
* the Free Software Foundation; either version 2 of the License, or |
||||
* (at your option) any later version. |
||||
*/ |
||||
|
||||
#ifndef AT91SAM9263_H |
||||
#define AT91SAM9263_H |
||||
|
||||
/*
|
||||
* Peripheral identifiers/interrupts. |
||||
*/ |
||||
#define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */ |
||||
#define AT91_ID_SYS 1 /* System Peripherals */ |
||||
#define AT91SAM9263_ID_PIOA 2 /* Parallel IO Controller A */ |
||||
#define AT91SAM9263_ID_PIOB 3 /* Parallel IO Controller B */ |
||||
#define AT91SAM9263_ID_PIOCDE 4 /* Parallel IO Controller C, D and E */ |
||||
#define AT91SAM9263_ID_US0 7 /* USART 0 */ |
||||
#define AT91SAM9263_ID_US1 8 /* USART 1 */ |
||||
#define AT91SAM9263_ID_US2 9 /* USART 2 */ |
||||
#define AT91SAM9263_ID_MCI0 10 /* Multimedia Card Interface 0 */ |
||||
#define AT91SAM9263_ID_MCI1 11 /* Multimedia Card Interface 1 */ |
||||
#define AT91SAM9263_ID_CAN 12 /* CAN */ |
||||
#define AT91SAM9263_ID_TWI 13 /* Two-Wire Interface */ |
||||
#define AT91SAM9263_ID_SPI0 14 /* Serial Peripheral Interface 0 */ |
||||
#define AT91SAM9263_ID_SPI1 15 /* Serial Peripheral Interface 1 */ |
||||
#define AT91SAM9263_ID_SSC0 16 /* Serial Synchronous Controller 0 */ |
||||
#define AT91SAM9263_ID_SSC1 17 /* Serial Synchronous Controller 1 */ |
||||
#define AT91SAM9263_ID_AC97C 18 /* AC97 Controller */ |
||||
#define AT91SAM9263_ID_TCB 19 /* Timer Counter 0, 1 and 2 */ |
||||
#define AT91SAM9263_ID_PWMC 20 /* Pulse Width Modulation Controller */ |
||||
#define AT91SAM9263_ID_EMAC 21 /* Ethernet */ |
||||
#define AT91SAM9263_ID_2DGE 23 /* 2D Graphic Engine */ |
||||
#define AT91SAM9263_ID_UDP 24 /* USB Device Port */ |
||||
#define AT91SAM9263_ID_ISI 25 /* Image Sensor Interface */ |
||||
#define AT91SAM9263_ID_LCDC 26 /* LCD Controller */ |
||||
#define AT91SAM9263_ID_DMA 27 /* DMA Controller */ |
||||
#define AT91SAM9263_ID_UHP 29 /* USB Host port */ |
||||
#define AT91SAM9263_ID_IRQ0 30 /* Advanced Interrupt Controller (IRQ0) */ |
||||
#define AT91SAM9263_ID_IRQ1 31 /* Advanced Interrupt Controller (IRQ1) */ |
||||
|
||||
|
||||
/*
|
||||
* User Peripheral physical base addresses. |
||||
*/ |
||||
#define AT91SAM9263_BASE_UDP 0xfff78000 |
||||
#define AT91SAM9263_BASE_TCB0 0xfff7c000 |
||||
#define AT91SAM9263_BASE_TC0 0xfff7c000 |
||||
#define AT91SAM9263_BASE_TC1 0xfff7c040 |
||||
#define AT91SAM9263_BASE_TC2 0xfff7c080 |
||||
#define AT91SAM9263_BASE_MCI0 0xfff80000 |
||||
#define AT91SAM9263_BASE_MCI1 0xfff84000 |
||||
#define AT91SAM9263_BASE_TWI 0xfff88000 |
||||
#define AT91SAM9263_BASE_US0 0xfff8c000 |
||||
#define AT91SAM9263_BASE_US1 0xfff90000 |
||||
#define AT91SAM9263_BASE_US2 0xfff94000 |
||||
#define AT91SAM9263_BASE_SSC0 0xfff98000 |
||||
#define AT91SAM9263_BASE_SSC1 0xfff9c000 |
||||
#define AT91SAM9263_BASE_AC97C 0xfffa0000 |
||||
#define AT91SAM9263_BASE_SPI0 0xfffa4000 |
||||
#define AT91SAM9263_BASE_SPI1 0xfffa8000 |
||||
#define AT91SAM9263_BASE_CAN 0xfffac000 |
||||
#define AT91SAM9263_BASE_PWMC 0xfffb8000 |
||||
#define AT91SAM9263_BASE_EMAC 0xfffbc000 |
||||
#define AT91SAM9263_BASE_ISI 0xfffc4000 |
||||
#define AT91SAM9263_BASE_2DGE 0xfffc8000 |
||||
#define AT91_BASE_SYS 0xffffe000 |
||||
|
||||
/*
|
||||
* System Peripherals (offset from AT91_BASE_SYS) |
||||
*/ |
||||
#define AT91_ECC0 (0xffffe000 - AT91_BASE_SYS) |
||||
#define AT91_SDRAMC0 (0xffffe200 - AT91_BASE_SYS) |
||||
#define AT91_SMC0 (0xffffe400 - AT91_BASE_SYS) |
||||
#define AT91_ECC1 (0xffffe600 - AT91_BASE_SYS) |
||||
#define AT91_SDRAMC1 (0xffffe800 - AT91_BASE_SYS) |
||||
#define AT91_SMC1 (0xffffea00 - AT91_BASE_SYS) |
||||
#define AT91_MATRIX (0xffffec00 - AT91_BASE_SYS) |
||||
#define AT91_CCFG (0xffffed10 - AT91_BASE_SYS) |
||||
#define AT91_DBGU (0xffffee00 - AT91_BASE_SYS) |
||||
#define AT91_AIC (0xfffff000 - AT91_BASE_SYS) |
||||
#define AT91_PIOA (0xfffff200 - AT91_BASE_SYS) |
||||
#define AT91_PIOB (0xfffff400 - AT91_BASE_SYS) |
||||
#define AT91_PIOC (0xfffff600 - AT91_BASE_SYS) |
||||
#define AT91_PIOD (0xfffff800 - AT91_BASE_SYS) |
||||
#define AT91_PIOE (0xfffffa00 - AT91_BASE_SYS) |
||||
#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) |
||||
#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS) |
||||
#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS) |
||||
#define AT91_RTT0 (0xfffffd20 - AT91_BASE_SYS) |
||||
#define AT91_PIT (0xfffffd30 - AT91_BASE_SYS) |
||||
#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS) |
||||
#define AT91_RTT1 (0xfffffd50 - AT91_BASE_SYS) |
||||
#define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS) |
||||
|
||||
#define AT91_USART0 AT91SAM9263_BASE_US0 |
||||
#define AT91_USART1 AT91SAM9263_BASE_US1 |
||||
#define AT91_USART2 AT91SAM9263_BASE_US2 |
||||
|
||||
#define AT91_SMC AT91_SMC0 |
||||
|
||||
/*
|
||||
* Internal Memory. |
||||
*/ |
||||
#define AT91SAM9263_SRAM0_BASE 0x00300000 /* Internal SRAM 0 base address */ |
||||
#define AT91SAM9263_SRAM0_SIZE (80 * SZ_1K) /* Internal SRAM 0 size (80Kb) */ |
||||
|
||||
#define AT91SAM9263_ROM_BASE 0x00400000 /* Internal ROM base address */ |
||||
#define AT91SAM9263_ROM_SIZE SZ_128K /* Internal ROM size (128Kb) */ |
||||
|
||||
#define AT91SAM9263_SRAM1_BASE 0x00500000 /* Internal SRAM 1 base address */ |
||||
#define AT91SAM9263_SRAM1_SIZE SZ_16K /* Internal SRAM 1 size (16Kb) */ |
||||
|
||||
#define AT91SAM9263_LCDC_BASE 0x00700000 /* LCD Controller */ |
||||
#define AT91SAM9263_DMAC_BASE 0x00800000 /* DMA Controller */ |
||||
#define AT91SAM9263_UHP_BASE 0x00a00000 /* USB Host controller */ |
||||
|
||||
|
||||
#endif |
||||
@ -0,0 +1,129 @@ |
||||
/*
|
||||
* [origin: Linux kernel include/asm-arm/arch-at91/at91sam9263_matrix.h] |
||||
* |
||||
* Copyright (C) 2006 Atmel Corporation. |
||||
* |
||||
* Memory Controllers (MATRIX, EBI) - System peripherals registers. |
||||
* Based on AT91SAM9263 datasheet revision B (Preliminary). |
||||
* |
||||
* This program is free software; you can redistribute it and/or modify |
||||
* it under the terms of the GNU General Public License as published by |
||||
* the Free Software Foundation; either version 2 of the License, or |
||||
* (at your option) any later version. |
||||
*/ |
||||
|
||||
#ifndef AT91SAM9263_MATRIX_H |
||||
#define AT91SAM9263_MATRIX_H |
||||
|
||||
#define AT91_MATRIX_MCFG0 (AT91_MATRIX + 0x00) /* Master Configuration Register 0 */ |
||||
#define AT91_MATRIX_MCFG1 (AT91_MATRIX + 0x04) /* Master Configuration Register 1 */ |
||||
#define AT91_MATRIX_MCFG2 (AT91_MATRIX + 0x08) /* Master Configuration Register 2 */ |
||||
#define AT91_MATRIX_MCFG3 (AT91_MATRIX + 0x0C) /* Master Configuration Register 3 */ |
||||
#define AT91_MATRIX_MCFG4 (AT91_MATRIX + 0x10) /* Master Configuration Register 4 */ |
||||
#define AT91_MATRIX_MCFG5 (AT91_MATRIX + 0x14) /* Master Configuration Register 5 */ |
||||
#define AT91_MATRIX_MCFG6 (AT91_MATRIX + 0x18) /* Master Configuration Register 6 */ |
||||
#define AT91_MATRIX_MCFG7 (AT91_MATRIX + 0x1C) /* Master Configuration Register 7 */ |
||||
#define AT91_MATRIX_MCFG8 (AT91_MATRIX + 0x20) /* Master Configuration Register 8 */ |
||||
#define AT91_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */ |
||||
#define AT91_MATRIX_ULBT_INFINITE (0 << 0) |
||||
#define AT91_MATRIX_ULBT_SINGLE (1 << 0) |
||||
#define AT91_MATRIX_ULBT_FOUR (2 << 0) |
||||
#define AT91_MATRIX_ULBT_EIGHT (3 << 0) |
||||
#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0) |
||||
|
||||
#define AT91_MATRIX_SCFG0 (AT91_MATRIX + 0x40) /* Slave Configuration Register 0 */ |
||||
#define AT91_MATRIX_SCFG1 (AT91_MATRIX + 0x44) /* Slave Configuration Register 1 */ |
||||
#define AT91_MATRIX_SCFG2 (AT91_MATRIX + 0x48) /* Slave Configuration Register 2 */ |
||||
#define AT91_MATRIX_SCFG3 (AT91_MATRIX + 0x4C) /* Slave Configuration Register 3 */ |
||||
#define AT91_MATRIX_SCFG4 (AT91_MATRIX + 0x50) /* Slave Configuration Register 4 */ |
||||
#define AT91_MATRIX_SCFG5 (AT91_MATRIX + 0x54) /* Slave Configuration Register 5 */ |
||||
#define AT91_MATRIX_SCFG6 (AT91_MATRIX + 0x58) /* Slave Configuration Register 6 */ |
||||
#define AT91_MATRIX_SCFG7 (AT91_MATRIX + 0x5C) /* Slave Configuration Register 7 */ |
||||
#define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */ |
||||
#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */ |
||||
#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16) |
||||
#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16) |
||||
#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16) |
||||
#define AT91_MATRIX_FIXED_DEFMSTR (0xf << 18) /* Fixed Index of Default Master */ |
||||
#define AT91_MATRIX_ARBT (3 << 24) /* Arbitration Type */ |
||||
#define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24) |
||||
#define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24) |
||||
|
||||
#define AT91_MATRIX_PRAS0 (AT91_MATRIX + 0x80) /* Priority Register A for Slave 0 */ |
||||
#define AT91_MATRIX_PRBS0 (AT91_MATRIX + 0x84) /* Priority Register B for Slave 0 */ |
||||
#define AT91_MATRIX_PRAS1 (AT91_MATRIX + 0x88) /* Priority Register A for Slave 1 */ |
||||
#define AT91_MATRIX_PRBS1 (AT91_MATRIX + 0x8C) /* Priority Register B for Slave 1 */ |
||||
#define AT91_MATRIX_PRAS2 (AT91_MATRIX + 0x90) /* Priority Register A for Slave 2 */ |
||||
#define AT91_MATRIX_PRBS2 (AT91_MATRIX + 0x94) /* Priority Register B for Slave 2 */ |
||||
#define AT91_MATRIX_PRAS3 (AT91_MATRIX + 0x98) /* Priority Register A for Slave 3 */ |
||||
#define AT91_MATRIX_PRBS3 (AT91_MATRIX + 0x9C) /* Priority Register B for Slave 3 */ |
||||
#define AT91_MATRIX_PRAS4 (AT91_MATRIX + 0xA0) /* Priority Register A for Slave 4 */ |
||||
#define AT91_MATRIX_PRBS4 (AT91_MATRIX + 0xA4) /* Priority Register B for Slave 4 */ |
||||
#define AT91_MATRIX_PRAS5 (AT91_MATRIX + 0xA8) /* Priority Register A for Slave 5 */ |
||||
#define AT91_MATRIX_PRBS5 (AT91_MATRIX + 0xAC) /* Priority Register B for Slave 5 */ |
||||
#define AT91_MATRIX_PRAS6 (AT91_MATRIX + 0xB0) /* Priority Register A for Slave 6 */ |
||||
#define AT91_MATRIX_PRBS6 (AT91_MATRIX + 0xB4) /* Priority Register B for Slave 6 */ |
||||
#define AT91_MATRIX_PRAS7 (AT91_MATRIX + 0xB8) /* Priority Register A for Slave 7 */ |
||||
#define AT91_MATRIX_PRBS7 (AT91_MATRIX + 0xBC) /* Priority Register B for Slave 7 */ |
||||
#define AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */ |
||||
#define AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */ |
||||
#define AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */ |
||||
#define AT91_MATRIX_M3PR (3 << 12) /* Master 3 Priority */ |
||||
#define AT91_MATRIX_M4PR (3 << 16) /* Master 4 Priority */ |
||||
#define AT91_MATRIX_M5PR (3 << 20) /* Master 5 Priority */ |
||||
#define AT91_MATRIX_M6PR (3 << 24) /* Master 6 Priority */ |
||||
#define AT91_MATRIX_M7PR (3 << 28) /* Master 7 Priority */ |
||||
#define AT91_MATRIX_M8PR (3 << 0) /* Master 8 Priority (in Register B) */ |
||||
|
||||
#define AT91_MATRIX_MRCR (AT91_MATRIX + 0x100) /* Master Remap Control Register */ |
||||
#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */ |
||||
#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */ |
||||
#define AT91_MATRIX_RCB2 (1 << 2) |
||||
#define AT91_MATRIX_RCB3 (1 << 3) |
||||
#define AT91_MATRIX_RCB4 (1 << 4) |
||||
#define AT91_MATRIX_RCB5 (1 << 5) |
||||
#define AT91_MATRIX_RCB6 (1 << 6) |
||||
#define AT91_MATRIX_RCB7 (1 << 7) |
||||
#define AT91_MATRIX_RCB8 (1 << 8) |
||||
|
||||
#define AT91_MATRIX_TCMR (AT91_MATRIX + 0x114) /* TCM Configuration Register */ |
||||
#define AT91_MATRIX_ITCM_SIZE (0xf << 0) /* Size of ITCM enabled memory block */ |
||||
#define AT91_MATRIX_ITCM_0 (0 << 0) |
||||
#define AT91_MATRIX_ITCM_16 (5 << 0) |
||||
#define AT91_MATRIX_ITCM_32 (6 << 0) |
||||
#define AT91_MATRIX_DTCM_SIZE (0xf << 4) /* Size of DTCM enabled memory block */ |
||||
#define AT91_MATRIX_DTCM_0 (0 << 4) |
||||
#define AT91_MATRIX_DTCM_16 (5 << 4) |
||||
#define AT91_MATRIX_DTCM_32 (6 << 4) |
||||
|
||||
#define AT91_MATRIX_EBI0CSA (AT91_MATRIX + 0x120) /* EBI0 Chip Select Assignment Register */ |
||||
#define AT91_MATRIX_EBI0_CS1A (1 << 1) /* Chip Select 1 Assignment */ |
||||
#define AT91_MATRIX_EBI0_CS1A_SMC (0 << 1) |
||||
#define AT91_MATRIX_EBI0_CS1A_SDRAMC (1 << 1) |
||||
#define AT91_MATRIX_EBI0_CS3A (1 << 3) /* Chip Select 3 Assignment */ |
||||
#define AT91_MATRIX_EBI0_CS3A_SMC (0 << 3) |
||||
#define AT91_MATRIX_EBI0_CS3A_SMC_SMARTMEDIA (1 << 3) |
||||
#define AT91_MATRIX_EBI0_CS4A (1 << 4) /* Chip Select 4 Assignment */ |
||||
#define AT91_MATRIX_EBI0_CS4A_SMC (0 << 4) |
||||
#define AT91_MATRIX_EBI0_CS4A_SMC_CF1 (1 << 4) |
||||
#define AT91_MATRIX_EBI0_CS5A (1 << 5) /* Chip Select 5 Assignment */ |
||||
#define AT91_MATRIX_EBI0_CS5A_SMC (0 << 5) |
||||
#define AT91_MATRIX_EBI0_CS5A_SMC_CF2 (1 << 5) |
||||
#define AT91_MATRIX_EBI0_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */ |
||||
#define AT91_MATRIX_EBI0_VDDIOMSEL (1 << 16) /* Memory voltage selection */ |
||||
#define AT91_MATRIX_EBI0_VDDIOMSEL_1_8V (0 << 16) |
||||
#define AT91_MATRIX_EBI0_VDDIOMSEL_3_3V (1 << 16) |
||||
|
||||
#define AT91_MATRIX_EBI1CSA (AT91_MATRIX + 0x124) /* EBI1 Chip Select Assignment Register */ |
||||
#define AT91_MATRIX_EBI1_CS1A (1 << 1) /* Chip Select 1 Assignment */ |
||||
#define AT91_MATRIX_EBI1_CS1A_SMC (0 << 1) |
||||
#define AT91_MATRIX_EBI1_CS1A_SDRAMC (1 << 1) |
||||
#define AT91_MATRIX_EBI1_CS2A (1 << 3) /* Chip Select 3 Assignment */ |
||||
#define AT91_MATRIX_EBI1_CS2A_SMC (0 << 3) |
||||
#define AT91_MATRIX_EBI1_CS2A_SMC_SMARTMEDIA (1 << 3) |
||||
#define AT91_MATRIX_EBI1_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */ |
||||
#define AT91_MATRIX_EBI1_VDDIOMSEL (1 << 16) /* Memory voltage selection */ |
||||
#define AT91_MATRIX_EBI1_VDDIOMSEL_1_8V (0 << 16) |
||||
#define AT91_MATRIX_EBI1_VDDIOMSEL_3_3V (1 << 16) |
||||
|
||||
#endif |
||||
@ -0,0 +1,115 @@ |
||||
/*
|
||||
* [origin: Linux kernel include/asm-arm/arch-at91/at91sam9rl.h] |
||||
* |
||||
* Copyright (C) 2007 Atmel Corporation |
||||
* |
||||
* Common definitions. |
||||
* Based on AT91SAM9RL datasheet revision A. (Preliminary) |
||||
* |
||||
* This file is subject to the terms and conditions of the GNU General Public |
||||
* License. See the file COPYING in the main directory of this archive for |
||||
* more details. |
||||
*/ |
||||
|
||||
#ifndef AT91SAM9RL_H |
||||
#define AT91SAM9RL_H |
||||
|
||||
/*
|
||||
* Peripheral identifiers/interrupts. |
||||
*/ |
||||
#define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */ |
||||
#define AT91_ID_SYS 1 /* System Controller */ |
||||
#define AT91SAM9RL_ID_PIOA 2 /* Parallel IO Controller A */ |
||||
#define AT91SAM9RL_ID_PIOB 3 /* Parallel IO Controller B */ |
||||
#define AT91SAM9RL_ID_PIOC 4 /* Parallel IO Controller C */ |
||||
#define AT91SAM9RL_ID_PIOD 5 /* Parallel IO Controller D */ |
||||
#define AT91SAM9RL_ID_US0 6 /* USART 0 */ |
||||
#define AT91SAM9RL_ID_US1 7 /* USART 1 */ |
||||
#define AT91SAM9RL_ID_US2 8 /* USART 2 */ |
||||
#define AT91SAM9RL_ID_US3 9 /* USART 3 */ |
||||
#define AT91SAM9RL_ID_MCI 10 /* Multimedia Card Interface */ |
||||
#define AT91SAM9RL_ID_TWI0 11 /* TWI 0 */ |
||||
#define AT91SAM9RL_ID_TWI1 12 /* TWI 1 */ |
||||
#define AT91SAM9RL_ID_SPI 13 /* Serial Peripheral Interface */ |
||||
#define AT91SAM9RL_ID_SSC0 14 /* Serial Synchronous Controller 0 */ |
||||
#define AT91SAM9RL_ID_SSC1 15 /* Serial Synchronous Controller 1 */ |
||||
#define AT91SAM9RL_ID_TC0 16 /* Timer Counter 0 */ |
||||
#define AT91SAM9RL_ID_TC1 17 /* Timer Counter 1 */ |
||||
#define AT91SAM9RL_ID_TC2 18 /* Timer Counter 2 */ |
||||
#define AT91SAM9RL_ID_PWMC 19 /* Pulse Width Modulation Controller */ |
||||
#define AT91SAM9RL_ID_TSC 20 /* Touch Screen Controller */ |
||||
#define AT91SAM9RL_ID_DMA 21 /* DMA Controller */ |
||||
#define AT91SAM9RL_ID_UDPHS 22 /* USB Device HS */ |
||||
#define AT91SAM9RL_ID_LCDC 23 /* LCD Controller */ |
||||
#define AT91SAM9RL_ID_AC97C 24 /* AC97 Controller */ |
||||
#define AT91SAM9RL_ID_IRQ0 31 /* Advanced Interrupt Controller (IRQ0) */ |
||||
|
||||
|
||||
/*
|
||||
* User Peripheral physical base addresses. |
||||
*/ |
||||
#define AT91SAM9RL_BASE_TCB0 0xfffa0000 |
||||
#define AT91SAM9RL_BASE_TC0 0xfffa0000 |
||||
#define AT91SAM9RL_BASE_TC1 0xfffa0040 |
||||
#define AT91SAM9RL_BASE_TC2 0xfffa0080 |
||||
#define AT91SAM9RL_BASE_MCI 0xfffa4000 |
||||
#define AT91SAM9RL_BASE_TWI0 0xfffa8000 |
||||
#define AT91SAM9RL_BASE_TWI1 0xfffac000 |
||||
#define AT91SAM9RL_BASE_US0 0xfffb0000 |
||||
#define AT91SAM9RL_BASE_US1 0xfffb4000 |
||||
#define AT91SAM9RL_BASE_US2 0xfffb8000 |
||||
#define AT91SAM9RL_BASE_US3 0xfffbc000 |
||||
#define AT91SAM9RL_BASE_SSC0 0xfffc0000 |
||||
#define AT91SAM9RL_BASE_SSC1 0xfffc4000 |
||||
#define AT91SAM9RL_BASE_PWMC 0xfffc8000 |
||||
#define AT91SAM9RL_BASE_SPI 0xfffcc000 |
||||
#define AT91SAM9RL_BASE_TSC 0xfffd0000 |
||||
#define AT91SAM9RL_BASE_UDPHS 0xfffd4000 |
||||
#define AT91SAM9RL_BASE_AC97C 0xfffd8000 |
||||
#define AT91_BASE_SYS 0xffffc000 |
||||
|
||||
|
||||
/*
|
||||
* System Peripherals (offset from AT91_BASE_SYS) |
||||
*/ |
||||
#define AT91_DMA (0xffffe600 - AT91_BASE_SYS) |
||||
#define AT91_ECC (0xffffe800 - AT91_BASE_SYS) |
||||
#define AT91_SDRAMC (0xffffea00 - AT91_BASE_SYS) |
||||
#define AT91_SMC (0xffffec00 - AT91_BASE_SYS) |
||||
#define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS) |
||||
#define AT91_CCFG (0xffffef10 - AT91_BASE_SYS) |
||||
#define AT91_AIC (0xfffff000 - AT91_BASE_SYS) |
||||
#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS) |
||||
#define AT91_PIOA (0xfffff400 - AT91_BASE_SYS) |
||||
#define AT91_PIOB (0xfffff600 - AT91_BASE_SYS) |
||||
#define AT91_PIOC (0xfffff800 - AT91_BASE_SYS) |
||||
#define AT91_PIOD (0xfffffa00 - AT91_BASE_SYS) |
||||
#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) |
||||
#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS) |
||||
#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS) |
||||
#define AT91_RTT (0xfffffd20 - AT91_BASE_SYS) |
||||
#define AT91_PIT (0xfffffd30 - AT91_BASE_SYS) |
||||
#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS) |
||||
#define AT91_SCKCR (0xfffffd50 - AT91_BASE_SYS) |
||||
#define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS) |
||||
#define AT91_RTC (0xfffffe00 - AT91_BASE_SYS) |
||||
|
||||
#define AT91_USART0 AT91SAM9RL_BASE_US0 |
||||
#define AT91_USART1 AT91SAM9RL_BASE_US1 |
||||
#define AT91_USART2 AT91SAM9RL_BASE_US2 |
||||
#define AT91_USART3 AT91SAM9RL_BASE_US3 |
||||
|
||||
|
||||
/*
|
||||
* Internal Memory. |
||||
*/ |
||||
#define AT91SAM9RL_SRAM_BASE 0x00300000 /* Internal SRAM base address */ |
||||
#define AT91SAM9RL_SRAM_SIZE SZ_16K /* Internal SRAM size (16Kb) */ |
||||
|
||||
#define AT91SAM9RL_ROM_BASE 0x00400000 /* Internal ROM base address */ |
||||
#define AT91SAM9RL_ROM_SIZE (2 * SZ_16K) /* Internal ROM size (32Kb) */ |
||||
|
||||
#define AT91SAM9RL_LCDC_BASE 0x00500000 /* LCD Controller */ |
||||
#define AT91SAM9RL_UDPHS_BASE 0x00600000 /* USB Device HS controller */ |
||||
|
||||
#endif |
||||
@ -0,0 +1,96 @@ |
||||
/*
|
||||
* [origin: Linux kernel include/asm-arm/arch-at91/at91sam9rl_matrix.h] |
||||
* |
||||
* Copyright (C) 2007 Atmel Corporation |
||||
* |
||||
* Memory Controllers (MATRIX, EBI) - System peripherals registers. |
||||
* Based on AT91SAM9RL datasheet revision A. (Preliminary) |
||||
* |
||||
* This file is subject to the terms and conditions of the GNU General Public |
||||
* License. See the file COPYING in the main directory of this archive for |
||||
* more details. |
||||
*/ |
||||
|
||||
#ifndef AT91SAM9RL_MATRIX_H |
||||
#define AT91SAM9RL_MATRIX_H |
||||
|
||||
#define AT91_MATRIX_MCFG0 (AT91_MATRIX + 0x00) /* Master Configuration Register 0 */ |
||||
#define AT91_MATRIX_MCFG1 (AT91_MATRIX + 0x04) /* Master Configuration Register 1 */ |
||||
#define AT91_MATRIX_MCFG2 (AT91_MATRIX + 0x08) /* Master Configuration Register 2 */ |
||||
#define AT91_MATRIX_MCFG3 (AT91_MATRIX + 0x0C) /* Master Configuration Register 3 */ |
||||
#define AT91_MATRIX_MCFG4 (AT91_MATRIX + 0x10) /* Master Configuration Register 4 */ |
||||
#define AT91_MATRIX_MCFG5 (AT91_MATRIX + 0x14) /* Master Configuration Register 5 */ |
||||
#define AT91_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */ |
||||
#define AT91_MATRIX_ULBT_INFINITE (0 << 0) |
||||
#define AT91_MATRIX_ULBT_SINGLE (1 << 0) |
||||
#define AT91_MATRIX_ULBT_FOUR (2 << 0) |
||||
#define AT91_MATRIX_ULBT_EIGHT (3 << 0) |
||||
#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0) |
||||
|
||||
#define AT91_MATRIX_SCFG0 (AT91_MATRIX + 0x40) /* Slave Configuration Register 0 */ |
||||
#define AT91_MATRIX_SCFG1 (AT91_MATRIX + 0x44) /* Slave Configuration Register 1 */ |
||||
#define AT91_MATRIX_SCFG2 (AT91_MATRIX + 0x48) /* Slave Configuration Register 2 */ |
||||
#define AT91_MATRIX_SCFG3 (AT91_MATRIX + 0x4C) /* Slave Configuration Register 3 */ |
||||
#define AT91_MATRIX_SCFG4 (AT91_MATRIX + 0x50) /* Slave Configuration Register 4 */ |
||||
#define AT91_MATRIX_SCFG5 (AT91_MATRIX + 0x54) /* Slave Configuration Register 5 */ |
||||
#define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */ |
||||
#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */ |
||||
#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16) |
||||
#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16) |
||||
#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16) |
||||
#define AT91_MATRIX_FIXED_DEFMSTR (0xf << 18) /* Fixed Index of Default Master */ |
||||
#define AT91_MATRIX_ARBT (3 << 24) /* Arbitration Type */ |
||||
#define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24) |
||||
#define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24) |
||||
|
||||
#define AT91_MATRIX_PRAS0 (AT91_MATRIX + 0x80) /* Priority Register A for Slave 0 */ |
||||
#define AT91_MATRIX_PRAS1 (AT91_MATRIX + 0x88) /* Priority Register A for Slave 1 */ |
||||
#define AT91_MATRIX_PRAS2 (AT91_MATRIX + 0x90) /* Priority Register A for Slave 2 */ |
||||
#define AT91_MATRIX_PRAS3 (AT91_MATRIX + 0x98) /* Priority Register A for Slave 3 */ |
||||
#define AT91_MATRIX_PRAS4 (AT91_MATRIX + 0xA0) /* Priority Register A for Slave 4 */ |
||||
#define AT91_MATRIX_PRAS5 (AT91_MATRIX + 0xA8) /* Priority Register A for Slave 5 */ |
||||
#define AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */ |
||||
#define AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */ |
||||
#define AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */ |
||||
#define AT91_MATRIX_M3PR (3 << 12) /* Master 3 Priority */ |
||||
#define AT91_MATRIX_M4PR (3 << 16) /* Master 4 Priority */ |
||||
#define AT91_MATRIX_M5PR (3 << 20) /* Master 5 Priority */ |
||||
|
||||
#define AT91_MATRIX_MRCR (AT91_MATRIX + 0x100) /* Master Remap Control Register */ |
||||
#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */ |
||||
#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */ |
||||
#define AT91_MATRIX_RCB2 (1 << 2) |
||||
#define AT91_MATRIX_RCB3 (1 << 3) |
||||
#define AT91_MATRIX_RCB4 (1 << 4) |
||||
#define AT91_MATRIX_RCB5 (1 << 5) |
||||
|
||||
#define AT91_MATRIX_TCMR (AT91_MATRIX + 0x114) /* TCM Configuration Register */ |
||||
#define AT91_MATRIX_ITCM_SIZE (0xf << 0) /* Size of ITCM enabled memory block */ |
||||
#define AT91_MATRIX_ITCM_0 (0 << 0) |
||||
#define AT91_MATRIX_ITCM_16 (5 << 0) |
||||
#define AT91_MATRIX_ITCM_32 (6 << 0) |
||||
#define AT91_MATRIX_DTCM_SIZE (0xf << 4) /* Size of DTCM enabled memory block */ |
||||
#define AT91_MATRIX_DTCM_0 (0 << 4) |
||||
#define AT91_MATRIX_DTCM_16 (5 << 4) |
||||
#define AT91_MATRIX_DTCM_32 (6 << 4) |
||||
|
||||
#define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x120) /* EBI0 Chip Select Assignment Register */ |
||||
#define AT91_MATRIX_CS1A (1 << 1) /* Chip Select 1 Assignment */ |
||||
#define AT91_MATRIX_CS1A_SMC (0 << 1) |
||||
#define AT91_MATRIX_CS1A_SDRAMC (1 << 1) |
||||
#define AT91_MATRIX_CS3A (1 << 3) /* Chip Select 3 Assignment */ |
||||
#define AT91_MATRIX_CS3A_SMC (0 << 3) |
||||
#define AT91_MATRIX_CS3A_SMC_SMARTMEDIA (1 << 3) |
||||
#define AT91_MATRIX_CS4A (1 << 4) /* Chip Select 4 Assignment */ |
||||
#define AT91_MATRIX_CS4A_SMC (0 << 4) |
||||
#define AT91_MATRIX_CS4A_SMC_CF1 (1 << 4) |
||||
#define AT91_MATRIX_CS5A (1 << 5) /* Chip Select 5 Assignment */ |
||||
#define AT91_MATRIX_CS5A_SMC (0 << 5) |
||||
#define AT91_MATRIX_CS5A_SMC_CF2 (1 << 5) |
||||
#define AT91_MATRIX_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */ |
||||
#define AT91_MATRIX_VDDIOMSEL (1 << 16) /* Memory voltage selection */ |
||||
#define AT91_MATRIX_VDDIOMSEL_1_8V (0 << 16) |
||||
#define AT91_MATRIX_VDDIOMSEL_3_3V (1 << 16) |
||||
|
||||
|
||||
#endif |
||||
@ -0,0 +1,177 @@ |
||||
/*
|
||||
* Header file for AT91/AT32 LCD Controller |
||||
* |
||||
* Data structure and register user interface |
||||
* |
||||
* Copyright (C) 2007 Atmel Corporation |
||||
* |
||||
* This program is free software; you can redistribute it and/or modify |
||||
* it under the terms of the GNU General Public License as published by |
||||
* the Free Software Foundation; either version 2 of the License, or |
||||
* (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
||||
*/ |
||||
#ifndef __ATMEL_LCDC_H__ |
||||
#define __ATMEL_LCDC_H__ |
||||
|
||||
#define ATMEL_LCDC_DMABADDR1 0x00 |
||||
#define ATMEL_LCDC_DMABADDR2 0x04 |
||||
#define ATMEL_LCDC_DMAFRMPT1 0x08 |
||||
#define ATMEL_LCDC_DMAFRMPT2 0x0c |
||||
#define ATMEL_LCDC_DMAFRMADD1 0x10 |
||||
#define ATMEL_LCDC_DMAFRMADD2 0x14 |
||||
|
||||
#define ATMEL_LCDC_DMAFRMCFG 0x18 |
||||
#define ATMEL_LCDC_FRSIZE (0x7fffff << 0) |
||||
#define ATMEL_LCDC_BLENGTH_OFFSET 24 |
||||
#define ATMEL_LCDC_BLENGTH (0x7f << ATMEL_LCDC_BLENGTH_OFFSET) |
||||
|
||||
#define ATMEL_LCDC_DMACON 0x1c |
||||
#define ATMEL_LCDC_DMAEN (0x1 << 0) |
||||
#define ATMEL_LCDC_DMARST (0x1 << 1) |
||||
#define ATMEL_LCDC_DMABUSY (0x1 << 2) |
||||
#define ATMEL_LCDC_DMAUPDT (0x1 << 3) |
||||
#define ATMEL_LCDC_DMA2DEN (0x1 << 4) |
||||
|
||||
#define ATMEL_LCDC_DMA2DCFG 0x20 |
||||
#define ATMEL_LCDC_ADDRINC_OFFSET 0 |
||||
#define ATMEL_LCDC_ADDRINC (0xffff) |
||||
#define ATMEL_LCDC_PIXELOFF_OFFSET 24 |
||||
#define ATMEL_LCDC_PIXELOFF (0x1f << 24) |
||||
|
||||
#define ATMEL_LCDC_LCDCON1 0x0800 |
||||
#define ATMEL_LCDC_BYPASS (1 << 0) |
||||
#define ATMEL_LCDC_CLKVAL_OFFSET 12 |
||||
#define ATMEL_LCDC_CLKVAL (0x1ff << ATMEL_LCDC_CLKVAL_OFFSET) |
||||
#define ATMEL_LCDC_LINCNT (0x7ff << 21) |
||||
|
||||
#define ATMEL_LCDC_LCDCON2 0x0804 |
||||
#define ATMEL_LCDC_DISTYPE (3 << 0) |
||||
#define ATMEL_LCDC_DISTYPE_STNMONO (0 << 0) |
||||
#define ATMEL_LCDC_DISTYPE_STNCOLOR (1 << 0) |
||||
#define ATMEL_LCDC_DISTYPE_TFT (2 << 0) |
||||
#define ATMEL_LCDC_SCANMOD (1 << 2) |
||||
#define ATMEL_LCDC_SCANMOD_SINGLE (0 << 2) |
||||
#define ATMEL_LCDC_SCANMOD_DUAL (1 << 2) |
||||
#define ATMEL_LCDC_IFWIDTH (3 << 3) |
||||
#define ATMEL_LCDC_IFWIDTH_4 (0 << 3) |
||||
#define ATMEL_LCDC_IFWIDTH_8 (1 << 3) |
||||
#define ATMEL_LCDC_IFWIDTH_16 (2 << 3) |
||||
#define ATMEL_LCDC_PIXELSIZE (7 << 5) |
||||
#define ATMEL_LCDC_PIXELSIZE_1 (0 << 5) |
||||
#define ATMEL_LCDC_PIXELSIZE_2 (1 << 5) |
||||
#define ATMEL_LCDC_PIXELSIZE_4 (2 << 5) |
||||
#define ATMEL_LCDC_PIXELSIZE_8 (3 << 5) |
||||
#define ATMEL_LCDC_PIXELSIZE_16 (4 << 5) |
||||
#define ATMEL_LCDC_PIXELSIZE_24 (5 << 5) |
||||
#define ATMEL_LCDC_PIXELSIZE_32 (6 << 5) |
||||
#define ATMEL_LCDC_INVVD (1 << 8) |
||||
#define ATMEL_LCDC_INVVD_NORMAL (0 << 8) |
||||
#define ATMEL_LCDC_INVVD_INVERTED (1 << 8) |
||||
#define ATMEL_LCDC_INVFRAME (1 << 9 ) |
||||
#define ATMEL_LCDC_INVFRAME_NORMAL (0 << 9) |
||||
#define ATMEL_LCDC_INVFRAME_INVERTED (1 << 9) |
||||
#define ATMEL_LCDC_INVLINE (1 << 10) |
||||
#define ATMEL_LCDC_INVLINE_NORMAL (0 << 10) |
||||
#define ATMEL_LCDC_INVLINE_INVERTED (1 << 10) |
||||
#define ATMEL_LCDC_INVCLK (1 << 11) |
||||
#define ATMEL_LCDC_INVCLK_NORMAL (0 << 11) |
||||
#define ATMEL_LCDC_INVCLK_INVERTED (1 << 11) |
||||
#define ATMEL_LCDC_INVDVAL (1 << 12) |
||||
#define ATMEL_LCDC_INVDVAL_NORMAL (0 << 12) |
||||
#define ATMEL_LCDC_INVDVAL_INVERTED (1 << 12) |
||||
#define ATMEL_LCDC_CLKMOD (1 << 15) |
||||
#define ATMEL_LCDC_CLKMOD_ACTIVEDISPLAY (0 << 15) |
||||
#define ATMEL_LCDC_CLKMOD_ALWAYSACTIVE (1 << 15) |
||||
#define ATMEL_LCDC_MEMOR (1 << 31) |
||||
#define ATMEL_LCDC_MEMOR_BIG (0 << 31) |
||||
#define ATMEL_LCDC_MEMOR_LITTLE (1 << 31) |
||||
|
||||
#define ATMEL_LCDC_TIM1 0x0808 |
||||
#define ATMEL_LCDC_VFP (0xffU << 0) |
||||
#define ATMEL_LCDC_VBP_OFFSET 8 |
||||
#define ATMEL_LCDC_VBP (0xffU << ATMEL_LCDC_VBP_OFFSET) |
||||
#define ATMEL_LCDC_VPW_OFFSET 16 |
||||
#define ATMEL_LCDC_VPW (0x3fU << ATMEL_LCDC_VPW_OFFSET) |
||||
#define ATMEL_LCDC_VHDLY_OFFSET 24 |
||||
#define ATMEL_LCDC_VHDLY (0xfU << ATMEL_LCDC_VHDLY_OFFSET) |
||||
|
||||
#define ATMEL_LCDC_TIM2 0x080c |
||||
#define ATMEL_LCDC_HBP (0xffU << 0) |
||||
#define ATMEL_LCDC_HPW_OFFSET 8 |
||||
#define ATMEL_LCDC_HPW (0x3fU << ATMEL_LCDC_HPW_OFFSET) |
||||
#define ATMEL_LCDC_HFP_OFFSET 21 |
||||
#define ATMEL_LCDC_HFP (0x7ffU << ATMEL_LCDC_HFP_OFFSET) |
||||
|
||||
#define ATMEL_LCDC_LCDFRMCFG 0x0810 |
||||
#define ATMEL_LCDC_LINEVAL (0x7ff << 0) |
||||
#define ATMEL_LCDC_HOZVAL_OFFSET 21 |
||||
#define ATMEL_LCDC_HOZVAL (0x7ff << ATMEL_LCDC_HOZVAL_OFFSET) |
||||
|
||||
#define ATMEL_LCDC_FIFO 0x0814 |
||||
#define ATMEL_LCDC_FIFOTH (0xffff) |
||||
|
||||
#define ATMEL_LCDC_MVAL 0x0818 |
||||
|
||||
#define ATMEL_LCDC_DP1_2 0x081c |
||||
#define ATMEL_LCDC_DP4_7 0x0820 |
||||
#define ATMEL_LCDC_DP3_5 0x0824 |
||||
#define ATMEL_LCDC_DP2_3 0x0828 |
||||
#define ATMEL_LCDC_DP5_7 0x082c |
||||
#define ATMEL_LCDC_DP3_4 0x0830 |
||||
#define ATMEL_LCDC_DP4_5 0x0834 |
||||
#define ATMEL_LCDC_DP6_7 0x0838 |
||||
#define ATMEL_LCDC_DP1_2_VAL (0xff) |
||||
#define ATMEL_LCDC_DP4_7_VAL (0xfffffff) |
||||
#define ATMEL_LCDC_DP3_5_VAL (0xfffff) |
||||
#define ATMEL_LCDC_DP2_3_VAL (0xfff) |
||||
#define ATMEL_LCDC_DP5_7_VAL (0xfffffff) |
||||
#define ATMEL_LCDC_DP3_4_VAL (0xffff) |
||||
#define ATMEL_LCDC_DP4_5_VAL (0xfffff) |
||||
#define ATMEL_LCDC_DP6_7_VAL (0xfffffff) |
||||
|
||||
#define ATMEL_LCDC_PWRCON 0x083c |
||||
#define ATMEL_LCDC_PWR (1 << 0) |
||||
#define ATMEL_LCDC_GUARDT_OFFSET 1 |
||||
#define ATMEL_LCDC_GUARDT (0x7f << ATMEL_LCDC_GUARDT_OFFSET) |
||||
#define ATMEL_LCDC_BUSY (1 << 31) |
||||
|
||||
#define ATMEL_LCDC_CONTRAST_CTR 0x0840 |
||||
#define ATMEL_LCDC_PS (3 << 0) |
||||
#define ATMEL_LCDC_PS_DIV1 (0 << 0) |
||||
#define ATMEL_LCDC_PS_DIV2 (1 << 0) |
||||
#define ATMEL_LCDC_PS_DIV4 (2 << 0) |
||||
#define ATMEL_LCDC_PS_DIV8 (3 << 0) |
||||
#define ATMEL_LCDC_POL (1 << 2) |
||||
#define ATMEL_LCDC_POL_NEGATIVE (0 << 2) |
||||
#define ATMEL_LCDC_POL_POSITIVE (1 << 2) |
||||
#define ATMEL_LCDC_ENA (1 << 3) |
||||
#define ATMEL_LCDC_ENA_PWMDISABLE (0 << 3) |
||||
#define ATMEL_LCDC_ENA_PWMENABLE (1 << 3) |
||||
|
||||
#define ATMEL_LCDC_CONTRAST_VAL 0x0844 |
||||
#define ATMEL_LCDC_CVAL (0xff) |
||||
|
||||
#define ATMEL_LCDC_IER 0x0848 |
||||
#define ATMEL_LCDC_IDR 0x084c |
||||
#define ATMEL_LCDC_IMR 0x0850 |
||||
#define ATMEL_LCDC_ISR 0x0854 |
||||
#define ATMEL_LCDC_ICR 0x0858 |
||||
#define ATMEL_LCDC_LNI (1 << 0) |
||||
#define ATMEL_LCDC_LSTLNI (1 << 1) |
||||
#define ATMEL_LCDC_EOFI (1 << 2) |
||||
#define ATMEL_LCDC_UFLWI (1 << 4) |
||||
#define ATMEL_LCDC_OWRI (1 << 5) |
||||
#define ATMEL_LCDC_MERI (1 << 6) |
||||
|
||||
#define ATMEL_LCDC_LUT(n) (0x0c00 + ((n)*4)) |
||||
|
||||
#endif /* __ATMEL_LCDC_H__ */ |
||||
@ -0,0 +1,202 @@ |
||||
/*
|
||||
* (C) Copyright 2007-2008 |
||||
* Stelian Pop <stelian.pop@leadtechdesign.com> |
||||
* Lead Tech Design <www.leadtechdesign.com> |
||||
* |
||||
* Configuation settings for the AT91SAM9261EK board. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#ifndef __CONFIG_H |
||||
#define __CONFIG_H |
||||
|
||||
/* ARM asynchronous clock */ |
||||
#define AT91_CPU_NAME "AT91SAM9261" |
||||
#define AT91_MAIN_CLOCK 198656000 /* from 18.432 MHz crystal */ |
||||
#define AT91_MASTER_CLOCK 99328000 /* peripheral = main / 2 */ |
||||
#define CFG_HZ 1000000 /* 1us resolution */ |
||||
|
||||
#define AT91_SLOW_CLOCK 32768 /* slow clock */ |
||||
|
||||
#define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */ |
||||
#define CONFIG_AT91SAM9261 1 /* It's an Atmel AT91SAM9261 SoC*/ |
||||
#define CONFIG_AT91SAM9261EK 1 /* on an AT91SAM9261EK Board */ |
||||
#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ |
||||
|
||||
#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ |
||||
#define CONFIG_SETUP_MEMORY_TAGS 1 |
||||
#define CONFIG_INITRD_TAG 1 |
||||
|
||||
#define CONFIG_SKIP_LOWLEVEL_INIT |
||||
#define CONFIG_SKIP_RELOCATE_UBOOT |
||||
|
||||
/*
|
||||
* Hardware drivers |
||||
*/ |
||||
#define CONFIG_ATMEL_USART 1 |
||||
#undef CONFIG_USART0 |
||||
#undef CONFIG_USART1 |
||||
#undef CONFIG_USART2 |
||||
#define CONFIG_USART3 1 /* USART 3 is DBGU */ |
||||
|
||||
/* LCD */ |
||||
#define CONFIG_LCD 1 |
||||
#define LCD_BPP LCD_COLOR8 |
||||
#define CONFIG_LCD_LOGO 1 |
||||
#undef LCD_TEST_PATTERN |
||||
#define CONFIG_LCD_INFO 1 |
||||
#define CONFIG_LCD_INFO_BELOW_LOGO 1 |
||||
#define CFG_WHITE_ON_BLACK 1 |
||||
#define CONFIG_ATMEL_LCD 1 |
||||
#define CONFIG_ATMEL_LCD_BGR555 1 |
||||
#define CFG_CONSOLE_IS_IN_ENV 1 |
||||
|
||||
#define CONFIG_BOOTDELAY 3 |
||||
|
||||
/*
|
||||
* BOOTP options |
||||
*/ |
||||
#define CONFIG_BOOTP_BOOTFILESIZE 1 |
||||
#define CONFIG_BOOTP_BOOTPATH 1 |
||||
#define CONFIG_BOOTP_GATEWAY 1 |
||||
#define CONFIG_BOOTP_HOSTNAME 1 |
||||
|
||||
/*
|
||||
* Command line configuration. |
||||
*/ |
||||
#include <config_cmd_default.h> |
||||
#undef CONFIG_CMD_BDI |
||||
#undef CONFIG_CMD_IMI |
||||
#undef CONFIG_CMD_AUTOSCRIPT |
||||
#undef CONFIG_CMD_FPGA |
||||
#undef CONFIG_CMD_LOADS |
||||
#undef CONFIG_CMD_IMLS |
||||
|
||||
#define CONFIG_CMD_PING 1 |
||||
#define CONFIG_CMD_DHCP 1 |
||||
#define CONFIG_CMD_NAND 1 |
||||
#define CONFIG_CMD_USB 1 |
||||
|
||||
/* SDRAM */ |
||||
#define CONFIG_NR_DRAM_BANKS 1 |
||||
#define PHYS_SDRAM 0x20000000 |
||||
#define PHYS_SDRAM_SIZE 0x04000000 /* 64 megs */ |
||||
|
||||
/* DataFlash */ |
||||
#define CONFIG_HAS_DATAFLASH 1 |
||||
#define CFG_SPI_WRITE_TOUT (5*CFG_HZ) |
||||
#define CFG_MAX_DATAFLASH_BANKS 2 |
||||
#define CFG_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* CS0 */ |
||||
#define CFG_DATAFLASH_LOGIC_ADDR_CS3 0xD0000000 /* CS3 */ |
||||
#define AT91_SPI_CLK 15000000 |
||||
#define DATAFLASH_TCSS (0x1a << 16) |
||||
#define DATAFLASH_TCHS (0x1 << 24) |
||||
|
||||
/* NAND flash */ |
||||
#define NAND_MAX_CHIPS 1 |
||||
#define CFG_MAX_NAND_DEVICE 1 |
||||
#define CFG_NAND_BASE 0x40000000 |
||||
#define CFG_NAND_DBW_8 1 |
||||
|
||||
/* NOR flash - no real flash on this board */ |
||||
#define CFG_NO_FLASH 1 |
||||
|
||||
/* Ethernet */ |
||||
#define CONFIG_DRIVER_DM9000 1 |
||||
#define CONFIG_DM9000_BASE 0x30000000 |
||||
#define DM9000_IO CONFIG_DM9000_BASE |
||||
#define DM9000_DATA (CONFIG_DM9000_BASE + 4) |
||||
#define CONFIG_DM9000_USE_16BIT 1 |
||||
#define CONFIG_NET_RETRY_COUNT 20 |
||||
#define CONFIG_RESET_PHY_R 1 |
||||
|
||||
/* USB */ |
||||
#define CONFIG_USB_OHCI_NEW 1 |
||||
#define LITTLEENDIAN 1 |
||||
#define CONFIG_DOS_PARTITION 1 |
||||
#define CFG_USB_OHCI_CPU_INIT 1 |
||||
#define CFG_USB_OHCI_REGS_BASE 0x00500000 /* AT91SAM9261_UHP_BASE */ |
||||
#define CFG_USB_OHCI_SLOT_NAME "at91sam9261" |
||||
#define CFG_USB_OHCI_MAX_ROOT_PORTS 2 |
||||
#define CONFIG_USB_STORAGE 1 |
||||
|
||||
#define CFG_LOAD_ADDR 0x22000000 /* load address */ |
||||
|
||||
#define CFG_MEMTEST_START PHYS_SDRAM |
||||
#define CFG_MEMTEST_END 0x23e00000 |
||||
|
||||
#define CFG_USE_DATAFLASH_CS0 1 |
||||
#undef CFG_USE_NANDFLASH |
||||
|
||||
#ifdef CFG_USE_DATAFLASH_CS0 |
||||
|
||||
/* bootstrap + u-boot + env + linux in dataflash on CS0 */ |
||||
#define CFG_ENV_IS_IN_DATAFLASH 1 |
||||
#define CFG_MONITOR_BASE (CFG_DATAFLASH_LOGIC_ADDR_CS0 + 0x8400) |
||||
#define CFG_ENV_OFFSET 0x4200 |
||||
#define CFG_ENV_ADDR (CFG_DATAFLASH_LOGIC_ADDR_CS0 + CFG_ENV_OFFSET) |
||||
#define CFG_ENV_SIZE 0x4200 |
||||
#define CONFIG_BOOTCOMMAND "cp.b 0xC0042000 0x22000000 0x210000; bootm" |
||||
#define CONFIG_BOOTARGS "console=ttyS0,115200 " \ |
||||
"root=/dev/mtdblock0 " \
|
||||
"mtdparts=at91_nand:-(root) " \
|
||||
"rw rootfstype=jffs2" |
||||
|
||||
#else /* CFG_USE_NANDFLASH */ |
||||
|
||||
/* bootstrap + u-boot + env + linux in nandflash */ |
||||
#define CFG_ENV_IS_IN_NAND 1 |
||||
#define CFG_ENV_OFFSET 0x60000 |
||||
#define CFG_ENV_OFFSET_REDUND 0x80000 |
||||
#define CFG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */ |
||||
#define CONFIG_BOOTCOMMAND "nand read 0x22000000 0xA0000 0x200000; bootm" |
||||
#define CONFIG_BOOTARGS "console=ttyS0,115200 " \ |
||||
"root=/dev/mtdblock5 " \
|
||||
"mtdparts=at91_nand:128k(bootstrap)ro," \
|
||||
"256k(uboot)ro,128k(env1)ro," \
|
||||
"128k(env2)ro,2M(linux),-(root) " \
|
||||
"rw rootfstype=jffs2" |
||||
|
||||
#endif |
||||
|
||||
#define CONFIG_BAUDRATE 115200 |
||||
#define CFG_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 } |
||||
|
||||
#define CFG_PROMPT "U-Boot> " |
||||
#define CFG_CBSIZE 256 |
||||
#define CFG_MAXARGS 16 |
||||
#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) |
||||
#define CFG_LONGHELP 1 |
||||
#define CONFIG_CMDLINE_EDITING 1 |
||||
|
||||
#define ROUND(A, B) (((A) + (B)) & ~((B) - 1)) |
||||
/*
|
||||
* Size of malloc() pool |
||||
*/ |
||||
#define CFG_MALLOC_LEN ROUND(3 * CFG_ENV_SIZE + 128*1024, 0x1000) |
||||
#define CFG_GBL_DATA_SIZE 128 /* 128 bytes for initial data */ |
||||
|
||||
#define CONFIG_STACKSIZE (32*1024) /* regular stack */ |
||||
|
||||
#ifdef CONFIG_USE_IRQ |
||||
#error CONFIG_USE_IRQ not supported |
||||
#endif |
||||
|
||||
#endif |
||||
@ -0,0 +1,206 @@ |
||||
/*
|
||||
* (C) Copyright 2007-2008 |
||||
* Stelian Pop <stelian.pop@leadtechdesign.com> |
||||
* Lead Tech Design <www.leadtechdesign.com> |
||||
* |
||||
* Configuation settings for the AT91SAM9263EK board. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#ifndef __CONFIG_H |
||||
#define __CONFIG_H |
||||
|
||||
/* ARM asynchronous clock */ |
||||
#define AT91_CPU_NAME "AT91SAM9263" |
||||
#define AT91_MAIN_CLOCK 199919000 /* from 16.367 MHz crystal */ |
||||
#define AT91_MASTER_CLOCK 99959500 /* peripheral = main / 2 */ |
||||
#define CFG_HZ 1000000 /* 1us resolution */ |
||||
|
||||
#define AT91_SLOW_CLOCK 32768 /* slow clock */ |
||||
|
||||
#define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */ |
||||
#define CONFIG_AT91SAM9263 1 /* It's an Atmel AT91SAM9263 SoC*/ |
||||
#define CONFIG_AT91SAM9263EK 1 /* on an AT91SAM9263EK Board */ |
||||
#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ |
||||
|
||||
#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ |
||||
#define CONFIG_SETUP_MEMORY_TAGS 1 |
||||
#define CONFIG_INITRD_TAG 1 |
||||
|
||||
#define CONFIG_SKIP_LOWLEVEL_INIT |
||||
#define CONFIG_SKIP_RELOCATE_UBOOT |
||||
|
||||
/*
|
||||
* Hardware drivers |
||||
*/ |
||||
#define CONFIG_ATMEL_USART 1 |
||||
#undef CONFIG_USART0 |
||||
#undef CONFIG_USART1 |
||||
#undef CONFIG_USART2 |
||||
#define CONFIG_USART3 1 /* USART 3 is DBGU */ |
||||
|
||||
/* LCD */ |
||||
#define CONFIG_LCD 1 |
||||
#define LCD_BPP LCD_COLOR8 |
||||
#define CONFIG_LCD_LOGO 1 |
||||
#undef LCD_TEST_PATTERN |
||||
#define CONFIG_LCD_INFO 1 |
||||
#define CONFIG_LCD_INFO_BELOW_LOGO 1 |
||||
#define CFG_WHITE_ON_BLACK 1 |
||||
#define CONFIG_ATMEL_LCD 1 |
||||
#define CONFIG_ATMEL_LCD_BGR555 1 |
||||
#define CFG_CONSOLE_IS_IN_ENV 1 |
||||
|
||||
#define CONFIG_BOOTDELAY 3 |
||||
|
||||
/*
|
||||
* BOOTP options |
||||
*/ |
||||
#define CONFIG_BOOTP_BOOTFILESIZE 1 |
||||
#define CONFIG_BOOTP_BOOTPATH 1 |
||||
#define CONFIG_BOOTP_GATEWAY 1 |
||||
#define CONFIG_BOOTP_HOSTNAME 1 |
||||
|
||||
/*
|
||||
* Command line configuration. |
||||
*/ |
||||
#include <config_cmd_default.h> |
||||
#undef CONFIG_CMD_BDI |
||||
#undef CONFIG_CMD_IMI |
||||
#undef CONFIG_CMD_AUTOSCRIPT |
||||
#undef CONFIG_CMD_FPGA |
||||
#undef CONFIG_CMD_LOADS |
||||
#undef CONFIG_CMD_IMLS |
||||
|
||||
#define CONFIG_CMD_PING 1 |
||||
#define CONFIG_CMD_DHCP 1 |
||||
#define CONFIG_CMD_NAND 1 |
||||
#define CONFIG_CMD_USB 1 |
||||
|
||||
/* SDRAM */ |
||||
#define CONFIG_NR_DRAM_BANKS 1 |
||||
#define PHYS_SDRAM 0x20000000 |
||||
#define PHYS_SDRAM_SIZE 0x04000000 /* 64 megs */ |
||||
|
||||
/* DataFlash */ |
||||
#define CONFIG_HAS_DATAFLASH 1 |
||||
#define CFG_SPI_WRITE_TOUT (5*CFG_HZ) |
||||
#define CFG_MAX_DATAFLASH_BANKS 1 |
||||
#define CFG_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* CS0 */ |
||||
#define AT91_SPI_CLK 15000000 |
||||
#define DATAFLASH_TCSS (0x1a << 16) |
||||
#define DATAFLASH_TCHS (0x1 << 24) |
||||
|
||||
/* NOR flash, if populated */ |
||||
#if 1 |
||||
#define CFG_NO_FLASH 1 |
||||
#else |
||||
#define CFG_FLASH_CFI 1 |
||||
#define CFG_FLASH_CFI_DRIVER 1 |
||||
#define PHYS_FLASH_1 0x10000000 |
||||
#define CFG_FLASH_BASE PHYS_FLASH_1 |
||||
#define CFG_MAX_FLASH_SECT 256 |
||||
#define CFG_MAX_FLASH_BANKS 1 |
||||
#endif |
||||
|
||||
/* NAND flash */ |
||||
#define NAND_MAX_CHIPS 1 |
||||
#define CFG_MAX_NAND_DEVICE 1 |
||||
#define CFG_NAND_BASE 0x40000000 |
||||
#define CFG_NAND_DBW_8 1 |
||||
|
||||
/* Ethernet */ |
||||
#define CONFIG_MACB 1 |
||||
#define CONFIG_RMII 1 |
||||
#define CONFIG_NET_MULTI 1 |
||||
#define CONFIG_NET_RETRY_COUNT 20 |
||||
#define CONFIG_RESET_PHY_R 1 |
||||
|
||||
/* USB */ |
||||
#define CONFIG_USB_OHCI_NEW 1 |
||||
#define LITTLEENDIAN 1 |
||||
#define CONFIG_DOS_PARTITION 1 |
||||
#define CFG_USB_OHCI_CPU_INIT 1 |
||||
#define CFG_USB_OHCI_REGS_BASE 0x00a00000 /* AT91SAM9263_UHP_BASE */ |
||||
#define CFG_USB_OHCI_SLOT_NAME "at91sam9263" |
||||
#define CFG_USB_OHCI_MAX_ROOT_PORTS 2 |
||||
#define CONFIG_USB_STORAGE 1 |
||||
|
||||
#define CFG_LOAD_ADDR 0x22000000 /* load address */ |
||||
|
||||
#define CFG_MEMTEST_START PHYS_SDRAM |
||||
#define CFG_MEMTEST_END 0x23e00000 |
||||
|
||||
#define CFG_USE_DATAFLASH 1 |
||||
#undef CFG_USE_NANDFLASH |
||||
|
||||
#ifdef CFG_USE_DATAFLASH |
||||
|
||||
/* bootstrap + u-boot + env + linux in dataflash on CS0 */ |
||||
#define CFG_ENV_IS_IN_DATAFLASH 1 |
||||
#define CFG_MONITOR_BASE (CFG_DATAFLASH_LOGIC_ADDR_CS0 + 0x8400) |
||||
#define CFG_ENV_OFFSET 0x4200 |
||||
#define CFG_ENV_ADDR (CFG_DATAFLASH_LOGIC_ADDR_CS0 + CFG_ENV_OFFSET) |
||||
#define CFG_ENV_SIZE 0x4200 |
||||
#define CONFIG_BOOTCOMMAND "cp.b 0xC0042000 0x22000000 0x210000; bootm" |
||||
#define CONFIG_BOOTARGS "console=ttyS0,115200 " \ |
||||
"root=/dev/mtdblock0 " \
|
||||
"mtdparts=at91_nand:-(root) "\
|
||||
"rw rootfstype=jffs2" |
||||
|
||||
#else /* CFG_USE_NANDFLASH */ |
||||
|
||||
/* bootstrap + u-boot + env + linux in nandflash */ |
||||
#define CFG_ENV_IS_IN_NAND 1 |
||||
#define CFG_ENV_OFFSET 0x60000 |
||||
#define CFG_ENV_OFFSET_REDUND 0x80000 |
||||
#define CFG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */ |
||||
#define CONFIG_BOOTCOMMAND "nand read 0x22000000 0xA0000 0x200000; bootm" |
||||
#define CONFIG_BOOTARGS "console=ttyS0,115200 " \ |
||||
"root=/dev/mtdblock5 " \
|
||||
"mtdparts=at91_nand:128k(bootstrap)ro,256k(uboot)ro,128k(env1)ro,128k(env2)ro,2M(linux),-(root) " \
|
||||
"rw rootfstype=jffs2" |
||||
|
||||
#endif |
||||
|
||||
#define CONFIG_BAUDRATE 115200 |
||||
#define CFG_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 } |
||||
|
||||
#define CFG_PROMPT "U-Boot> " |
||||
#define CFG_CBSIZE 256 |
||||
#define CFG_MAXARGS 16 |
||||
#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) |
||||
#define CFG_LONGHELP 1 |
||||
#define CONFIG_CMDLINE_EDITING 1 |
||||
|
||||
#define ROUND(A, B) (((A) + (B)) & ~((B) - 1)) |
||||
/*
|
||||
* Size of malloc() pool |
||||
*/ |
||||
#define CFG_MALLOC_LEN ROUND(3 * CFG_ENV_SIZE + 128*1024, 0x1000) |
||||
#define CFG_GBL_DATA_SIZE 128 /* 128 bytes for initial data */ |
||||
|
||||
#define CONFIG_STACKSIZE (32*1024) /* regular stack */ |
||||
|
||||
#ifdef CONFIG_USE_IRQ |
||||
#error CONFIG_USE_IRQ not supported |
||||
#endif |
||||
|
||||
#endif |
||||
@ -0,0 +1,175 @@ |
||||
/*
|
||||
* (C) Copyright 2007-2008 |
||||
* Stelian Pop <stelian.pop@leadtechdesign.com> |
||||
* Lead Tech Design <www.leadtechdesign.com> |
||||
* |
||||
* Configuation settings for the AT91SAM9RLEK board. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#ifndef __CONFIG_H |
||||
#define __CONFIG_H |
||||
|
||||
/* ARM asynchronous clock */ |
||||
#define AT91_CPU_NAME "AT91SAM9RL" |
||||
#define AT91_MAIN_CLOCK 200000000 /* from 12.000 MHz crystal */ |
||||
#define AT91_MASTER_CLOCK 100000000 /* peripheral = main / 2 */ |
||||
#define CFG_HZ 1000000 /* 1us resolution */ |
||||
|
||||
#define AT91_SLOW_CLOCK 32768 /* slow clock */ |
||||
|
||||
#define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */ |
||||
#define CONFIG_AT91SAM9RL 1 /* It's an Atmel AT91SAM9RL SoC*/ |
||||
#define CONFIG_AT91SAM9RLEK 1 /* on an AT91SAM9RLEK Board */ |
||||
#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ |
||||
|
||||
#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ |
||||
#define CONFIG_SETUP_MEMORY_TAGS 1 |
||||
#define CONFIG_INITRD_TAG 1 |
||||
|
||||
#define CONFIG_SKIP_LOWLEVEL_INIT |
||||
#define CONFIG_SKIP_RELOCATE_UBOOT |
||||
|
||||
/*
|
||||
* Hardware drivers |
||||
*/ |
||||
#define CONFIG_ATMEL_USART 1 |
||||
#undef CONFIG_USART0 |
||||
#undef CONFIG_USART1 |
||||
#undef CONFIG_USART2 |
||||
#define CONFIG_USART3 1 /* USART 3 is DBGU */ |
||||
|
||||
/* LCD */ |
||||
#define CONFIG_LCD 1 |
||||
#define LCD_BPP LCD_COLOR8 |
||||
#define CONFIG_LCD_LOGO 1 |
||||
#undef LCD_TEST_PATTERN |
||||
#define CONFIG_LCD_INFO 1 |
||||
#define CONFIG_LCD_INFO_BELOW_LOGO 1 |
||||
#define CFG_WHITE_ON_BLACK 1 |
||||
#define CONFIG_ATMEL_LCD 1 |
||||
#define CONFIG_ATMEL_LCD_RGB565 1 |
||||
#define CFG_CONSOLE_IS_IN_ENV 1 |
||||
|
||||
#define CONFIG_BOOTDELAY 3 |
||||
|
||||
/*
|
||||
* Command line configuration. |
||||
*/ |
||||
#include <config_cmd_default.h> |
||||
#undef CONFIG_CMD_BDI |
||||
#undef CONFIG_CMD_IMI |
||||
#undef CONFIG_CMD_AUTOSCRIPT |
||||
#undef CONFIG_CMD_FPGA |
||||
#undef CONFIG_CMD_LOADS |
||||
#undef CONFIG_CMD_IMLS |
||||
#undef CONFIG_CMD_NET |
||||
#undef CONFIG_CMD_USB |
||||
|
||||
#define CONFIG_CMD_NAND 1 |
||||
|
||||
/* SDRAM */ |
||||
#define CONFIG_NR_DRAM_BANKS 1 |
||||
#define PHYS_SDRAM 0x20000000 |
||||
#define PHYS_SDRAM_SIZE 0x04000000 /* 64 megs */ |
||||
|
||||
/* DataFlash */ |
||||
#define CONFIG_HAS_DATAFLASH 1 |
||||
#define CFG_SPI_WRITE_TOUT (5*CFG_HZ) |
||||
#define CFG_MAX_DATAFLASH_BANKS 1 |
||||
#define CFG_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* CS0 */ |
||||
#define AT91_SPI_CLK 15000000 |
||||
#define DATAFLASH_TCSS (0x1a << 16) |
||||
#define DATAFLASH_TCHS (0x1 << 24) |
||||
|
||||
/* NOR flash - not present */ |
||||
#define CFG_NO_FLASH 1 |
||||
|
||||
/* NAND flash */ |
||||
#define NAND_MAX_CHIPS 1 |
||||
#define CFG_MAX_NAND_DEVICE 1 |
||||
#define CFG_NAND_BASE 0x40000000 |
||||
#define CFG_NAND_DBW_8 1 |
||||
|
||||
/* Ethernet - not present */ |
||||
|
||||
/* USB - not supported */ |
||||
|
||||
#define CFG_LOAD_ADDR 0x22000000 /* load address */ |
||||
|
||||
#define CFG_MEMTEST_START PHYS_SDRAM |
||||
#define CFG_MEMTEST_END 0x23e00000 |
||||
|
||||
#define CFG_USE_DATAFLASH 1 |
||||
#undef CFG_USE_NANDFLASH |
||||
|
||||
#ifdef CFG_USE_DATAFLASH |
||||
|
||||
/* bootstrap + u-boot + env + linux in dataflash on CS0 */ |
||||
#define CFG_ENV_IS_IN_DATAFLASH 1 |
||||
#define CFG_MONITOR_BASE (CFG_DATAFLASH_LOGIC_ADDR_CS0 + 0x8400) |
||||
#define CFG_ENV_OFFSET 0x4200 |
||||
#define CFG_ENV_ADDR (CFG_DATAFLASH_LOGIC_ADDR_CS0 + CFG_ENV_OFFSET) |
||||
#define CFG_ENV_SIZE 0x4200 |
||||
#define CONFIG_BOOTCOMMAND "cp.b 0xC0042000 0x22000000 0x210000; bootm" |
||||
#define CONFIG_BOOTARGS "console=ttyS0,115200 " \ |
||||
"root=/dev/mtdblock0 " \
|
||||
"mtdparts=at91_nand:-(root) "\
|
||||
"rw rootfstype=jffs2" |
||||
|
||||
#else /* CFG_USE_NANDFLASH */ |
||||
|
||||
/* bootstrap + u-boot + env + linux in nandflash */ |
||||
#define CFG_ENV_IS_IN_NAND 1 |
||||
#define CFG_ENV_OFFSET 0x60000 |
||||
#define CFG_ENV_OFFSET_REDUND 0x80000 |
||||
#define CFG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */ |
||||
#define CONFIG_BOOTCOMMAND "nand read 0x22000000 0xA0000 0x200000; bootm" |
||||
#define CONFIG_BOOTARGS "console=ttyS0,115200 " \ |
||||
"root=/dev/mtdblock5 " \
|
||||
"mtdparts=at91_nand:128k(bootstrap)ro,256k(uboot)ro,128k(env1)ro,128k(env2)ro,2M(linux),-(root) " \
|
||||
"rw rootfstype=jffs2" |
||||
|
||||
#endif |
||||
|
||||
#define CONFIG_BAUDRATE 115200 |
||||
#define CFG_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 } |
||||
|
||||
#define CFG_PROMPT "U-Boot> " |
||||
#define CFG_CBSIZE 256 |
||||
#define CFG_MAXARGS 16 |
||||
#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) |
||||
#define CFG_LONGHELP 1 |
||||
#define CONFIG_CMDLINE_EDITING 1 |
||||
|
||||
#define ROUND(A, B) (((A) + (B)) & ~((B) - 1)) |
||||
/*
|
||||
* Size of malloc() pool |
||||
*/ |
||||
#define CFG_MALLOC_LEN ROUND(3 * CFG_ENV_SIZE + 128*1024, 0x1000) |
||||
#define CFG_GBL_DATA_SIZE 128 /* 128 bytes for initial data */ |
||||
|
||||
#define CONFIG_STACKSIZE (32*1024) /* regular stack */ |
||||
|
||||
#ifdef CONFIG_USE_IRQ |
||||
#error CONFIG_USE_IRQ not supported |
||||
#endif |
||||
|
||||
#endif |
||||
|
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Reference in new issue