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ppc4xx: Convert PPC4xx UIC defines from lower case to upper case

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The latest PPC4xx register cleanup patch missed the UIC defines.
This patch now changes lower case UIC defines to upper case.

Signed-off-by: Stefan Roese <sr@denx.de>
master
Stefan Roese 15 years ago
parent 984f10baac
commit 952e7760bf
72 changed files with 1017 additions and 1029 deletions
Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL
Show Stats Download Patch File Download Diff File
  1. 12
      board/amcc/acadia/acadia.c
  2. 30
      board/amcc/bamboo/bamboo.c
  3. 12
      board/amcc/bubinga/bubinga.c
  4. 62
      board/amcc/canyonlands/canyonlands.c
  5. 28
      board/amcc/ebony/ebony.c
  6. 72
      board/amcc/katmai/katmai.c
  7. 52
      board/amcc/kilauea/kilauea.c
  8. 34
      board/amcc/luan/luan.c
  9. 48
      board/amcc/makalu/makalu.c
  10. 60
      board/amcc/ocotea/ocotea.c
  11. 60
      board/amcc/redwood/redwood.c
  12. 46
      board/amcc/sequoia/sequoia.c
  13. 14
      board/amcc/taihu/taihu.c
  14. 60
      board/amcc/taishan/taishan.c
  15. 14
      board/amcc/walnut/walnut.c
  16. 30
      board/amcc/yosemite/yosemite.c
  17. 64
      board/amcc/yucca/yucca.c
  18. 14
      board/cray/L1/L1.c
  19. 14
      board/csb272/csb272.c
  20. 14
      board/csb472/csb472.c
  21. 14
      board/dave/PPChameleonEVB/PPChameleonEVB.c
  22. 14
      board/eric/eric.c
  23. 14
      board/esd/apc405/apc405.c
  24. 14
      board/esd/ar405/ar405.c
  25. 14
      board/esd/ash405/ash405.c
  26. 14
      board/esd/canbt/canbt.c
  27. 14
      board/esd/cms700/cms700.c
  28. 16
      board/esd/cpci2dp/cpci2dp.c
  29. 18
      board/esd/cpci405/cpci405.c
  30. 16
      board/esd/cpciiser4/cpciiser4.c
  31. 14
      board/esd/dp405/dp405.c
  32. 14
      board/esd/du405/du405.c
  33. 42
      board/esd/du440/du440.c
  34. 14
      board/esd/hh405/hh405.c
  35. 14
      board/esd/hub405/hub405.c
  36. 14
      board/esd/ocrtc/ocrtc.c
  37. 16
      board/esd/pci405/pci405.c
  38. 14
      board/esd/plu405/plu405.c
  39. 14
      board/esd/pmc405/pmc405.c
  40. 14
      board/esd/pmc405de/pmc405de.c
  41. 46
      board/esd/pmc440/pmc440.c
  42. 14
      board/esd/voh405/voh405.c
  43. 14
      board/esd/vom405/vom405.c
  44. 14
      board/esd/wuh405/wuh405.c
  45. 14
      board/exbitgen/exbitgen.c
  46. 26
      board/g2000/g2000.c
  47. 14
      board/gdsys/dlvision/dlvision.c
  48. 30
      board/gdsys/gdppc440etx/gdppc440etx.c
  49. 62
      board/gdsys/intip/intip.c
  50. 14
      board/gdsys/neo/neo.c
  51. 12
      board/jse/jse.c
  52. 46
      board/korat/korat.c
  53. 46
      board/lwmon5/lwmon5.c
  54. 14
      board/mpl/mip405/mip405.c
  55. 14
      board/mpl/pip405/pip405.c
  56. 12
      board/netstal/hcu4/hcu4.c
  57. 46
      board/netstal/hcu5/hcu5.c
  58. 12
      board/netstal/mcu25/mcu25.c
  59. 30
      board/pcs440ep/pcs440ep.c
  60. 60
      board/prodrive/alpr/alpr.c
  61. 30
      board/prodrive/p3p440/p3p440.c
  62. 14
      board/quad100hd/quad100hd.c
  63. 60
      board/sandburst/karef/karef.c
  64. 60
      board/sandburst/metrobox/metrobox.c
  65. 14
      board/sbc405/sbc405.c
  66. 18
      board/sc3/sc3.c
  67. 28
      board/w7o/w7o.c
  68. 60
      board/xes/xpedite1000/xpedite1000.c
  69. 14
      board/zeus/zeus.c
  70. 36
      common/cmd_reginfo.c
  71. 28
      cpu/ppc4xx/uic.c
  72. 86
      include/asm-ppc/ppc4xx-uic.h

12
board/amcc/acadia/acadia.c
Unescape View File

@ -78,12 +78,12 @@ int board_early_init_f(void)
mfsdr(SDR0_ULTRA1, reg);
mtsdr(SDR0_ULTRA1, reg | SDR_ULTRA1_LEDNENABLE);
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr(uicer, 0x00000000); /* disable all ints */
mtdcr(uiccr, 0x00000010);
mtdcr(uicpr, 0xFE7FFFF0); /* set int polarities */
mtdcr(uictr, 0x00000010); /* set int trigger levels */
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
mtdcr(UIC0ER, 0x00000000); /* disable all ints */
mtdcr(UIC0CR, 0x00000010);
mtdcr(UIC0PR, 0xFE7FFFF0); /* set int polarities */
mtdcr(UIC0TR, 0x00000010); /* set int trigger levels */
mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
return 0;
}

30
board/amcc/bamboo/bamboo.c
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@ -392,21 +392,21 @@ int board_early_init_f(void)
/*--------------------------------------------------------------------
* Setup the interrupt controller polarities, triggers, etc.
*-------------------------------------------------------------------*/
mtdcr(uic0sr, 0xffffffff); /* clear all */
mtdcr(uic0er, 0x00000000); /* disable all */
mtdcr(uic0cr, 0x00000009); /* ATI & UIC1 crit are critical */
mtdcr(uic0pr, 0xfffffe13); /* per ref-board manual */
mtdcr(uic0tr, 0x01c00008); /* per ref-board manual */
mtdcr(uic0vr, 0x00000001); /* int31 highest, base=0x000 */
mtdcr(uic0sr, 0xffffffff); /* clear all */
mtdcr(uic1sr, 0xffffffff); /* clear all */
mtdcr(uic1er, 0x00000000); /* disable all */
mtdcr(uic1cr, 0x00000000); /* all non-critical */
mtdcr(uic1pr, 0xffffe0ff); /* per ref-board manual */
mtdcr(uic1tr, 0x00ffc000); /* per ref-board manual */
mtdcr(uic1vr, 0x00000001); /* int31 highest, base=0x000 */
mtdcr(uic1sr, 0xffffffff); /* clear all */
mtdcr(UIC0SR, 0xffffffff); /* clear all */
mtdcr(UIC0ER, 0x00000000); /* disable all */
mtdcr(UIC0CR, 0x00000009); /* ATI & UIC1 crit are critical */
mtdcr(UIC0PR, 0xfffffe13); /* per ref-board manual */
mtdcr(UIC0TR, 0x01c00008); /* per ref-board manual */
mtdcr(UIC0VR, 0x00000001); /* int31 highest, base=0x000 */
mtdcr(UIC0SR, 0xffffffff); /* clear all */
mtdcr(UIC1SR, 0xffffffff); /* clear all */
mtdcr(UIC1ER, 0x00000000); /* disable all */
mtdcr(UIC1CR, 0x00000000); /* all non-critical */
mtdcr(UIC1PR, 0xffffe0ff); /* per ref-board manual */
mtdcr(UIC1TR, 0x00ffc000); /* per ref-board manual */
mtdcr(UIC1VR, 0x00000001); /* int31 highest, base=0x000 */
mtdcr(UIC1SR, 0xffffffff); /* clear all */
/*--------------------------------------------------------------------
* Setup the GPIO pins

12
board/amcc/bubinga/bubinga.c
Unescape View File

@ -29,12 +29,12 @@ long int spd_sdram(void);
int board_early_init_f(void)
{
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr(uicer, 0x00000000); /* disable all ints */
mtdcr(uiccr, 0x00000010);
mtdcr(uicpr, 0xFFFF7FF0); /* set int polarities */
mtdcr(uictr, 0x00000010); /* set int trigger levels */
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
mtdcr(UIC0ER, 0x00000000); /* disable all ints */
mtdcr(UIC0CR, 0x00000010);
mtdcr(UIC0PR, 0xFFFF7FF0); /* set int polarities */
mtdcr(UIC0TR, 0x00000010); /* set int trigger levels */
mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
/*
* Configure CPC0_PCI to enable PerWE as output

62
board/amcc/canyonlands/canyonlands.c
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@ -116,37 +116,37 @@ int board_early_init_f(void)
/*
* Setup the interrupt controller polarities, triggers, etc.
*/
mtdcr(uic0sr, 0xffffffff); /* clear all */
mtdcr(uic0er, 0x00000000); /* disable all */
mtdcr(uic0cr, 0x00000005); /* ATI & UIC1 crit are critical */
mtdcr(uic0pr, 0xffffffff); /* per ref-board manual */
mtdcr(uic0tr, 0x00000000); /* per ref-board manual */
mtdcr(uic0vr, 0x00000000); /* int31 highest, base=0x000 */
mtdcr(uic0sr, 0xffffffff); /* clear all */
mtdcr(uic1sr, 0xffffffff); /* clear all */
mtdcr(uic1er, 0x00000000); /* disable all */
mtdcr(uic1cr, 0x00000000); /* all non-critical */
mtdcr(uic1pr, 0xffffffff); /* per ref-board manual */
mtdcr(uic1tr, 0x00000000); /* per ref-board manual */
mtdcr(uic1vr, 0x00000000); /* int31 highest, base=0x000 */
mtdcr(uic1sr, 0xffffffff); /* clear all */
mtdcr(uic2sr, 0xffffffff); /* clear all */
mtdcr(uic2er, 0x00000000); /* disable all */
mtdcr(uic2cr, 0x00000000); /* all non-critical */
mtdcr(uic2pr, 0xffffffff); /* per ref-board manual */
mtdcr(uic2tr, 0x00000000); /* per ref-board manual */
mtdcr(uic2vr, 0x00000000); /* int31 highest, base=0x000 */
mtdcr(uic2sr, 0xffffffff); /* clear all */
mtdcr(uic3sr, 0xffffffff); /* clear all */
mtdcr(uic3er, 0x00000000); /* disable all */
mtdcr(uic3cr, 0x00000000); /* all non-critical */
mtdcr(uic3pr, 0xffffffff); /* per ref-board manual */
mtdcr(uic3tr, 0x00000000); /* per ref-board manual */
mtdcr(uic3vr, 0x00000000); /* int31 highest, base=0x000 */
mtdcr(uic3sr, 0xffffffff); /* clear all */
mtdcr(UIC0SR, 0xffffffff); /* clear all */
mtdcr(UIC0ER, 0x00000000); /* disable all */
mtdcr(UIC0CR, 0x00000005); /* ATI & UIC1 crit are critical */
mtdcr(UIC0PR, 0xffffffff); /* per ref-board manual */
mtdcr(UIC0TR, 0x00000000); /* per ref-board manual */
mtdcr(UIC0VR, 0x00000000); /* int31 highest, base=0x000 */
mtdcr(UIC0SR, 0xffffffff); /* clear all */
mtdcr(UIC1SR, 0xffffffff); /* clear all */
mtdcr(UIC1ER, 0x00000000); /* disable all */
mtdcr(UIC1CR, 0x00000000); /* all non-critical */
mtdcr(UIC1PR, 0xffffffff); /* per ref-board manual */
mtdcr(UIC1TR, 0x00000000); /* per ref-board manual */
mtdcr(UIC1VR, 0x00000000); /* int31 highest, base=0x000 */
mtdcr(UIC1SR, 0xffffffff); /* clear all */
mtdcr(UIC2SR, 0xffffffff); /* clear all */
mtdcr(UIC2ER, 0x00000000); /* disable all */
mtdcr(UIC2CR, 0x00000000); /* all non-critical */
mtdcr(UIC2PR, 0xffffffff); /* per ref-board manual */
mtdcr(UIC2TR, 0x00000000); /* per ref-board manual */
mtdcr(UIC2VR, 0x00000000); /* int31 highest, base=0x000 */
mtdcr(UIC2SR, 0xffffffff); /* clear all */
mtdcr(UIC3SR, 0xffffffff); /* clear all */
mtdcr(UIC3ER, 0x00000000); /* disable all */
mtdcr(UIC3CR, 0x00000000); /* all non-critical */
mtdcr(UIC3PR, 0xffffffff); /* per ref-board manual */
mtdcr(UIC3TR, 0x00000000); /* per ref-board manual */
mtdcr(UIC3VR, 0x00000000); /* int31 highest, base=0x000 */
mtdcr(UIC3SR, 0xffffffff); /* clear all */
#if !defined(CONFIG_ARCHES)
/* SDR Setting - enable NDFC */

28
board/amcc/ebony/ebony.c
Unescape View File

@ -71,21 +71,21 @@ int board_early_init_f(void)
/*--------------------------------------------------------------------
* Setup the interrupt controller polarities, triggers, etc.
*-------------------------------------------------------------------*/
mtdcr(uic0sr, 0xffffffff); /* clear all */
mtdcr(uic0er, 0x00000000); /* disable all */
mtdcr(uic0cr, 0x00000009); /* SMI & UIC1 crit are critical */
mtdcr(uic0pr, 0xfffffe13); /* per ref-board manual */
mtdcr(uic0tr, 0x01c00008); /* per ref-board manual */
mtdcr(uic0vr, 0x00000001); /* int31 highest, base=0x000 */
mtdcr(uic0sr, 0xffffffff); /* clear all */
mtdcr(UIC0SR, 0xffffffff); /* clear all */
mtdcr(UIC0ER, 0x00000000); /* disable all */
mtdcr(UIC0CR, 0x00000009); /* SMI & UIC1 crit are critical */
mtdcr(UIC0PR, 0xfffffe13); /* per ref-board manual */
mtdcr(UIC0TR, 0x01c00008); /* per ref-board manual */
mtdcr(UIC0VR, 0x00000001); /* int31 highest, base=0x000 */
mtdcr(UIC0SR, 0xffffffff); /* clear all */
mtdcr(uic1sr, 0xffffffff); /* clear all */
mtdcr(uic1er, 0x00000000); /* disable all */
mtdcr(uic1cr, 0x00000000); /* all non-critical */
mtdcr(uic1pr, 0xffffe0ff); /* per ref-board manual */
mtdcr(uic1tr, 0x00ffc000); /* per ref-board manual */
mtdcr(uic1vr, 0x00000001); /* int31 highest, base=0x000 */
mtdcr(uic1sr, 0xffffffff); /* clear all */
mtdcr(UIC1SR, 0xffffffff); /* clear all */
mtdcr(UIC1ER, 0x00000000); /* disable all */
mtdcr(UIC1CR, 0x00000000); /* all non-critical */
mtdcr(UIC1PR, 0xffffe0ff); /* per ref-board manual */
mtdcr(UIC1TR, 0x00ffc000); /* per ref-board manual */
mtdcr(UIC1VR, 0x00000001); /* int31 highest, base=0x000 */
mtdcr(UIC1SR, 0xffffffff); /* clear all */
return 0;
}

72
board/amcc/katmai/katmai.c
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@ -183,42 +183,42 @@ int board_early_init_f (void)
* Set critical interrupt values. Set interrupt polarities. Set interrupt
* trigger levels. Make bit 0 High priority. Clear all interrupts again.
*------------------------------------------------------------------------*/
mtdcr (uic3sr, 0xffffffff); /* Clear all interrupts */
mtdcr (uic3er, 0x00000000); /* disable all interrupts */
mtdcr (uic3cr, 0x00000000); /* Set Critical / Non Critical interrupts: */
mtdcr (uic3pr, 0xffffffff); /* Set Interrupt Polarities*/
mtdcr (uic3tr, 0x001fffff); /* Set Interrupt Trigger Levels */
mtdcr (uic3vr, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
mtdcr (uic3sr, 0x00000000); /* clear all interrupts*/
mtdcr (uic3sr, 0xffffffff); /* clear all interrupts*/
mtdcr (uic2sr, 0xffffffff); /* Clear all interrupts */
mtdcr (uic2er, 0x00000000); /* disable all interrupts*/
mtdcr (uic2cr, 0x00000000); /* Set Critical / Non Critical interrupts*/
mtdcr (uic2pr, 0xebebebff); /* Set Interrupt Polarities*/
mtdcr (uic2tr, 0x74747400); /* Set Interrupt Trigger Levels */
mtdcr (uic2vr, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
mtdcr (uic2sr, 0x00000000); /* clear all interrupts */
mtdcr (uic2sr, 0xffffffff); /* clear all interrupts */
mtdcr (uic1sr, 0xffffffff); /* Clear all interrupts*/
mtdcr (uic1er, 0x00000000); /* disable all interrupts*/
mtdcr (uic1cr, 0x00000000); /* Set Critical / Non Critical interrupts*/
mtdcr (uic1pr, 0xffffffff); /* Set Interrupt Polarities */
mtdcr (uic1tr, 0x001f8040); /* Set Interrupt Trigger Levels*/
mtdcr (uic1vr, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
mtdcr (uic1sr, 0x00000000); /* clear all interrupts*/
mtdcr (uic1sr, 0xffffffff); /* clear all interrupts*/
mtdcr (uic0sr, 0xffffffff); /* Clear all interrupts */
mtdcr (uic0er, 0x00000000); /* disable all interrupts excepted cascade to be checked */
mtdcr (uic0cr, 0x00104001); /* Set Critical / Non Critical interrupts*/
mtdcr (uic0pr, 0xffffffff); /* Set Interrupt Polarities*/
mtdcr (uic0tr, 0x010f0004); /* Set Interrupt Trigger Levels */
mtdcr (uic0vr, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
mtdcr (uic0sr, 0x00000000); /* clear all interrupts*/
mtdcr (uic0sr, 0xffffffff); /* clear all interrupts*/
mtdcr (UIC3SR, 0xffffffff); /* Clear all interrupts */
mtdcr (UIC3ER, 0x00000000); /* disable all interrupts */
mtdcr (UIC3CR, 0x00000000); /* Set Critical / Non Critical interrupts: */
mtdcr (UIC3PR, 0xffffffff); /* Set Interrupt Polarities*/
mtdcr (UIC3TR, 0x001fffff); /* Set Interrupt Trigger Levels */
mtdcr (UIC3VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
mtdcr (UIC3SR, 0x00000000); /* clear all interrupts*/
mtdcr (UIC3SR, 0xffffffff); /* clear all interrupts*/
mtdcr (UIC2SR, 0xffffffff); /* Clear all interrupts */
mtdcr (UIC2ER, 0x00000000); /* disable all interrupts*/
mtdcr (UIC2CR, 0x00000000); /* Set Critical / Non Critical interrupts*/
mtdcr (UIC2PR, 0xebebebff); /* Set Interrupt Polarities*/
mtdcr (UIC2TR, 0x74747400); /* Set Interrupt Trigger Levels */
mtdcr (UIC2VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
mtdcr (UIC2SR, 0x00000000); /* clear all interrupts */
mtdcr (UIC2SR, 0xffffffff); /* clear all interrupts */
mtdcr (UIC1SR, 0xffffffff); /* Clear all interrupts*/
mtdcr (UIC1ER, 0x00000000); /* disable all interrupts*/
mtdcr (UIC1CR, 0x00000000); /* Set Critical / Non Critical interrupts*/
mtdcr (UIC1PR, 0xffffffff); /* Set Interrupt Polarities */
mtdcr (UIC1TR, 0x001f8040); /* Set Interrupt Trigger Levels*/
mtdcr (UIC1VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
mtdcr (UIC1SR, 0x00000000); /* clear all interrupts*/
mtdcr (UIC1SR, 0xffffffff); /* clear all interrupts*/
mtdcr (UIC0SR, 0xffffffff); /* Clear all interrupts */
mtdcr (UIC0ER, 0x00000000); /* disable all interrupts excepted cascade to be checked */
mtdcr (UIC0CR, 0x00104001); /* Set Critical / Non Critical interrupts*/
mtdcr (UIC0PR, 0xffffffff); /* Set Interrupt Polarities*/
mtdcr (UIC0TR, 0x010f0004); /* Set Interrupt Trigger Levels */
mtdcr (UIC0VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
mtdcr (UIC0SR, 0x00000000); /* clear all interrupts*/
mtdcr (UIC0SR, 0xffffffff); /* clear all interrupts*/
mfsdr(SDR0_MFR, mfr);
mfr |= SDR0_MFR_FIXD; /* Workaround for PCI/DMA */

52
board/amcc/kilauea/kilauea.c
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@ -158,33 +158,33 @@ int board_early_init_f (void)
| interrupts again.
+-------------------------------------------------------------------*/
mtdcr (uic2sr, 0xffffffff); /* Clear all interrupts */
mtdcr (uic2er, 0x00000000); /* disable all interrupts */
mtdcr (uic2cr, 0x00000000); /* Set Critical / Non Critical interrupts */
mtdcr (uic2pr, 0xf7ffffff); /* Set Interrupt Polarities */
mtdcr (uic2tr, 0x01e1fff8); /* Set Interrupt Trigger Levels */
mtdcr (uic2vr, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
mtdcr (uic2sr, 0x00000000); /* clear all interrupts */
mtdcr (uic2sr, 0xffffffff); /* clear all interrupts */
mtdcr (uic1sr, 0xffffffff); /* Clear all interrupts */
mtdcr (uic1er, 0x00000000); /* disable all interrupts */
mtdcr (uic1cr, 0x00000000); /* Set Critical / Non Critical interrupts */
mtdcr (uic1pr, 0xfffac785); /* Set Interrupt Polarities */
mtdcr (uic1tr, 0x001d0040); /* Set Interrupt Trigger Levels */
mtdcr (uic1vr, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
mtdcr (uic1sr, 0x00000000); /* clear all interrupts */
mtdcr (uic1sr, 0xffffffff); /* clear all interrupts */
mtdcr (uic0sr, 0xffffffff); /* Clear all interrupts */
mtdcr (uic0er, 0x0000000a); /* Disable all interrupts */
mtdcr (UIC2SR, 0xffffffff); /* Clear all interrupts */
mtdcr (UIC2ER, 0x00000000); /* disable all interrupts */
mtdcr (UIC2CR, 0x00000000); /* Set Critical / Non Critical interrupts */
mtdcr (UIC2PR, 0xf7ffffff); /* Set Interrupt Polarities */
mtdcr (UIC2TR, 0x01e1fff8); /* Set Interrupt Trigger Levels */
mtdcr (UIC2VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
mtdcr (UIC2SR, 0x00000000); /* clear all interrupts */
mtdcr (UIC2SR, 0xffffffff); /* clear all interrupts */
mtdcr (UIC1SR, 0xffffffff); /* Clear all interrupts */
mtdcr (UIC1ER, 0x00000000); /* disable all interrupts */
mtdcr (UIC1CR, 0x00000000); /* Set Critical / Non Critical interrupts */
mtdcr (UIC1PR, 0xfffac785); /* Set Interrupt Polarities */
mtdcr (UIC1TR, 0x001d0040); /* Set Interrupt Trigger Levels */
mtdcr (UIC1VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
mtdcr (UIC1SR, 0x00000000); /* clear all interrupts */
mtdcr (UIC1SR, 0xffffffff); /* clear all interrupts */
mtdcr (UIC0SR, 0xffffffff); /* Clear all interrupts */
mtdcr (UIC0ER, 0x0000000a); /* Disable all interrupts */
/* Except cascade UIC0 and UIC1 */
mtdcr (uic0cr, 0x00000000); /* Set Critical / Non Critical interrupts */
mtdcr (uic0pr, 0xffbfefef); /* Set Interrupt Polarities */
mtdcr (uic0tr, 0x00007000); /* Set Interrupt Trigger Levels */
mtdcr (uic0vr, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
mtdcr (uic0sr, 0x00000000); /* clear all interrupts */
mtdcr (uic0sr, 0xffffffff); /* clear all interrupts */
mtdcr (UIC0CR, 0x00000000); /* Set Critical / Non Critical interrupts */
mtdcr (UIC0PR, 0xffbfefef); /* Set Interrupt Polarities */
mtdcr (UIC0TR, 0x00007000); /* Set Interrupt Trigger Levels */
mtdcr (UIC0VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
mtdcr (UIC0SR, 0x00000000); /* clear all interrupts */
mtdcr (UIC0SR, 0xffffffff); /* clear all interrupts */
/*
* Note: Some cores are still in reset when the chip starts, so

34
board/amcc/luan/luan.c
Unescape View File

@ -49,23 +49,23 @@ int board_early_init_f(void)
mtebc( PB2AP, 0x03800000 );
mtebc( PB2CR, 0xff838000 ); /* ebc0_b2cr, 2MB at 0xff800000 CS2 */
mtdcr( uic1sr, 0xffffffff ); /* Clear all interrupts */
mtdcr( uic1er, 0x00000000 ); /* disable all interrupts */
mtdcr( uic1cr, 0x00000000 ); /* Set Critical / Non Critical interrupts */
mtdcr( uic1pr, 0x7fff83ff ); /* Set Interrupt Polarities */
mtdcr( uic1tr, 0x001f8000 ); /* Set Interrupt Trigger Levels */
mtdcr( uic1vr, 0x00000001 ); /* Set Vect base=0,INT31 Highest priority */
mtdcr( uic1sr, 0x00000000 ); /* clear all interrupts */
mtdcr( uic1sr, 0xffffffff );
mtdcr( uic0sr, 0xffffffff ); /* Clear all interrupts */
mtdcr( uic0er, 0x00000000 ); /* disable all interrupts excepted cascade */
mtdcr( uic0cr, 0x00000001 ); /* Set Critical / Non Critical interrupts */
mtdcr( uic0pr, 0xffffffff ); /* Set Interrupt Polarities */
mtdcr( uic0tr, 0x01000004 ); /* Set Interrupt Trigger Levels */
mtdcr( uic0vr, 0x00000001 ); /* Set Vect base=0,INT31 Highest priority */
mtdcr( uic0sr, 0x00000000 ); /* clear all interrupts */
mtdcr( uic0sr, 0xffffffff );
mtdcr( UIC1SR, 0xffffffff ); /* Clear all interrupts */
mtdcr( UIC1ER, 0x00000000 ); /* disable all interrupts */
mtdcr( UIC1CR, 0x00000000 ); /* Set Critical / Non Critical interrupts */
mtdcr( UIC1PR, 0x7fff83ff ); /* Set Interrupt Polarities */
mtdcr( UIC1TR, 0x001f8000 ); /* Set Interrupt Trigger Levels */
mtdcr( UIC1VR, 0x00000001 ); /* Set Vect base=0,INT31 Highest priority */
mtdcr( UIC1SR, 0x00000000 ); /* clear all interrupts */
mtdcr( UIC1SR, 0xffffffff );
mtdcr( UIC0SR, 0xffffffff ); /* Clear all interrupts */
mtdcr( UIC0ER, 0x00000000 ); /* disable all interrupts excepted cascade */
mtdcr( UIC0CR, 0x00000001 ); /* Set Critical / Non Critical interrupts */
mtdcr( UIC0PR, 0xffffffff ); /* Set Interrupt Polarities */
mtdcr( UIC0TR, 0x01000004 ); /* Set Interrupt Trigger Levels */
mtdcr( UIC0VR, 0x00000001 ); /* Set Vect base=0,INT31 Highest priority */
mtdcr( UIC0SR, 0x00000000 ); /* clear all interrupts */
mtdcr( UIC0SR, 0xffffffff );
mfsdr(SDR0_MFR, mfr);
mfr |= SDR0_MFR_FIXD; /* Workaround for PCI/DMA */

48
board/amcc/makalu/makalu.c
Unescape View File

@ -159,33 +159,33 @@ int board_early_init_f (void)
| interrupts again.
+-------------------------------------------------------------------*/
mtdcr (uic2sr, 0xffffffff); /* Clear all interrupts */
mtdcr (uic2er, 0x00000000); /* disable all interrupts */
mtdcr (uic2cr, 0x00000000); /* Set Critical / Non Critical interrupts */
mtdcr (uic2pr, 0xf7ffffff); /* Set Interrupt Polarities */
mtdcr (uic2tr, 0x01e1fff8); /* Set Interrupt Trigger Levels */
mtdcr (uic2vr, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
mtdcr (uic2sr, 0x00000000); /* clear all interrupts */
mtdcr (uic2sr, 0xffffffff); /* clear all interrupts */
mtdcr (UIC2SR, 0xffffffff); /* Clear all interrupts */
mtdcr (UIC2ER, 0x00000000); /* disable all interrupts */
mtdcr (UIC2CR, 0x00000000); /* Set Critical / Non Critical interrupts */
mtdcr (UIC2PR, 0xf7ffffff); /* Set Interrupt Polarities */
mtdcr (UIC2TR, 0x01e1fff8); /* Set Interrupt Trigger Levels */
mtdcr (UIC2VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
mtdcr (UIC2SR, 0x00000000); /* clear all interrupts */
mtdcr (UIC2SR, 0xffffffff); /* clear all interrupts */
mtdcr (uic1sr, 0xffffffff); /* Clear all interrupts */
mtdcr (uic1er, 0x00000000); /* disable all interrupts */
mtdcr (uic1cr, 0x00000000); /* Set Critical / Non Critical interrupts */
mtdcr (uic1pr, 0xfffac785); /* Set Interrupt Polarities */
mtdcr (uic1tr, 0x001d0040); /* Set Interrupt Trigger Levels */
mtdcr (uic1vr, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
mtdcr (uic1sr, 0x00000000); /* clear all interrupts */
mtdcr (uic1sr, 0xffffffff); /* clear all interrupts */
mtdcr (UIC1SR, 0xffffffff); /* Clear all interrupts */
mtdcr (UIC1ER, 0x00000000); /* disable all interrupts */
mtdcr (UIC1CR, 0x00000000); /* Set Critical / Non Critical interrupts */
mtdcr (UIC1PR, 0xfffac785); /* Set Interrupt Polarities */
mtdcr (UIC1TR, 0x001d0040); /* Set Interrupt Trigger Levels */
mtdcr (UIC1VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
mtdcr (UIC1SR, 0x00000000); /* clear all interrupts */
mtdcr (UIC1SR, 0xffffffff); /* clear all interrupts */
mtdcr (uic0sr, 0xffffffff); /* Clear all interrupts */
mtdcr (uic0er, 0x0000000a); /* Disable all interrupts */
mtdcr (UIC0SR, 0xffffffff); /* Clear all interrupts */
mtdcr (UIC0ER, 0x0000000a); /* Disable all interrupts */
/* Except cascade UIC0 and UIC1 */
mtdcr (uic0cr, 0x00000000); /* Set Critical / Non Critical interrupts */
mtdcr (uic0pr, 0xffbfefef); /* Set Interrupt Polarities */
mtdcr (uic0tr, 0x00007000); /* Set Interrupt Trigger Levels */
mtdcr (uic0vr, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
mtdcr (uic0sr, 0x00000000); /* clear all interrupts */
mtdcr (uic0sr, 0xffffffff); /* clear all interrupts */
mtdcr (UIC0CR, 0x00000000); /* Set Critical / Non Critical interrupts */
mtdcr (UIC0PR, 0xffbfefef); /* Set Interrupt Polarities */
mtdcr (UIC0TR, 0x00007000); /* Set Interrupt Trigger Levels */
mtdcr (UIC0VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
mtdcr (UIC0SR, 0x00000000); /* clear all interrupts */
mtdcr (UIC0SR, 0xffffffff); /* clear all interrupts */
/*
* Note: Some cores are still in reset when the chip starts, so

60
board/amcc/ocotea/ocotea.c
Unescape View File

@ -159,36 +159,36 @@ int board_early_init_f (void)
* UIC2 UIC1
* UIC3 UIC2
*/
mtdcr (uic1sr, 0xffffffff); /* clear all */
mtdcr (uic1er, 0x00000000); /* disable all */
mtdcr (uic1cr, 0x00000009); /* SMI & UIC1 crit are critical */
mtdcr (uic1pr, 0xfffffe13); /* per ref-board manual */
mtdcr (uic1tr, 0x01c00008); /* per ref-board manual */
mtdcr (uic1vr, 0x00000001); /* int31 highest, base=0x000 */
mtdcr (uic1sr, 0xffffffff); /* clear all */
mtdcr (uic2sr, 0xffffffff); /* clear all */
mtdcr (uic2er, 0x00000000); /* disable all */
mtdcr (uic2cr, 0x00000000); /* all non-critical */
mtdcr (uic2pr, 0xffffe0ff); /* per ref-board manual */
mtdcr (uic2tr, 0x00ffc000); /* per ref-board manual */
mtdcr (uic2vr, 0x00000001); /* int31 highest, base=0x000 */
mtdcr (uic2sr, 0xffffffff); /* clear all */
mtdcr (uic3sr, 0xffffffff); /* clear all */
mtdcr (uic3er, 0x00000000); /* disable all */
mtdcr (uic3cr, 0x00000000); /* all non-critical */
mtdcr (uic3pr, 0xffffffff); /* per ref-board manual */
mtdcr (uic3tr, 0x00ff8c0f); /* per ref-board manual */
mtdcr (uic3vr, 0x00000001); /* int31 highest, base=0x000 */
mtdcr (uic3sr, 0xffffffff); /* clear all */
mtdcr (uic0sr, 0xfc000000); /* clear all */
mtdcr (uic0er, 0x00000000); /* disable all */
mtdcr (uic0cr, 0x00000000); /* all non-critical */
mtdcr (uic0pr, 0xfc000000); /* */
mtdcr (uic0tr, 0x00000000); /* */
mtdcr (uic0vr, 0x00000001); /* */
mtdcr (UIC1SR, 0xffffffff); /* clear all */
mtdcr (UIC1ER, 0x00000000); /* disable all */
mtdcr (UIC1CR, 0x00000009); /* SMI & UIC1 crit are critical */
mtdcr (UIC1PR, 0xfffffe13); /* per ref-board manual */
mtdcr (UIC1TR, 0x01c00008); /* per ref-board manual */
mtdcr (UIC1VR, 0x00000001); /* int31 highest, base=0x000 */
mtdcr (UIC1SR, 0xffffffff); /* clear all */
mtdcr (UIC2SR, 0xffffffff); /* clear all */
mtdcr (UIC2ER, 0x00000000); /* disable all */
mtdcr (UIC2CR, 0x00000000); /* all non-critical */
mtdcr (UIC2PR, 0xffffe0ff); /* per ref-board manual */
mtdcr (UIC2TR, 0x00ffc000); /* per ref-board manual */
mtdcr (UIC2VR, 0x00000001); /* int31 highest, base=0x000 */
mtdcr (UIC2SR, 0xffffffff); /* clear all */
mtdcr (UIC3SR, 0xffffffff); /* clear all */
mtdcr (UIC3ER, 0x00000000); /* disable all */
mtdcr (UIC3CR, 0x00000000); /* all non-critical */
mtdcr (UIC3PR, 0xffffffff); /* per ref-board manual */
mtdcr (UIC3TR, 0x00ff8c0f); /* per ref-board manual */
mtdcr (UIC3VR, 0x00000001); /* int31 highest, base=0x000 */
mtdcr (UIC3SR, 0xffffffff); /* clear all */
mtdcr (UIC0SR, 0xfc000000); /* clear all */
mtdcr (UIC0ER, 0x00000000); /* disable all */
mtdcr (UIC0CR, 0x00000000); /* all non-critical */
mtdcr (UIC0PR, 0xfc000000); /* */
mtdcr (UIC0TR, 0x00000000); /* */
mtdcr (UIC0VR, 0x00000001); /* */
mfsdr (SDR0_MFR, mfr);
mfr &= ~SDR0_MFR_ECS_MASK;
/* mtsdr(SDR0_MFR, mfr); */

60
board/amcc/redwood/redwood.c
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@ -416,41 +416,41 @@ static void early_init_UIC(void)
* interrupt trigger levels. Make bit 0 High priority. Clear all
* interrupts again.
*/
mtdcr(uic3sr, 0xffffffff); /* Clear all interrupts */
mtdcr(uic3er, 0x00000000); /* disable all interrupts */
mtdcr(uic3cr, 0x00000000); /* Set Critical / Non Critical
mtdcr(UIC3SR, 0xffffffff); /* Clear all interrupts */
mtdcr(UIC3ER, 0x00000000); /* disable all interrupts */
mtdcr(UIC3CR, 0x00000000); /* Set Critical / Non Critical
* interrupts */
mtdcr(uic3pr, 0xffffffff); /* Set Interrupt Polarities */
mtdcr(uic3tr, 0x001fffff); /* Set Interrupt Trigger Levels */
mtdcr(uic3vr, 0x00000000); /* int31 highest, base=0x000 */
mtdcr(uic3sr, 0xffffffff); /* clear all interrupts */
mtdcr(uic2sr, 0xffffffff); /* Clear all interrupts */
mtdcr(uic2er, 0x00000000); /* disable all interrupts */
mtdcr(uic2cr, 0x00000000); /* Set Critical / Non Critical
mtdcr(UIC3PR, 0xffffffff); /* Set Interrupt Polarities */
mtdcr(UIC3TR, 0x001fffff); /* Set Interrupt Trigger Levels */
mtdcr(UIC3VR, 0x00000000); /* int31 highest, base=0x000 */
mtdcr(UIC3SR, 0xffffffff); /* clear all interrupts */
mtdcr(UIC2SR, 0xffffffff); /* Clear all interrupts */
mtdcr(UIC2ER, 0x00000000); /* disable all interrupts */
mtdcr(UIC2CR, 0x00000000); /* Set Critical / Non Critical
* interrupts */
mtdcr(uic2pr, 0xebebebff); /* Set Interrupt Polarities */
mtdcr(uic2tr, 0x74747400); /* Set Interrupt Trigger Levels */
mtdcr(uic2vr, 0x00000000); /* int31 highest, base=0x000 */
mtdcr(uic2sr, 0xffffffff); /* clear all interrupts */
mtdcr(uic1sr, 0xffffffff); /* Clear all interrupts */
mtdcr(uic1er, 0x00000000); /* disable all interrupts */
mtdcr(uic1cr, 0x00000000); /* Set Critical / Non Critical
mtdcr(UIC2PR, 0xebebebff); /* Set Interrupt Polarities */
mtdcr(UIC2TR, 0x74747400); /* Set Interrupt Trigger Levels */
mtdcr(UIC2VR, 0x00000000); /* int31 highest, base=0x000 */
mtdcr(UIC2SR, 0xffffffff); /* clear all interrupts */
mtdcr(UIC1SR, 0xffffffff); /* Clear all interrupts */
mtdcr(UIC1ER, 0x00000000); /* disable all interrupts */
mtdcr(UIC1CR, 0x00000000); /* Set Critical / Non Critical
* interrupts */
mtdcr(uic1pr, 0xffffffff); /* Set Interrupt Polarities */
mtdcr(uic1tr, 0x001fc0ff); /* Set Interrupt Trigger Levels */
mtdcr(uic1vr, 0x00000000); /* int31 highest, base=0x000 */
mtdcr(uic1sr, 0xffffffff); /* clear all interrupts */
mtdcr(UIC1PR, 0xffffffff); /* Set Interrupt Polarities */
mtdcr(UIC1TR, 0x001fc0ff); /* Set Interrupt Trigger Levels */
mtdcr(UIC1VR, 0x00000000); /* int31 highest, base=0x000 */
mtdcr(UIC1SR, 0xffffffff); /* clear all interrupts */
mtdcr(uic0sr, 0xffffffff); /* Clear all interrupts */
mtdcr(uic0er, 0x00000000); /* disable all interrupts excepted
mtdcr(UIC0SR, 0xffffffff); /* Clear all interrupts */
mtdcr(UIC0ER, 0x00000000); /* disable all interrupts excepted
* cascade to be checked */
mtdcr(uic0cr, 0x00104001); /* Set Critical / Non Critical
mtdcr(UIC0CR, 0x00104001); /* Set Critical / Non Critical
* interrupts */
mtdcr(uic0pr, 0xffffffff); /* Set Interrupt Polarities */
mtdcr(uic0tr, 0x000f003c); /* Set Interrupt Trigger Levels */
mtdcr(uic0vr, 0x00000000); /* int31 highest, base=0x000 */
mtdcr(uic0sr, 0xffffffff); /* clear all interrupts */
mtdcr(UIC0PR, 0xffffffff); /* Set Interrupt Polarities */
mtdcr(UIC0TR, 0x000f003c); /* Set Interrupt Trigger Levels */
mtdcr(UIC0VR, 0x00000000); /* int31 highest, base=0x000 */
mtdcr(UIC0SR, 0xffffffff); /* clear all interrupts */
}

46
board/amcc/sequoia/sequoia.c
Unescape View File

@ -52,29 +52,29 @@ int board_early_init_f(void)
/*
* Setup the interrupt controller polarities, triggers, etc.
*/
mtdcr(uic0sr, 0xffffffff); /* clear all */
mtdcr(uic0er, 0x00000000); /* disable all */
mtdcr(uic0cr, 0x00000005); /* ATI & UIC1 crit are critical */
mtdcr(uic0pr, 0xfffff7ff); /* per ref-board manual */
mtdcr(uic0tr, 0x00000000); /* per ref-board manual */
mtdcr(uic0vr, 0x00000000); /* int31 highest, base=0x000 */
mtdcr(uic0sr, 0xffffffff); /* clear all */
mtdcr(uic1sr, 0xffffffff); /* clear all */
mtdcr(uic1er, 0x00000000); /* disable all */
mtdcr(uic1cr, 0x00000000); /* all non-critical */
mtdcr(uic1pr, 0xffffffff); /* per ref-board manual */
mtdcr(uic1tr, 0x00000000); /* per ref-board manual */
mtdcr(uic1vr, 0x00000000); /* int31 highest, base=0x000 */
mtdcr(uic1sr, 0xffffffff); /* clear all */
mtdcr(uic2sr, 0xffffffff); /* clear all */
mtdcr(uic2er, 0x00000000); /* disable all */
mtdcr(uic2cr, 0x00000000); /* all non-critical */
mtdcr(uic2pr, 0xffffffff); /* per ref-board manual */
mtdcr(uic2tr, 0x00000000); /* per ref-board manual */
mtdcr(uic2vr, 0x00000000); /* int31 highest, base=0x000 */
mtdcr(uic2sr, 0xffffffff); /* clear all */
mtdcr(UIC0SR, 0xffffffff); /* clear all */
mtdcr(UIC0ER, 0x00000000); /* disable all */
mtdcr(UIC0CR, 0x00000005); /* ATI & UIC1 crit are critical */
mtdcr(UIC0PR, 0xfffff7ff); /* per ref-board manual */
mtdcr(UIC0TR, 0x00000000); /* per ref-board manual */
mtdcr(UIC0VR, 0x00000000); /* int31 highest, base=0x000 */
mtdcr(UIC0SR, 0xffffffff); /* clear all */
mtdcr(UIC1SR, 0xffffffff); /* clear all */
mtdcr(UIC1ER, 0x00000000); /* disable all */
mtdcr(UIC1CR, 0x00000000); /* all non-critical */
mtdcr(UIC1PR, 0xffffffff); /* per ref-board manual */
mtdcr(UIC1TR, 0x00000000); /* per ref-board manual */
mtdcr(UIC1VR, 0x00000000); /* int31 highest, base=0x000 */
mtdcr(UIC1SR, 0xffffffff); /* clear all */
mtdcr(UIC2SR, 0xffffffff); /* clear all */
mtdcr(UIC2ER, 0x00000000); /* disable all */
mtdcr(UIC2CR, 0x00000000); /* all non-critical */
mtdcr(UIC2PR, 0xffffffff); /* per ref-board manual */
mtdcr(UIC2TR, 0x00000000); /* per ref-board manual */
mtdcr(UIC2VR, 0x00000000); /* int31 highest, base=0x000 */
mtdcr(UIC2SR, 0xffffffff); /* clear all */
/* 50MHz tmrclk */
out_8((u8 *) CONFIG_SYS_BCSR_BASE + 0x04, 0x00);

14
board/amcc/taihu/taihu.c
Unescape View File

@ -40,13 +40,13 @@ int board_early_init_f(void)
{
lcd_init();
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr(uicer, 0x00000000); /* disable all ints */
mtdcr(uiccr, 0x00000000);
mtdcr(uicpr, 0xFFFF7F00); /* set int polarities */
mtdcr(uictr, 0x00000000); /* set int trigger levels */
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */
mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
mtdcr(UIC0ER, 0x00000000); /* disable all ints */
mtdcr(UIC0CR, 0x00000000);
mtdcr(UIC0PR, 0xFFFF7F00); /* set int polarities */
mtdcr(UIC0TR, 0x00000000); /* set int trigger levels */
mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority */
mtebc(PB3AP, CONFIG_SYS_EBC_PB3AP); /* memory bank 3 (CPLD_LCM) initialization */
mtebc(PB3CR, CONFIG_SYS_EBC_PB3CR);

60
board/amcc/taishan/taishan.c
Unescape View File

@ -132,36 +132,36 @@ int board_early_init_f (void)
* UIC2 UIC1
* UIC3 UIC2
*/
mtdcr (uic1sr, 0xffffffff); /* clear all */
mtdcr (uic1er, 0x00000000); /* disable all */
mtdcr (uic1cr, 0x00000009); /* SMI & UIC1 crit are critical */
mtdcr (uic1pr, 0xfffffe13); /* per ref-board manual */
mtdcr (uic1tr, 0x01c00008); /* per ref-board manual */
mtdcr (uic1vr, 0x00000001); /* int31 highest, base=0x000 */
mtdcr (uic1sr, 0xffffffff); /* clear all */
mtdcr (uic2sr, 0xffffffff); /* clear all */
mtdcr (uic2er, 0x00000000); /* disable all */
mtdcr (uic2cr, 0x00000000); /* all non-critical */
mtdcr (uic2pr, 0xffffe0ff); /* per ref-board manual */
mtdcr (uic2tr, 0x00ffc000); /* per ref-board manual */
mtdcr (uic2vr, 0x00000001); /* int31 highest, base=0x000 */
mtdcr (uic2sr, 0xffffffff); /* clear all */
mtdcr (uic3sr, 0xffffffff); /* clear all */
mtdcr (uic3er, 0x00000000); /* disable all */
mtdcr (uic3cr, 0x00000000); /* all non-critical */
mtdcr (uic3pr, 0xffffffff); /* per ref-board manual */
mtdcr (uic3tr, 0x00ff8c0f); /* per ref-board manual */
mtdcr (uic3vr, 0x00000001); /* int31 highest, base=0x000 */
mtdcr (uic3sr, 0xffffffff); /* clear all */
mtdcr (uic0sr, 0xfc000000); /* clear all */
mtdcr (uic0er, 0x00000000); /* disable all */
mtdcr (uic0cr, 0x00000000); /* all non-critical */
mtdcr (uic0pr, 0xfc000000); /* */
mtdcr (uic0tr, 0x00000000); /* */
mtdcr (uic0vr, 0x00000001); /* */
mtdcr (UIC1SR, 0xffffffff); /* clear all */
mtdcr (UIC1ER, 0x00000000); /* disable all */
mtdcr (UIC1CR, 0x00000009); /* SMI & UIC1 crit are critical */
mtdcr (UIC1PR, 0xfffffe13); /* per ref-board manual */
mtdcr (UIC1TR, 0x01c00008); /* per ref-board manual */
mtdcr (UIC1VR, 0x00000001); /* int31 highest, base=0x000 */
mtdcr (UIC1SR, 0xffffffff); /* clear all */
mtdcr (UIC2SR, 0xffffffff); /* clear all */
mtdcr (UIC2ER, 0x00000000); /* disable all */
mtdcr (UIC2CR, 0x00000000); /* all non-critical */
mtdcr (UIC2PR, 0xffffe0ff); /* per ref-board manual */
mtdcr (UIC2TR, 0x00ffc000); /* per ref-board manual */
mtdcr (UIC2VR, 0x00000001); /* int31 highest, base=0x000 */
mtdcr (UIC2SR, 0xffffffff); /* clear all */
mtdcr (UIC3SR, 0xffffffff); /* clear all */
mtdcr (UIC3ER, 0x00000000); /* disable all */
mtdcr (UIC3CR, 0x00000000); /* all non-critical */
mtdcr (UIC3PR, 0xffffffff); /* per ref-board manual */
mtdcr (UIC3TR, 0x00ff8c0f); /* per ref-board manual */
mtdcr (UIC3VR, 0x00000001); /* int31 highest, base=0x000 */
mtdcr (UIC3SR, 0xffffffff); /* clear all */
mtdcr (UIC0SR, 0xfc000000); /* clear all */
mtdcr (UIC0ER, 0x00000000); /* disable all */
mtdcr (UIC0CR, 0x00000000); /* all non-critical */
mtdcr (UIC0PR, 0xfc000000); /* */
mtdcr (UIC0TR, 0x00000000); /* */
mtdcr (UIC0VR, 0x00000001); /* */
/* Enable two GPIO 10~11 and TraceA signal */
mfsdr(SDR0_PFC0,reg);

14
board/amcc/walnut/walnut.c
Unescape View File

@ -47,13 +47,13 @@ int board_early_init_f(void)
|
+-------------------------------------------------------------------------*/
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr(uicer, 0x00000000); /* disable all ints */
mtdcr(uiccr, 0x00000020); /* set all but FPGA SMI to be non-critical */
mtdcr(uicpr, 0xFFFFFFE0); /* set int polarities */
mtdcr(uictr, 0x10000000); /* set int trigger levels */
mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
mtdcr(UIC0ER, 0x00000000); /* disable all ints */
mtdcr(UIC0CR, 0x00000020); /* set all but FPGA SMI to be non-critical */
mtdcr(UIC0PR, 0xFFFFFFE0); /* set int polarities */
mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */
mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority */
mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
/* set UART1 control to select CTS/RTS */
#define FPGA_BRDC 0xF0300004

30
board/amcc/yosemite/yosemite.c
Unescape View File

@ -82,21 +82,21 @@ int board_early_init_f(void)
/*--------------------------------------------------------------------
* Setup the interrupt controller polarities, triggers, etc.
*-------------------------------------------------------------------*/
mtdcr(uic0sr, 0xffffffff); /* clear all */
mtdcr(uic0er, 0x00000000); /* disable all */
mtdcr(uic0cr, 0x00000009); /* ATI & UIC1 crit are critical */
mtdcr(uic0pr, 0xfffffe13); /* per ref-board manual */
mtdcr(uic0tr, 0x01c00008); /* per ref-board manual */
mtdcr(uic0vr, 0x00000001); /* int31 highest, base=0x000 */
mtdcr(uic0sr, 0xffffffff); /* clear all */
mtdcr(uic1sr, 0xffffffff); /* clear all */
mtdcr(uic1er, 0x00000000); /* disable all */
mtdcr(uic1cr, 0x00000000); /* all non-critical */
mtdcr(uic1pr, 0xffffe0ff); /* per ref-board manual */
mtdcr(uic1tr, 0x00ffc000); /* per ref-board manual */
mtdcr(uic1vr, 0x00000001); /* int31 highest, base=0x000 */
mtdcr(uic1sr, 0xffffffff); /* clear all */
mtdcr(UIC0SR, 0xffffffff); /* clear all */
mtdcr(UIC0ER, 0x00000000); /* disable all */
mtdcr(UIC0CR, 0x00000009); /* ATI & UIC1 crit are critical */
mtdcr(UIC0PR, 0xfffffe13); /* per ref-board manual */
mtdcr(UIC0TR, 0x01c00008); /* per ref-board manual */
mtdcr(UIC0VR, 0x00000001); /* int31 highest, base=0x000 */
mtdcr(UIC0SR, 0xffffffff); /* clear all */
mtdcr(UIC1SR, 0xffffffff); /* clear all */
mtdcr(UIC1ER, 0x00000000); /* disable all */
mtdcr(UIC1CR, 0x00000000); /* all non-critical */
mtdcr(UIC1PR, 0xffffe0ff); /* per ref-board manual */
mtdcr(UIC1TR, 0x00ffc000); /* per ref-board manual */
mtdcr(UIC1VR, 0x00000001); /* int31 highest, base=0x000 */
mtdcr(UIC1SR, 0xffffffff); /* clear all */
/*--------------------------------------------------------------------
* Setup other serial configuration

64
board/amcc/yucca/yucca.c
Unescape View File

@ -485,50 +485,50 @@ int board_early_init_f (void)
| interrupt trigger levels. Make bit 0 High priority. Clear all
| interrupts again.
+-------------------------------------------------------------------*/
mtdcr (uic3sr, 0xffffffff); /* Clear all interrupts */
mtdcr (uic3er, 0x00000000); /* disable all interrupts */
mtdcr (uic3cr, 0x00000000); /* Set Critical / Non Critical
mtdcr (UIC3SR, 0xffffffff); /* Clear all interrupts */
mtdcr (UIC3ER, 0x00000000); /* disable all interrupts */
mtdcr (UIC3CR, 0x00000000); /* Set Critical / Non Critical
* interrupts */
mtdcr (uic3pr, 0xffffffff); /* Set Interrupt Polarities */
mtdcr (uic3tr, 0x001fffff); /* Set Interrupt Trigger Levels */
mtdcr (uic3vr, 0x00000001); /* Set Vect base=0,INT31 Highest
mtdcr (UIC3PR, 0xffffffff); /* Set Interrupt Polarities */
mtdcr (UIC3TR, 0x001fffff); /* Set Interrupt Trigger Levels */
mtdcr (UIC3VR, 0x00000001); /* Set Vect base=0,INT31 Highest
* priority */
mtdcr (uic3sr, 0x00000000); /* clear all interrupts */
mtdcr (uic3sr, 0xffffffff); /* clear all interrupts */
mtdcr (UIC3SR, 0x00000000); /* clear all interrupts */
mtdcr (UIC3SR, 0xffffffff); /* clear all interrupts */
mtdcr (uic2sr, 0xffffffff); /* Clear all interrupts */
mtdcr (uic2er, 0x00000000); /* disable all interrupts */
mtdcr (uic2cr, 0x00000000); /* Set Critical / Non Critical
mtdcr (UIC2SR, 0xffffffff); /* Clear all interrupts */
mtdcr (UIC2ER, 0x00000000); /* disable all interrupts */
mtdcr (UIC2CR, 0x00000000); /* Set Critical / Non Critical
* interrupts */
mtdcr (uic2pr, 0xebebebff); /* Set Interrupt Polarities */
mtdcr (uic2tr, 0x74747400); /* Set Interrupt Trigger Levels */
mtdcr (uic2vr, 0x00000001); /* Set Vect base=0,INT31 Highest
mtdcr (UIC2PR, 0xebebebff); /* Set Interrupt Polarities */
mtdcr (UIC2TR, 0x74747400); /* Set Interrupt Trigger Levels */
mtdcr (UIC2VR, 0x00000001); /* Set Vect base=0,INT31 Highest
* priority */
mtdcr (uic2sr, 0x00000000); /* clear all interrupts */
mtdcr (uic2sr, 0xffffffff); /* clear all interrupts */
mtdcr (UIC2SR, 0x00000000); /* clear all interrupts */
mtdcr (UIC2SR, 0xffffffff); /* clear all interrupts */
mtdcr (uic1sr, 0xffffffff); /* Clear all interrupts */
mtdcr (uic1er, 0x00000000); /* disable all interrupts */
mtdcr (uic1cr, 0x00000000); /* Set Critical / Non Critical
mtdcr (UIC1SR, 0xffffffff); /* Clear all interrupts */
mtdcr (UIC1ER, 0x00000000); /* disable all interrupts */
mtdcr (UIC1CR, 0x00000000); /* Set Critical / Non Critical
* interrupts */
mtdcr (uic1pr, 0xffffffff); /* Set Interrupt Polarities */
mtdcr (uic1tr, 0x001f8040); /* Set Interrupt Trigger Levels */
mtdcr (uic1vr, 0x00000001); /* Set Vect base=0,INT31 Highest
mtdcr (UIC1PR, 0xffffffff); /* Set Interrupt Polarities */
mtdcr (UIC1TR, 0x001f8040); /* Set Interrupt Trigger Levels */
mtdcr (UIC1VR, 0x00000001); /* Set Vect base=0,INT31 Highest
* priority */
mtdcr (uic1sr, 0x00000000); /* clear all interrupts */
mtdcr (uic1sr, 0xffffffff); /* clear all interrupts */
mtdcr (UIC1SR, 0x00000000); /* clear all interrupts */
mtdcr (UIC1SR, 0xffffffff); /* clear all interrupts */
mtdcr (uic0sr, 0xffffffff); /* Clear all interrupts */
mtdcr (uic0er, 0x00000000); /* disable all interrupts excepted
mtdcr (UIC0SR, 0xffffffff); /* Clear all interrupts */
mtdcr (UIC0ER, 0x00000000); /* disable all interrupts excepted
* cascade to be checked */
mtdcr (uic0cr, 0x00104001); /* Set Critical / Non Critical
mtdcr (UIC0CR, 0x00104001); /* Set Critical / Non Critical
* interrupts */
mtdcr (uic0pr, 0xffffffff); /* Set Interrupt Polarities */
mtdcr (uic0tr, 0x010f0004); /* Set Interrupt Trigger Levels */
mtdcr (uic0vr, 0x00000001); /* Set Vect base=0,INT31 Highest
mtdcr (UIC0PR, 0xffffffff); /* Set Interrupt Polarities */
mtdcr (UIC0TR, 0x010f0004); /* Set Interrupt Trigger Levels */
mtdcr (UIC0VR, 0x00000001); /* Set Vect base=0,INT31 Highest
* priority */
mtdcr (uic0sr, 0x00000000); /* clear all interrupts */
mtdcr (uic0sr, 0xffffffff); /* clear all interrupts */
mtdcr (UIC0SR, 0x00000000); /* clear all interrupts */
mtdcr (UIC0SR, 0xffffffff); /* clear all interrupts */
mfsdr(SDR0_MFR, mfr);
mfr |= SDR0_MFR_FIXD; /* Workaround for PCI/DMA */

14
board/cray/L1/L1.c
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@ -113,13 +113,13 @@ int board_early_init_f (void)
{
/* Running from ROM: global data is still READONLY */
init_sdram ();
mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr (uicer, 0x00000000); /* disable all ints */
mtdcr (uiccr, 0x00000020); /* set all but FPGA SMI to be non-critical */
mtdcr (uicpr, 0xFFFFFFE0); /* set int polarities */
mtdcr (uictr, 0x10000000); /* set int trigger levels */
mtdcr (uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */
mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
mtdcr (UIC0ER, 0x00000000); /* disable all ints */
mtdcr (UIC0CR, 0x00000020); /* set all but FPGA SMI to be non-critical */
mtdcr (UIC0PR, 0xFFFFFFE0); /* set int polarities */
mtdcr (UIC0TR, 0x10000000); /* set int trigger levels */
mtdcr (UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority */
mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
return 0;
}

14
board/csb272/csb272.c
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@ -87,13 +87,13 @@ int board_early_init_f(void)
|
+-------------------------------------------------------------------------*/
mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr (uicer, 0x00000000); /* disable all ints */
mtdcr (uiccr, 0x00000000); /* set all to be non-critical */
mtdcr (uicpr, 0xFFFFFF83); /* set int polarities */
mtdcr (uictr, 0x10000000); /* set int trigger levels */
mtdcr (uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */
mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
mtdcr (UIC0ER, 0x00000000); /* disable all ints */
mtdcr (UIC0CR, 0x00000000); /* set all to be non-critical */
mtdcr (UIC0PR, 0xFFFFFF83); /* set int polarities */
mtdcr (UIC0TR, 0x10000000); /* set int trigger levels */
mtdcr (UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority */
mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
mtebc (EBC0_CFG, 0xa8400000); /* EBC always driven */

14
board/csb472/csb472.c
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@ -55,13 +55,13 @@ int board_early_init_f(void)
|
+-------------------------------------------------------------------------*/
mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr (uicer, 0x00000000); /* disable all ints */
mtdcr (uiccr, 0x00000000); /* set all to be non-critical */
mtdcr (uicpr, 0xFFFFFF83); /* set int polarities */
mtdcr (uictr, 0x10000000); /* set int trigger levels */
mtdcr (uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */
mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
mtdcr (UIC0ER, 0x00000000); /* disable all ints */
mtdcr (UIC0CR, 0x00000000); /* set all to be non-critical */
mtdcr (UIC0PR, 0xFFFFFF83); /* set int polarities */
mtdcr (UIC0TR, 0x10000000); /* set int trigger levels */
mtdcr (UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority */
mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
mtebc (EBC0_CFG, 0xa8400000); /* EBC always driven */

14
board/dave/PPChameleonEVB/PPChameleonEVB.c
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@ -53,13 +53,13 @@ int board_early_init_f (void)
* IRQ 30 (EXT IRQ 5)
* IRQ 31 (EXT IRQ 6)
*/
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr(uicer, 0x00000000); /* disable all ints */
mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/
mtdcr(uicpr, 0xFFFFFF80); /* set int polarities */
mtdcr(uictr, 0x10000000); /* set int trigger levels */
mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
mtdcr(UIC0ER, 0x00000000); /* disable all ints */
mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/
mtdcr(UIC0PR, 0xFFFFFF80); /* set int polarities */
mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */
mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority*/
mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
/*
* EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us

14
board/eric/eric.c
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@ -62,13 +62,13 @@ int board_early_init_f (void)
|
+-------------------------------------------------------------------------*/
mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr (uicer, 0x00000000); /* disable all ints */
mtdcr (uiccr, 0x00000000); /* set all SMI to be non-critical */
mtdcr (uicpr, 0xFFFFFF88); /* set int polarities; IRQ3 to 1 */
mtdcr (uictr, 0x10000000); /* set int trigger levels, UART0 is EDGE */
mtdcr (uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */
mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
mtdcr (UIC0ER, 0x00000000); /* disable all ints */
mtdcr (UIC0CR, 0x00000000); /* set all SMI to be non-critical */
mtdcr (UIC0PR, 0xFFFFFF88); /* set int polarities; IRQ3 to 1 */
mtdcr (UIC0TR, 0x10000000); /* set int trigger levels, UART0 is EDGE */
mtdcr (UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority */
mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
mtdcr (CPC0_CR0, 0x00002000); /* set IRQ6 as GPIO23 to generate an interrupt request to the PCP2PCI bridge */

14
board/esd/apc405/apc405.c
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@ -155,13 +155,13 @@ int board_early_init_f (void)
* IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
* IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
*/
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr(uicer, 0x00000000); /* disable all ints */
mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/
mtdcr(uicpr, 0xFFFFFF81); /* set int polarities */
mtdcr(uictr, 0x10000000); /* set int trigger levels */
mtdcr(uicvcr, 0x00000001); /* set vect base=0 */
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
mtdcr(UIC0ER, 0x00000000); /* disable all ints */
mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/
mtdcr(UIC0PR, 0xFFFFFF81); /* set int polarities */
mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */
mtdcr(UIC0VCR, 0x00000001); /* set vect base=0 */
mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
/*
* EBC Configuration Register: set ready timeout to 512 ebc-clks

14
board/esd/ar405/ar405.c
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@ -130,13 +130,13 @@ int board_early_init_f (void)
* IRQ 30 (EXT IRQ 5) PCI SLOT 3; active low; level sensitive
* IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
*/
mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr (uicer, 0x00000000); /* disable all ints */
mtdcr (uiccr, 0x00000000); /* set all to be non-critical */
mtdcr (uicpr, 0xFFFFFF81); /* set int polarities */
mtdcr (uictr, 0x10000000); /* set int trigger levels */
mtdcr (uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */
mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
mtdcr (UIC0ER, 0x00000000); /* disable all ints */
mtdcr (UIC0CR, 0x00000000); /* set all to be non-critical */
mtdcr (UIC0PR, 0xFFFFFF81); /* set int polarities */
mtdcr (UIC0TR, 0x10000000); /* set int trigger levels */
mtdcr (UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority */
mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
out_be16((void *)0xf03000ec, 0x0fff); /* enable interrupts in fpga */

14
board/esd/ash405/ash405.c
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@ -66,13 +66,13 @@ int board_early_init_f (void)
* IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
* IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
*/
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr(uicer, 0x00000000); /* disable all ints */
mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/
mtdcr(uicpr, 0xFFFFFF9F); /* set int polarities */
mtdcr(uictr, 0x10000000); /* set int trigger levels */
mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
mtdcr(UIC0ER, 0x00000000); /* disable all ints */
mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/
mtdcr(UIC0PR, 0xFFFFFF9F); /* set int polarities */
mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */
mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority*/
mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
/*
* EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us

14
board/esd/canbt/canbt.c
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@ -134,13 +134,13 @@ int board_early_init_f (void)
* IRQ 30 (EXT IRQ 5) PCI SLOT 3; active low; level sensitive
* IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
*/
mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr (uicer, 0x00000000); /* disable all ints */
mtdcr (uiccr, 0x00000000); /* set all to be non-critical */
mtdcr (uicpr, 0xFFFFFF81); /* set int polarities */
mtdcr (uictr, 0x10000000); /* set int trigger levels */
mtdcr (uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */
mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
mtdcr (UIC0ER, 0x00000000); /* disable all ints */
mtdcr (UIC0CR, 0x00000000); /* set all to be non-critical */
mtdcr (UIC0PR, 0xFFFFFF81); /* set int polarities */
mtdcr (UIC0TR, 0x10000000); /* set int trigger levels */
mtdcr (UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority */
mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
return 0;
}

14
board/esd/cms700/cms700.c
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@ -45,13 +45,13 @@ int board_early_init_f (void)
* IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
* IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
*/
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr(uicer, 0x00000000); /* disable all ints */
mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/
mtdcr(uicpr, 0xFFFFFF80); /* set int polarities */
mtdcr(uictr, 0x10000000); /* set int trigger levels */
mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
mtdcr(UIC0ER, 0x00000000); /* disable all ints */
mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/
mtdcr(UIC0PR, 0xFFFFFF80); /* set int polarities */
mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */
mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority*/
mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
/*
* EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us

16
board/esd/cpci2dp/cpci2dp.c
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@ -58,14 +58,14 @@ int board_early_init_f (void)
* IRQ 30 (EXT IRQ 5) PCI SLOT 3; active low; level sensitive
* IRQ 31 (EXT IRQ 6) unused
*/
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr(uicer, 0x00000000); /* disable all ints */
mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/
mtdcr(uicpr, 0xFFFFFF81); /* set int polarities */
mtdcr(uictr, 0x10000000); /* set int trigger levels */
mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
mtdcr(UIC0ER, 0x00000000); /* disable all ints */
mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/
mtdcr(UIC0PR, 0xFFFFFF81); /* set int polarities */
mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */
mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority*/
mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
return 0;
}

18
board/esd/cpci405/cpci405.c
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@ -179,22 +179,22 @@ int board_early_init_f(void)
* IRQ 30 (EXT IRQ 5) PCI SLOT 3; active low; level sensitive
* IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
*/
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr(uicer, 0x00000000); /* disable all ints */
mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/
mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
mtdcr(UIC0ER, 0x00000000); /* disable all ints */
mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/
#if defined(CONFIG_CPCI405_6U)
if (cpci405_version() == 3) {
mtdcr(uicpr, 0xFFFFFF99); /* set int polarities */
mtdcr(UIC0PR, 0xFFFFFF99); /* set int polarities */
} else {
mtdcr(uicpr, 0xFFFFFF81); /* set int polarities */
mtdcr(UIC0PR, 0xFFFFFF81); /* set int polarities */
}
#else
mtdcr(uicpr, 0xFFFFFF81); /* set int polarities */
mtdcr(UIC0PR, 0xFFFFFF81); /* set int polarities */
#endif
mtdcr(uictr, 0x10000000); /* set int trigger levels */
mtdcr(uicvcr, 0x00000001); /* set vect base=0,
mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */
mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,
* INT0 highest priority */
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
return 0;
}

16
board/esd/cpciiser4/cpciiser4.c
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@ -129,14 +129,14 @@ int board_early_init_f (void)
* IRQ 30 (EXT IRQ 5) PCI SLOT 3; active low; level sensitive
* IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
*/
mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr (uicer, 0x00000000); /* disable all ints */
mtdcr (uiccr, 0x00000000); /* set all to be non-critical */
/* mtdcr(uicpr, 0xFFFFFF81); / set int polarities */
mtdcr (uicpr, 0xFFFFFF80); /* set int polarities */
mtdcr (uictr, 0x10000000); /* set int trigger levels */
mtdcr (uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */
mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
mtdcr (UIC0ER, 0x00000000); /* disable all ints */
mtdcr (UIC0CR, 0x00000000); /* set all to be non-critical */
/* mtdcr(UIC0PR, 0xFFFFFF81); / set int polarities */
mtdcr (UIC0PR, 0xFFFFFF80); /* set int polarities */
mtdcr (UIC0TR, 0x10000000); /* set int trigger levels */
mtdcr (UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority */
mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
return 0;
}

14
board/esd/dp405/dp405.c
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@ -43,13 +43,13 @@ int board_early_init_f (void)
* IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
* IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
*/
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr(uicer, 0x00000000); /* disable all ints */
mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/
mtdcr(uicpr, 0xFFFFFF80); /* set int polarities */
mtdcr(uictr, 0x10000000); /* set int trigger levels */
mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
mtdcr(UIC0ER, 0x00000000); /* disable all ints */
mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/
mtdcr(UIC0PR, 0xFFFFFF80); /* set int polarities */
mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */
mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority*/
mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
/*
* EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us

14
board/esd/du405/du405.c
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@ -124,13 +124,13 @@ int board_early_init_f (void)
* IRQ 30 (EXT IRQ 5) unused; active low; level sensitive
* IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
*/
mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr (uicer, 0x00000000); /* disable all ints */
mtdcr (uiccr, 0x00000000); /* set all to be non-critical */
mtdcr (uicpr, 0xFFFFFFB1); /* set int polarities */
mtdcr (uictr, 0x10000000); /* set int trigger levels */
mtdcr (uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */
mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
mtdcr (UIC0ER, 0x00000000); /* disable all ints */
mtdcr (UIC0CR, 0x00000000); /* set all to be non-critical */
mtdcr (UIC0PR, 0xFFFFFFB1); /* set int polarities */
mtdcr (UIC0TR, 0x10000000); /* set int trigger levels */
mtdcr (UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority */
mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
/*
* EBC Configuration Register: set ready timeout to 100 us

42
board/esd/du440/du440.c
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@ -87,37 +87,37 @@ int board_early_init_f(void)
/*
* Setup the interrupt controller polarities, triggers, etc.
*/
mtdcr(uic0sr, 0xffffffff); /* clear all */
mtdcr(uic0er, 0x00000000); /* disable all */
mtdcr(uic0cr, 0x00000005); /* ATI & UIC1 crit are critical */
mtdcr(uic0pr, 0xfffff7ff); /* per ref-board manual */
mtdcr(uic0tr, 0x00000000); /* per ref-board manual */
mtdcr(uic0vr, 0x00000000); /* int31 highest, base=0x000 */
mtdcr(uic0sr, 0xffffffff); /* clear all */
mtdcr(UIC0SR, 0xffffffff); /* clear all */
mtdcr(UIC0ER, 0x00000000); /* disable all */
mtdcr(UIC0CR, 0x00000005); /* ATI & UIC1 crit are critical */
mtdcr(UIC0PR, 0xfffff7ff); /* per ref-board manual */
mtdcr(UIC0TR, 0x00000000); /* per ref-board manual */
mtdcr(UIC0VR, 0x00000000); /* int31 highest, base=0x000 */
mtdcr(UIC0SR, 0xffffffff); /* clear all */
/*
* UIC1:
* bit30: ext. Irq 1: PLD : int 32+30
*/
mtdcr(uic1sr, 0xffffffff); /* clear all */
mtdcr(uic1er, 0x00000000); /* disable all */
mtdcr(uic1cr, 0x00000000); /* all non-critical */
mtdcr(uic1pr, 0xfffffffd);
mtdcr(uic1tr, 0x00000000);
mtdcr(uic1vr, 0x00000000); /* int31 highest, base=0x000 */
mtdcr(uic1sr, 0xffffffff); /* clear all */
mtdcr(UIC1SR, 0xffffffff); /* clear all */
mtdcr(UIC1ER, 0x00000000); /* disable all */
mtdcr(UIC1CR, 0x00000000); /* all non-critical */
mtdcr(UIC1PR, 0xfffffffd);
mtdcr(UIC1TR, 0x00000000);
mtdcr(UIC1VR, 0x00000000); /* int31 highest, base=0x000 */
mtdcr(UIC1SR, 0xffffffff); /* clear all */
/*
* UIC2
* bit3: ext. Irq 2: DCF77 : int 64+3
*/
mtdcr(uic2sr, 0xffffffff); /* clear all */
mtdcr(uic2er, 0x00000000); /* disable all */
mtdcr(uic2cr, 0x00000000); /* all non-critical */
mtdcr(uic2pr, 0xffffffff); /* per ref-board manual */
mtdcr(uic2tr, 0x00000000); /* per ref-board manual */
mtdcr(uic2vr, 0x00000000); /* int31 highest, base=0x000 */
mtdcr(uic2sr, 0xffffffff); /* clear all */
mtdcr(UIC2SR, 0xffffffff); /* clear all */
mtdcr(UIC2ER, 0x00000000); /* disable all */
mtdcr(UIC2CR, 0x00000000); /* all non-critical */
mtdcr(UIC2PR, 0xffffffff); /* per ref-board manual */
mtdcr(UIC2TR, 0x00000000); /* per ref-board manual */
mtdcr(UIC2VR, 0x00000000); /* int31 highest, base=0x000 */
mtdcr(UIC2SR, 0xffffffff); /* clear all */
/* select Ethernet pins */
mfsdr(SDR0_PFC1, sdr0_pfc1);

14
board/esd/hh405/hh405.c
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@ -363,13 +363,13 @@ int board_early_init_f (void)
* IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
* IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
*/
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr(uicer, 0x00000000); /* disable all ints */
mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/
mtdcr(uicpr, CONFIG_SYS_UIC0_POLARITY);/* set int polarities */
mtdcr(uictr, 0x10000000); /* set int trigger levels */
mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
mtdcr(UIC0ER, 0x00000000); /* disable all ints */
mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/
mtdcr(UIC0PR, CONFIG_SYS_UIC0_POLARITY);/* set int polarities */
mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */
mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority*/
mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
/*
* EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us

14
board/esd/hub405/hub405.c
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@ -86,13 +86,13 @@ int board_early_init_f (void)
* IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
* IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
*/
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr(uicer, 0x00000000); /* disable all ints */
mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/
mtdcr(uicpr, 0xFFFFFF9F); /* set int polarities */
mtdcr(uictr, 0x10000000); /* set int trigger levels */
mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
mtdcr(UIC0ER, 0x00000000); /* disable all ints */
mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/
mtdcr(UIC0PR, 0xFFFFFF9F); /* set int polarities */
mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */
mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority*/
mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
/*
* EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us

14
board/esd/ocrtc/ocrtc.c
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@ -45,13 +45,13 @@ int board_early_init_f (void)
* IRQ 30 (EXT IRQ 5) PCI SLOT 3; active low; level sensitive
* IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
*/
mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr (uicer, 0x00000000); /* disable all ints */
mtdcr (uiccr, 0x00000000); /* set all to be non-critical */
mtdcr (uicpr, 0xFFFFFF81); /* set int polarities */
mtdcr (uictr, 0x10000000); /* set int trigger levels */
mtdcr (uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */
mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
mtdcr (UIC0ER, 0x00000000); /* disable all ints */
mtdcr (UIC0CR, 0x00000000); /* set all to be non-critical */
mtdcr (UIC0PR, 0xFFFFFF81); /* set int polarities */
mtdcr (UIC0TR, 0x10000000); /* set int trigger levels */
mtdcr (UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority */
mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
/*
* EBC Configuration Register: clear EBTC -> high-Z ebc signals between

16
board/esd/pci405/pci405.c
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@ -155,13 +155,13 @@ int board_early_init_f (void)
* IRQ 30 (EXT IRQ 5) FPGA Timestamp; active low; level sensitive
* IRQ 31 (EXT IRQ 6) PCI Reset; active low; level sensitive
*/
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr(uicer, 0x00000000); /* disable all ints */
mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/
mtdcr(uicpr, 0xFFFFFF80); /* set int polarities */
mtdcr(uictr, 0x10000000); /* set int trigger levels */
mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
mtdcr(UIC0ER, 0x00000000); /* disable all ints */
mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/
mtdcr(UIC0PR, 0xFFFFFF80); /* set int polarities */
mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */
mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority*/
mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
/*
* Setup GPIO pins (IRQ4/GPIO21 as GPIO)
@ -271,7 +271,7 @@ int misc_init_r (void)
pci_write_config_dword(PCIDEVID_405GP, i, *ptr++);
}
}
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
*magic = 0; /* clear pci reconfig magic again */
}

14
board/esd/plu405/plu405.c
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@ -78,13 +78,13 @@ int board_early_init_f(void)
* IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
* IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
*/
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr(uicer, 0x00000000); /* disable all ints */
mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/
mtdcr(uicpr, 0xFFFFFF99); /* set int polarities */
mtdcr(uictr, 0x10000000); /* set int trigger levels */
mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest prio */
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
mtdcr(UIC0ER, 0x00000000); /* disable all ints */
mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/
mtdcr(UIC0PR, 0xFFFFFF99); /* set int polarities */
mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */
mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest prio */
mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
/*
* EBC Configuration Register: set ready timeout to

14
board/esd/pmc405/pmc405.c
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@ -48,13 +48,13 @@ int board_early_init_f (void)
* IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
* IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
*/
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr(uicer, 0x00000000); /* disable all ints */
mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/
mtdcr(uicpr, 0xFFFFFF81); /* set int polarities */
mtdcr(uictr, 0x10000000); /* set int trigger levels */
mtdcr(uicvcr, 0x00000001); /* set vect base=0, INT0 highest priority */
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
mtdcr(UIC0ER, 0x00000000); /* disable all ints */
mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/
mtdcr(UIC0PR, 0xFFFFFF81); /* set int polarities */
mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */
mtdcr(UIC0VCR, 0x00000001); /* set vect base=0, INT0 highest priority */
mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
/*
* EBC Configuration Register:

14
board/esd/pmc405de/pmc405de.c
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@ -114,13 +114,13 @@ int board_early_init_f(void)
* IRQ 30 (EXT IRQ 5) ETH1-PHY-IRQ#; active low; level sensitive
* IRQ 31 (EXT IRQ 6) PLD-IRQ#; active low; level sensitive
*/
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr(uicer, 0x00000000); /* disable all ints */
mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/
mtdcr(uicpr, 0xFFFFFF80); /* set int polarities */
mtdcr(uictr, 0x10000000); /* set int trigger levels */
mtdcr(uicvcr, 0x00000001); /* set vect base=0, INT0 highest prio */
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
mtdcr(UIC0ER, 0x00000000); /* disable all ints */
mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/
mtdcr(UIC0PR, 0xFFFFFF80); /* set int polarities */
mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */
mtdcr(UIC0VCR, 0x00000001); /* set vect base=0, INT0 highest prio */
mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
/*
* EBC Configuration Register:

46
board/esd/pmc440/pmc440.c
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@ -148,29 +148,29 @@ int board_early_init_f(void)
/*
* Setup the interrupt controller polarities, triggers, etc.
*/
mtdcr(uic0sr, 0xffffffff); /* clear all */
mtdcr(uic0er, 0x00000000); /* disable all */
mtdcr(uic0cr, 0x00000005); /* ATI & UIC1 crit are critical */
mtdcr(uic0pr, 0xfffff7ef);
mtdcr(uic0tr, 0x00000000);
mtdcr(uic0vr, 0x00000000); /* int31 highest, base=0x000 */
mtdcr(uic0sr, 0xffffffff); /* clear all */
mtdcr(uic1sr, 0xffffffff); /* clear all */
mtdcr(uic1er, 0x00000000); /* disable all */
mtdcr(uic1cr, 0x00000000); /* all non-critical */
mtdcr(uic1pr, 0xffffc7f5);
mtdcr(uic1tr, 0x00000000);
mtdcr(uic1vr, 0x00000000); /* int31 highest, base=0x000 */
mtdcr(uic1sr, 0xffffffff); /* clear all */
mtdcr(uic2sr, 0xffffffff); /* clear all */
mtdcr(uic2er, 0x00000000); /* disable all */
mtdcr(uic2cr, 0x00000000); /* all non-critical */
mtdcr(uic2pr, 0x27ffffff);
mtdcr(uic2tr, 0x00000000);
mtdcr(uic2vr, 0x00000000); /* int31 highest, base=0x000 */
mtdcr(uic2sr, 0xffffffff); /* clear all */
mtdcr(UIC0SR, 0xffffffff); /* clear all */
mtdcr(UIC0ER, 0x00000000); /* disable all */
mtdcr(UIC0CR, 0x00000005); /* ATI & UIC1 crit are critical */
mtdcr(UIC0PR, 0xfffff7ef);
mtdcr(UIC0TR, 0x00000000);
mtdcr(UIC0VR, 0x00000000); /* int31 highest, base=0x000 */
mtdcr(UIC0SR, 0xffffffff); /* clear all */
mtdcr(UIC1SR, 0xffffffff); /* clear all */
mtdcr(UIC1ER, 0x00000000); /* disable all */
mtdcr(UIC1CR, 0x00000000); /* all non-critical */
mtdcr(UIC1PR, 0xffffc7f5);
mtdcr(UIC1TR, 0x00000000);
mtdcr(UIC1VR, 0x00000000); /* int31 highest, base=0x000 */
mtdcr(UIC1SR, 0xffffffff); /* clear all */
mtdcr(UIC2SR, 0xffffffff); /* clear all */
mtdcr(UIC2ER, 0x00000000); /* disable all */
mtdcr(UIC2CR, 0x00000000); /* all non-critical */
mtdcr(UIC2PR, 0x27ffffff);
mtdcr(UIC2TR, 0x00000000);
mtdcr(UIC2VR, 0x00000000); /* int31 highest, base=0x000 */
mtdcr(UIC2SR, 0xffffffff); /* clear all */
/* select Ethernet pins */
mfsdr(SDR0_PFC1, sdr0_pfc1);

14
board/esd/voh405/voh405.c
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@ -88,13 +88,13 @@ int board_early_init_f (void)
* IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
* IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
*/
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr(uicer, 0x00000000); /* disable all ints */
mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/
mtdcr(uicpr, 0xFFFFFFB5); /* set int polarities */
mtdcr(uictr, 0x10000000); /* set int trigger levels */
mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
mtdcr(UIC0ER, 0x00000000); /* disable all ints */
mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/
mtdcr(UIC0PR, 0xFFFFFFB5); /* set int polarities */
mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */
mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority*/
mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
/*
* EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us

14
board/esd/vom405/vom405.c
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@ -45,13 +45,13 @@ int board_early_init_f (void)
* IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
* IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
*/
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr(uicer, 0x00000000); /* disable all ints */
mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/
mtdcr(uicpr, 0xFFFFFF80); /* set int polarities */
mtdcr(uictr, 0x10000000); /* set int trigger levels */
mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
mtdcr(UIC0ER, 0x00000000); /* disable all ints */
mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/
mtdcr(UIC0PR, 0xFFFFFF80); /* set int polarities */
mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */
mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority*/
mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
/*
* EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us

14
board/esd/wuh405/wuh405.c
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@ -64,13 +64,13 @@ int board_early_init_f (void)
* IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
* IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
*/
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr(uicer, 0x00000000); /* disable all ints */
mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/
mtdcr(uicpr, 0xFFFFFF9F); /* set int polarities */
mtdcr(uictr, 0x10000000); /* set int trigger levels */
mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
mtdcr(UIC0ER, 0x00000000); /* disable all ints */
mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/
mtdcr(UIC0PR, 0xFFFFFF9F); /* set int polarities */
mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */
mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority*/
mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
/*
* EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us

14
board/exbitgen/exbitgen.c
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@ -37,13 +37,13 @@ int board_early_init_f (void)
|
+-------------------------------------------------------------------------*/
mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr (uicer, 0x00000000); /* disable all ints */
mtdcr (uiccr, 0x00000020); /* set all but FPGA SMI to be non-critical */
mtdcr (uicpr, 0xFFFFFF90); /* set int polarities */
mtdcr (uictr, 0x10000000); /* set int trigger levels */
mtdcr (uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */
mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
mtdcr (UIC0ER, 0x00000000); /* disable all ints */
mtdcr (UIC0CR, 0x00000020); /* set all but FPGA SMI to be non-critical */
mtdcr (UIC0PR, 0xFFFFFF90); /* set int polarities */
mtdcr (UIC0TR, 0x10000000); /* set int trigger levels */
mtdcr (UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority */
mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
/* Perform reset of PHY connected to PPC via register in CPLD */
out8 (PHY_CTRL_ADDR, 0x2e); /* activate nRESET,FDX,F100,ANEN, enable output */

26
board/g2000/g2000.c
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@ -38,20 +38,20 @@
int board_early_init_f (void)
{
#if 0 /* test-only */
mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr (uicer, 0x00000000); /* disable all ints */
mtdcr (uiccr, 0x00000010);
mtdcr (uicpr, 0xFFFF7FF0); /* set int polarities */
mtdcr (uictr, 0x00000010); /* set int trigger levels */
mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
mtdcr (UIC0ER, 0x00000000); /* disable all ints */
mtdcr (UIC0CR, 0x00000010);
mtdcr (UIC0PR, 0xFFFF7FF0); /* set int polarities */
mtdcr (UIC0TR, 0x00000010); /* set int trigger levels */
mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
#else
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr(uicer, 0x00000000); /* disable all ints */
mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/
mtdcr(uicpr, 0xFFFFFFF0); /* set int polarities */
mtdcr(uictr, 0x10000000); /* set int trigger levels */
mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
mtdcr(UIC0ER, 0x00000000); /* disable all ints */
mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/
mtdcr(UIC0PR, 0xFFFFFFF0); /* set int polarities */
mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */
mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority*/
mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
#endif
#if 1 /* test-only */

14
board/gdsys/dlvision/dlvision.c
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@ -36,13 +36,13 @@ enum {
int board_early_init_f(void)
{
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr(uicer, 0x00000000); /* disable all ints */
mtdcr(uiccr, 0x00000000); /* set all to be non-critical */
mtdcr(uicpr, 0xFFFFFF80); /* set int polarities */
mtdcr(uictr, 0x10000000); /* set int trigger levels */
mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest prio */
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
mtdcr(UIC0ER, 0x00000000); /* disable all ints */
mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical */
mtdcr(UIC0PR, 0xFFFFFF80); /* set int polarities */
mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */
mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest prio */
mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
/*
* EBC Configuration Register: set ready timeout to 512 ebc-clks

30
board/gdsys/gdppc440etx/gdppc440etx.c
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@ -83,21 +83,21 @@ int board_early_init_f(void)
/*
* Setup the interrupt controller polarities, triggers, etc.
*/
mtdcr(uic0sr, 0xffffffff); /* clear all */
mtdcr(uic0er, 0x00000000); /* disable all */
mtdcr(uic0cr, 0x00000009); /* ATI & UIC1 crit are critical */
mtdcr(uic0pr, 0xfffffe13); /* per ref-board manual */
mtdcr(uic0tr, 0x01c00008); /* per ref-board manual */
mtdcr(uic0vr, 0x00000001); /* int31 highest, base=0x000 */
mtdcr(uic0sr, 0xffffffff); /* clear all */
mtdcr(uic1sr, 0xffffffff); /* clear all */
mtdcr(uic1er, 0x00000000); /* disable all */
mtdcr(uic1cr, 0x00000000); /* all non-critical */
mtdcr(uic1pr, 0xffffe0ff); /* per ref-board manual */
mtdcr(uic1tr, 0x00ffc000); /* per ref-board manual */
mtdcr(uic1vr, 0x00000001); /* int31 highest, base=0x000 */
mtdcr(uic1sr, 0xffffffff); /* clear all */
mtdcr(UIC0SR, 0xffffffff); /* clear all */
mtdcr(UIC0ER, 0x00000000); /* disable all */
mtdcr(UIC0CR, 0x00000009); /* ATI & UIC1 crit are critical */
mtdcr(UIC0PR, 0xfffffe13); /* per ref-board manual */
mtdcr(UIC0TR, 0x01c00008); /* per ref-board manual */
mtdcr(UIC0VR, 0x00000001); /* int31 highest, base=0x000 */
mtdcr(UIC0SR, 0xffffffff); /* clear all */
mtdcr(UIC1SR, 0xffffffff); /* clear all */
mtdcr(UIC1ER, 0x00000000); /* disable all */
mtdcr(UIC1CR, 0x00000000); /* all non-critical */
mtdcr(UIC1PR, 0xffffe0ff); /* per ref-board manual */
mtdcr(UIC1TR, 0x00ffc000); /* per ref-board manual */
mtdcr(UIC1VR, 0x00000001); /* int31 highest, base=0x000 */
mtdcr(UIC1SR, 0xffffffff); /* clear all */
/*
* Setup other serial configuration

62
board/gdsys/intip/intip.c
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@ -44,37 +44,37 @@ int board_early_init_f(void)
/*
* Setup the interrupt controller polarities, triggers, etc.
*/
mtdcr(uic0sr, 0xffffffff); /* clear all */
mtdcr(uic0er, 0x00000000); /* disable all */
mtdcr(uic0cr, 0x00000005); /* ATI & UIC1 crit are critical */
mtdcr(uic0pr, 0xffffffff); /* per ref-board manual */
mtdcr(uic0tr, 0x00000000); /* per ref-board manual */
mtdcr(uic0vr, 0x00000000); /* int31 highest, base=0x000 */
mtdcr(uic0sr, 0xffffffff); /* clear all */
mtdcr(uic1sr, 0xffffffff); /* clear all */
mtdcr(uic1er, 0x00000000); /* disable all */
mtdcr(uic1cr, 0x00000000); /* all non-critical */
mtdcr(uic1pr, 0xffffffff); /* per ref-board manual */
mtdcr(uic1tr, 0x00000000); /* per ref-board manual */
mtdcr(uic1vr, 0x00000000); /* int31 highest, base=0x000 */
mtdcr(uic1sr, 0xffffffff); /* clear all */
mtdcr(uic2sr, 0xffffffff); /* clear all */
mtdcr(uic2er, 0x00000000); /* disable all */
mtdcr(uic2cr, 0x00000000); /* all non-critical */
mtdcr(uic2pr, 0xffffffff); /* per ref-board manual */
mtdcr(uic2tr, 0x00000000); /* per ref-board manual */
mtdcr(uic2vr, 0x00000000); /* int31 highest, base=0x000 */
mtdcr(uic2sr, 0xffffffff); /* clear all */
mtdcr(uic3sr, 0xffffffff); /* clear all */
mtdcr(uic3er, 0x00000000); /* disable all */
mtdcr(uic3cr, 0x00000000); /* all non-critical */
mtdcr(uic3pr, 0xffffffff); /* per ref-board manual */
mtdcr(uic3tr, 0x00000000); /* per ref-board manual */
mtdcr(uic3vr, 0x00000000); /* int31 highest, base=0x000 */
mtdcr(uic3sr, 0xffffffff); /* clear all */
mtdcr(UIC0SR, 0xffffffff); /* clear all */
mtdcr(UIC0ER, 0x00000000); /* disable all */
mtdcr(UIC0CR, 0x00000005); /* ATI & UIC1 crit are critical */
mtdcr(UIC0PR, 0xffffffff); /* per ref-board manual */
mtdcr(UIC0TR, 0x00000000); /* per ref-board manual */
mtdcr(UIC0VR, 0x00000000); /* int31 highest, base=0x000 */
mtdcr(UIC0SR, 0xffffffff); /* clear all */
mtdcr(UIC1SR, 0xffffffff); /* clear all */
mtdcr(UIC1ER, 0x00000000); /* disable all */
mtdcr(UIC1CR, 0x00000000); /* all non-critical */
mtdcr(UIC1PR, 0xffffffff); /* per ref-board manual */
mtdcr(UIC1TR, 0x00000000); /* per ref-board manual */
mtdcr(UIC1VR, 0x00000000); /* int31 highest, base=0x000 */
mtdcr(UIC1SR, 0xffffffff); /* clear all */
mtdcr(UIC2SR, 0xffffffff); /* clear all */
mtdcr(UIC2ER, 0x00000000); /* disable all */
mtdcr(UIC2CR, 0x00000000); /* all non-critical */
mtdcr(UIC2PR, 0xffffffff); /* per ref-board manual */
mtdcr(UIC2TR, 0x00000000); /* per ref-board manual */
mtdcr(UIC2VR, 0x00000000); /* int31 highest, base=0x000 */
mtdcr(UIC2SR, 0xffffffff); /* clear all */
mtdcr(UIC3SR, 0xffffffff); /* clear all */
mtdcr(UIC3ER, 0x00000000); /* disable all */
mtdcr(UIC3CR, 0x00000000); /* all non-critical */
mtdcr(UIC3PR, 0xffffffff); /* per ref-board manual */
mtdcr(UIC3TR, 0x00000000); /* per ref-board manual */
mtdcr(UIC3VR, 0x00000000); /* int31 highest, base=0x000 */
mtdcr(UIC3SR, 0xffffffff); /* clear all */
/*
* Configure PFC (Pin Function Control) registers

14
board/gdsys/neo/neo.c
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@ -31,13 +31,13 @@
int board_early_init_f(void)
{
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr(uicer, 0x00000000); /* disable all ints */
mtdcr(uiccr, 0x00000000); /* set all to be non-critical */
mtdcr(uicpr, 0xFFFFFF80); /* set int polarities */
mtdcr(uictr, 0x10000000); /* set int trigger levels */
mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest prio */
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
mtdcr(UIC0ER, 0x00000000); /* disable all ints */
mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical */
mtdcr(UIC0PR, 0xFFFFFF80); /* set int polarities */
mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */
mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest prio */
mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
/*
* EBC Configuration Register: set ready timeout to 512 ebc-clks

12
board/jse/jse.c
Unescape View File

@ -48,12 +48,12 @@ int board_early_init_f (void)
| IRQ 30 (EXT IRQ 5) SystemACE BRdy (unused)
| IRQ 31 (EXT IRQ 6) (unused)
+-------------------------------------------------------------------------*/
mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr (uicer, 0x00000000); /* disable all ints */
mtdcr (uiccr, 0x00000000); /* set all to be non-critical */
mtdcr (uicpr, 0xFFFFFF87); /* set int polarities */
mtdcr (uictr, 0x10000000); /* set int trigger levels */
mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
mtdcr (UIC0ER, 0x00000000); /* disable all ints */
mtdcr (UIC0CR, 0x00000000); /* set all to be non-critical */
mtdcr (UIC0PR, 0xFFFFFF87); /* set int polarities */
mtdcr (UIC0TR, 0x10000000); /* set int trigger levels */
mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
/* Configure the interface to the SystemACE MCU port.
The SystemACE is fast, but there is no reason to have

46
board/korat/korat.c
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@ -87,29 +87,29 @@ int board_early_init_f(void)
/*
* Setup the interrupt controller polarities, triggers, etc.
*/
mtdcr(uic0sr, 0xffffffff); /* clear all */
mtdcr(uic0er, 0x00000000); /* disable all */
mtdcr(uic0cr, 0x00000005); /* ATI & UIC1 crit are critical */
mtdcr(uic0pr, 0xfffff7ff); /* per ref-board manual */
mtdcr(uic0tr, 0x00000000); /* per ref-board manual */
mtdcr(uic0vr, 0x00000000); /* int31 highest, base=0x000 */
mtdcr(uic0sr, 0xffffffff); /* clear all */
mtdcr(uic1sr, 0xffffffff); /* clear all */
mtdcr(uic1er, 0x00000000); /* disable all */
mtdcr(uic1cr, 0x00000000); /* all non-critical */
mtdcr(uic1pr, 0xffffffff); /* per ref-board manual */
mtdcr(uic1tr, 0x00000000); /* per ref-board manual */
mtdcr(uic1vr, 0x00000000); /* int31 highest, base=0x000 */
mtdcr(uic1sr, 0xffffffff); /* clear all */
mtdcr(uic2sr, 0xffffffff); /* clear all */
mtdcr(uic2er, 0x00000000); /* disable all */
mtdcr(uic2cr, 0x00000000); /* all non-critical */
mtdcr(uic2pr, 0xffffffff); /* per ref-board manual */
mtdcr(uic2tr, 0x00000000); /* per ref-board manual */
mtdcr(uic2vr, 0x00000000); /* int31 highest, base=0x000 */
mtdcr(uic2sr, 0xffffffff); /* clear all */
mtdcr(UIC0SR, 0xffffffff); /* clear all */
mtdcr(UIC0ER, 0x00000000); /* disable all */
mtdcr(UIC0CR, 0x00000005); /* ATI & UIC1 crit are critical */
mtdcr(UIC0PR, 0xfffff7ff); /* per ref-board manual */
mtdcr(UIC0TR, 0x00000000); /* per ref-board manual */
mtdcr(UIC0VR, 0x00000000); /* int31 highest, base=0x000 */
mtdcr(UIC0SR, 0xffffffff); /* clear all */
mtdcr(UIC1SR, 0xffffffff); /* clear all */
mtdcr(UIC1ER, 0x00000000); /* disable all */
mtdcr(UIC1CR, 0x00000000); /* all non-critical */
mtdcr(UIC1PR, 0xffffffff); /* per ref-board manual */
mtdcr(UIC1TR, 0x00000000); /* per ref-board manual */
mtdcr(UIC1VR, 0x00000000); /* int31 highest, base=0x000 */
mtdcr(UIC1SR, 0xffffffff); /* clear all */
mtdcr(UIC2SR, 0xffffffff); /* clear all */
mtdcr(UIC2ER, 0x00000000); /* disable all */
mtdcr(UIC2CR, 0x00000000); /* all non-critical */
mtdcr(UIC2PR, 0xffffffff); /* per ref-board manual */
mtdcr(UIC2TR, 0x00000000); /* per ref-board manual */
mtdcr(UIC2VR, 0x00000000); /* int31 highest, base=0x000 */
mtdcr(UIC2SR, 0xffffffff); /* clear all */
/*
* Take sim card reader and CF controller out of reset. Also enable PHY

46
board/lwmon5/lwmon5.c
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@ -44,29 +44,29 @@ int board_early_init_f(void)
/*--------------------------------------------------------------------
* Setup the interrupt controller polarities, triggers, etc.
*-------------------------------------------------------------------*/
mtdcr(uic0sr, 0xffffffff); /* clear all. if write with 1 then the status is cleared */
mtdcr(uic0er, 0x00000000); /* disable all */
mtdcr(uic0cr, 0x00000000); /* we have not critical interrupts at the moment */
mtdcr(uic0pr, 0xFFBFF1EF); /* Adjustment of the polarity */
mtdcr(uic0tr, 0x00000900); /* per ref-board manual */
mtdcr(uic0vr, 0x00000000); /* int31 highest, base=0x000 is within DDRAM */
mtdcr(uic0sr, 0xffffffff); /* clear all */
mtdcr(uic1sr, 0xffffffff); /* clear all */
mtdcr(uic1er, 0x00000000); /* disable all */
mtdcr(uic1cr, 0x00000000); /* all non-critical */
mtdcr(uic1pr, 0xFFFFC6A5); /* Adjustment of the polarity */
mtdcr(uic1tr, 0x60000040); /* per ref-board manual */
mtdcr(uic1vr, 0x00000000); /* int31 highest, base=0x000 is within DDRAM */
mtdcr(uic1sr, 0xffffffff); /* clear all */
mtdcr(uic2sr, 0xffffffff); /* clear all */
mtdcr(uic2er, 0x00000000); /* disable all */
mtdcr(uic2cr, 0x00000000); /* all non-critical */
mtdcr(uic2pr, 0x27C00000); /* Adjustment of the polarity */
mtdcr(uic2tr, 0x3C000000); /* per ref-board manual */
mtdcr(uic2vr, 0x00000000); /* int31 highest, base=0x000 is within DDRAM */
mtdcr(uic2sr, 0xffffffff); /* clear all */
mtdcr(UIC0SR, 0xffffffff); /* clear all. if write with 1 then the status is cleared */
mtdcr(UIC0ER, 0x00000000); /* disable all */
mtdcr(UIC0CR, 0x00000000); /* we have not critical interrupts at the moment */
mtdcr(UIC0PR, 0xFFBFF1EF); /* Adjustment of the polarity */
mtdcr(UIC0TR, 0x00000900); /* per ref-board manual */
mtdcr(UIC0VR, 0x00000000); /* int31 highest, base=0x000 is within DDRAM */
mtdcr(UIC0SR, 0xffffffff); /* clear all */
mtdcr(UIC1SR, 0xffffffff); /* clear all */
mtdcr(UIC1ER, 0x00000000); /* disable all */
mtdcr(UIC1CR, 0x00000000); /* all non-critical */
mtdcr(UIC1PR, 0xFFFFC6A5); /* Adjustment of the polarity */
mtdcr(UIC1TR, 0x60000040); /* per ref-board manual */
mtdcr(UIC1VR, 0x00000000); /* int31 highest, base=0x000 is within DDRAM */
mtdcr(UIC1SR, 0xffffffff); /* clear all */
mtdcr(UIC2SR, 0xffffffff); /* clear all */
mtdcr(UIC2ER, 0x00000000); /* disable all */
mtdcr(UIC2CR, 0x00000000); /* all non-critical */
mtdcr(UIC2PR, 0x27C00000); /* Adjustment of the polarity */
mtdcr(UIC2TR, 0x3C000000); /* per ref-board manual */
mtdcr(UIC2VR, 0x00000000); /* int31 highest, base=0x000 is within DDRAM */
mtdcr(UIC2SR, 0xffffffff); /* clear all */
/* Trace Pins are disabled. SDR0_PFC0 Register */
mtsdr(SDR0_PFC0, 0x0);

14
board/mpl/mip405/mip405.c
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@ -489,13 +489,13 @@ int board_early_init_f (void)
| caused the interrupt.
|
+-------------------------------------------------------------------------*/
mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr (uicer, 0x00000000); /* disable all ints */
mtdcr (uiccr, 0x00000000); /* set all to be non-critical (for now) */
mtdcr (uicpr, 0xFFFFFF80); /* set int polarities */
mtdcr (uictr, 0x10000000); /* set int trigger levels */
mtdcr (uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */
mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
mtdcr (UIC0ER, 0x00000000); /* disable all ints */
mtdcr (UIC0CR, 0x00000000); /* set all to be non-critical (for now) */
mtdcr (UIC0PR, 0xFFFFFF80); /* set int polarities */
mtdcr (UIC0TR, 0x10000000); /* set int trigger levels */
mtdcr (UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority */
mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
return 0;
}

14
board/mpl/pip405/pip405.c
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@ -552,13 +552,13 @@ int board_early_init_f (void)
| caused the interrupt.
|
+-------------------------------------------------------------------------*/
mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr (uicer, 0x00000000); /* disable all ints */
mtdcr (uiccr, 0x00000000); /* set all to be non-critical (for now) */
mtdcr (uicpr, 0xFFFFFF80); /* set int polarities */
mtdcr (uictr, 0x10000000); /* set int trigger levels */
mtdcr (uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */
mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
mtdcr (UIC0ER, 0x00000000); /* disable all ints */
mtdcr (UIC0CR, 0x00000000); /* set all to be non-critical (for now) */
mtdcr (UIC0PR, 0xFFFFFF80); /* set int polarities */
mtdcr (UIC0TR, 0x10000000); /* set int trigger levels */
mtdcr (UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority */
mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
return 0;
}

12
board/netstal/hcu4/hcu4.c
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@ -58,12 +58,12 @@ int board_early_init_f (void)
* IRQ 17-24 RESERVED/UNUSED
* IRQ 31 (EXT IRQ 6) (unused)
*/
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr(uicer, 0x00000000); /* disable all ints */
mtdcr(uiccr, 0x00000000); /* set all to be non-critical */
mtdcr(uicpr, 0xFFFFE000); /* set int polarities */
mtdcr(uictr, 0x00000000); /* set int trigger levels */
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
mtdcr(UIC0ER, 0x00000000); /* disable all ints */
mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical */
mtdcr(UIC0PR, 0xFFFFE000); /* set int polarities */
mtdcr(UIC0TR, 0x00000000); /* set int trigger levels */
mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
mtdcr(CPC0_CR1, CPC0_CR1_VALUE);
mtdcr(CPC0_ECR, 0x60606000);

46
board/netstal/hcu5/hcu5.c
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@ -129,29 +129,29 @@ int board_early_init_f(void)
/*
* Setup the interrupt controller polarities, triggers, etc.
*/
mtdcr(uic0sr, 0xffffffff); /* clear all */
mtdcr(uic0er, 0x00000000); /* disable all */
mtdcr(uic0cr, 0x00000005); /* ATI & UIC1 crit are critical */
mtdcr(uic0pr, 0xfffff7ff); /* per ref-board manual */
mtdcr(uic0tr, 0x00000000); /* per ref-board manual */
mtdcr(uic0vr, 0x00000000); /* int31 highest, base=0x000 */
mtdcr(uic0sr, 0xffffffff); /* clear all */
mtdcr(uic1sr, 0xffffffff); /* clear all */
mtdcr(uic1er, 0x00000000); /* disable all */
mtdcr(uic1cr, 0x00000000); /* all non-critical */
mtdcr(uic1pr, 0xffffffff); /* per ref-board manual */
mtdcr(uic1tr, 0x00000000); /* per ref-board manual */
mtdcr(uic1vr, 0x00000000); /* int31 highest, base=0x000 */
mtdcr(uic1sr, 0xffffffff); /* clear all */
mtdcr(uic2sr, 0xffffffff); /* clear all */
mtdcr(uic2er, 0x00000000); /* disable all */
mtdcr(uic2cr, 0x00000000); /* all non-critical */
mtdcr(uic2pr, 0xffffffff); /* per ref-board manual */
mtdcr(uic2tr, 0x00000000); /* per ref-board manual */
mtdcr(uic2vr, 0x00000000); /* int31 highest, base=0x000 */
mtdcr(uic2sr, 0xffffffff); /* clear all */
mtdcr(UIC0SR, 0xffffffff); /* clear all */
mtdcr(UIC0ER, 0x00000000); /* disable all */
mtdcr(UIC0CR, 0x00000005); /* ATI & UIC1 crit are critical */
mtdcr(UIC0PR, 0xfffff7ff); /* per ref-board manual */
mtdcr(UIC0TR, 0x00000000); /* per ref-board manual */
mtdcr(UIC0VR, 0x00000000); /* int31 highest, base=0x000 */
mtdcr(UIC0SR, 0xffffffff); /* clear all */
mtdcr(UIC1SR, 0xffffffff); /* clear all */
mtdcr(UIC1ER, 0x00000000); /* disable all */
mtdcr(UIC1CR, 0x00000000); /* all non-critical */
mtdcr(UIC1PR, 0xffffffff); /* per ref-board manual */
mtdcr(UIC1TR, 0x00000000); /* per ref-board manual */
mtdcr(UIC1VR, 0x00000000); /* int31 highest, base=0x000 */
mtdcr(UIC1SR, 0xffffffff); /* clear all */
mtdcr(UIC2SR, 0xffffffff); /* clear all */
mtdcr(UIC2ER, 0x00000000); /* disable all */
mtdcr(UIC2CR, 0x00000000); /* all non-critical */
mtdcr(UIC2PR, 0xffffffff); /* per ref-board manual */
mtdcr(UIC2TR, 0x00000000); /* per ref-board manual */
mtdcr(UIC2VR, 0x00000000); /* int31 highest, base=0x000 */
mtdcr(UIC2SR, 0xffffffff); /* clear all */
mtsdr(SDR0_PFC0, 0x00003E00); /* Pin function: */
mtsdr(SDR0_PFC1, 0x00848000); /* Pin function: UART0 has 4 pins */

12
board/netstal/mcu25/mcu25.c
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@ -64,12 +64,12 @@ int board_early_init_f (void)
* IRQ 17-24 RESERVED/UNUSED
* IRQ 31 (EXT IRQ 6) (unused)
*/
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr(uicer, 0x00000000); /* disable all ints */
mtdcr(uiccr, 0x00000000); /* set all to be non-critical */
mtdcr(uicpr, 0xFFFFE000); /* set int polarities */
mtdcr(uictr, 0x00000000); /* set int trigger levels */
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
mtdcr(UIC0ER, 0x00000000); /* disable all ints */
mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical */
mtdcr(UIC0PR, 0xFFFFE000); /* set int polarities */
mtdcr(UIC0TR, 0x00000000); /* set int trigger levels */
mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
mtdcr(CPC0_CR1, CPC0_CR1_VALUE);
mtdcr(CPC0_ECR, 0x60606000);

30
board/pcs440ep/pcs440ep.c
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@ -155,21 +155,21 @@ int board_early_init_f(void)
/*--------------------------------------------------------------------
* Setup the interrupt controller polarities, triggers, etc.
*-------------------------------------------------------------------*/
mtdcr(uic0sr, 0xffffffff); /* clear all */
mtdcr(uic0er, 0x00000000); /* disable all */
mtdcr(uic0cr, 0x00000001); /* UIC1 crit is critical */
mtdcr(uic0pr, 0xfffffe1f); /* per ref-board manual */
mtdcr(uic0tr, 0x01c00000); /* per ref-board manual */
mtdcr(uic0vr, 0x00000001); /* int31 highest, base=0x000 */
mtdcr(uic0sr, 0xffffffff); /* clear all */
mtdcr(uic1sr, 0xffffffff); /* clear all */
mtdcr(uic1er, 0x00000000); /* disable all */
mtdcr(uic1cr, 0x00000000); /* all non-critical */
mtdcr(uic1pr, 0xffffe0ff); /* per ref-board manual */
mtdcr(uic1tr, 0x00ffc000); /* per ref-board manual */
mtdcr(uic1vr, 0x00000001); /* int31 highest, base=0x000 */
mtdcr(uic1sr, 0xffffffff); /* clear all */
mtdcr(UIC0SR, 0xffffffff); /* clear all */
mtdcr(UIC0ER, 0x00000000); /* disable all */
mtdcr(UIC0CR, 0x00000001); /* UIC1 crit is critical */
mtdcr(UIC0PR, 0xfffffe1f); /* per ref-board manual */
mtdcr(UIC0TR, 0x01c00000); /* per ref-board manual */
mtdcr(UIC0VR, 0x00000001); /* int31 highest, base=0x000 */
mtdcr(UIC0SR, 0xffffffff); /* clear all */
mtdcr(UIC1SR, 0xffffffff); /* clear all */
mtdcr(UIC1ER, 0x00000000); /* disable all */
mtdcr(UIC1CR, 0x00000000); /* all non-critical */
mtdcr(UIC1PR, 0xffffe0ff); /* per ref-board manual */
mtdcr(UIC1TR, 0x00ffc000); /* per ref-board manual */
mtdcr(UIC1VR, 0x00000001); /* int31 highest, base=0x000 */
mtdcr(UIC1SR, 0xffffffff); /* clear all */
/*--------------------------------------------------------------------
* Setup other serial configuration

60
board/prodrive/alpr/alpr.c
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@ -60,36 +60,36 @@ int board_early_init_f (void)
* UIC2 UIC1
* UIC3 UIC2
*/
mtdcr (uic1sr, 0xffffffff); /* clear all */
mtdcr (uic1er, 0x00000000); /* disable all */
mtdcr (uic1cr, 0x00000009); /* SMI & UIC1 crit are critical */
mtdcr (uic1pr, 0xfffffe03); /* per manual */
mtdcr (uic1tr, 0x01c00000); /* per manual */
mtdcr (uic1vr, 0x00000001); /* int31 highest, base=0x000 */
mtdcr (uic1sr, 0xffffffff); /* clear all */
mtdcr (uic2sr, 0xffffffff); /* clear all */
mtdcr (uic2er, 0x00000000); /* disable all */
mtdcr (uic2cr, 0x00000000); /* all non-critical */
mtdcr (uic2pr, 0xffffe0ff); /* per ref-board manual */
mtdcr (uic2tr, 0x00ffc000); /* per ref-board manual */
mtdcr (uic2vr, 0x00000001); /* int31 highest, base=0x000 */
mtdcr (uic2sr, 0xffffffff); /* clear all */
mtdcr (uic3sr, 0xffffffff); /* clear all */
mtdcr (uic3er, 0x00000000); /* disable all */
mtdcr (uic3cr, 0x00000000); /* all non-critical */
mtdcr (uic3pr, 0xffffffff); /* per ref-board manual */
mtdcr (uic3tr, 0x00ff8c0f); /* per ref-board manual */
mtdcr (uic3vr, 0x00000001); /* int31 highest, base=0x000 */
mtdcr (uic3sr, 0xffffffff); /* clear all */
mtdcr (uic0sr, 0xfc000000); /* clear all */
mtdcr (uic0er, 0x00000000); /* disable all */
mtdcr (uic0cr, 0x00000000); /* all non-critical */
mtdcr (uic0pr, 0xfc000000); /* */
mtdcr (uic0tr, 0x00000000); /* */
mtdcr (uic0vr, 0x00000001); /* */
mtdcr (UIC1SR, 0xffffffff); /* clear all */
mtdcr (UIC1ER, 0x00000000); /* disable all */
mtdcr (UIC1CR, 0x00000009); /* SMI & UIC1 crit are critical */
mtdcr (UIC1PR, 0xfffffe03); /* per manual */
mtdcr (UIC1TR, 0x01c00000); /* per manual */
mtdcr (UIC1VR, 0x00000001); /* int31 highest, base=0x000 */
mtdcr (UIC1SR, 0xffffffff); /* clear all */
mtdcr (UIC2SR, 0xffffffff); /* clear all */
mtdcr (UIC2ER, 0x00000000); /* disable all */
mtdcr (UIC2CR, 0x00000000); /* all non-critical */
mtdcr (UIC2PR, 0xffffe0ff); /* per ref-board manual */
mtdcr (UIC2TR, 0x00ffc000); /* per ref-board manual */
mtdcr (UIC2VR, 0x00000001); /* int31 highest, base=0x000 */
mtdcr (UIC2SR, 0xffffffff); /* clear all */
mtdcr (UIC3SR, 0xffffffff); /* clear all */
mtdcr (UIC3ER, 0x00000000); /* disable all */
mtdcr (UIC3CR, 0x00000000); /* all non-critical */
mtdcr (UIC3PR, 0xffffffff); /* per ref-board manual */
mtdcr (UIC3TR, 0x00ff8c0f); /* per ref-board manual */
mtdcr (UIC3VR, 0x00000001); /* int31 highest, base=0x000 */
mtdcr (UIC3SR, 0xffffffff); /* clear all */
mtdcr (UIC0SR, 0xfc000000); /* clear all */
mtdcr (UIC0ER, 0x00000000); /* disable all */
mtdcr (UIC0CR, 0x00000000); /* all non-critical */
mtdcr (UIC0PR, 0xfc000000); /* */
mtdcr (UIC0TR, 0x00000000); /* */
mtdcr (UIC0VR, 0x00000001); /* */
/* Setup shutdown/SSD empty interrupt as inputs */
out32(GPIO0_TCR, in32(GPIO0_TCR) & ~(CONFIG_SYS_GPIO_SHUTDOWN | CONFIG_SYS_GPIO_SSD_EMPTY));

30
board/prodrive/p3p440/p3p440.c
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@ -101,21 +101,21 @@ int board_early_init_f(void)
/*--------------------------------------------------------------------
* Setup the interrupt controller polarities, triggers, etc.
*-------------------------------------------------------------------*/
mtdcr(uic0sr, 0xffffffff); /* clear all */
mtdcr(uic0er, 0x00000000); /* disable all */
mtdcr(uic0cr, 0x00000001); /* UIC1 crit is critical */
mtdcr(uic0pr, 0xfffffe13); /* per ref-board manual */
mtdcr(uic0tr, 0x01c00008); /* per ref-board manual */
mtdcr(uic0vr, 0x00000001); /* int31 highest, base=0x000 */
mtdcr(uic0sr, 0xffffffff); /* clear all */
mtdcr(uic1sr, 0xffffffff); /* clear all */
mtdcr(uic1er, 0x00000000); /* disable all */
mtdcr(uic1cr, 0x00000000); /* all non-critical */
mtdcr(uic1pr, 0xffffe0ff); /* per ref-board manual */
mtdcr(uic1tr, 0x00ffc000); /* per ref-board manual */
mtdcr(uic1vr, 0x00000001); /* int31 highest, base=0x000 */
mtdcr(uic1sr, 0xffffffff); /* clear all */
mtdcr(UIC0SR, 0xffffffff); /* clear all */
mtdcr(UIC0ER, 0x00000000); /* disable all */
mtdcr(UIC0CR, 0x00000001); /* UIC1 crit is critical */
mtdcr(UIC0PR, 0xfffffe13); /* per ref-board manual */
mtdcr(UIC0TR, 0x01c00008); /* per ref-board manual */
mtdcr(UIC0VR, 0x00000001); /* int31 highest, base=0x000 */
mtdcr(UIC0SR, 0xffffffff); /* clear all */
mtdcr(UIC1SR, 0xffffffff); /* clear all */
mtdcr(UIC1ER, 0x00000000); /* disable all */
mtdcr(UIC1CR, 0x00000000); /* all non-critical */
mtdcr(UIC1PR, 0xffffe0ff); /* per ref-board manual */
mtdcr(UIC1TR, 0x00ffc000); /* per ref-board manual */
mtdcr(UIC1VR, 0x00000001); /* int31 highest, base=0x000 */
mtdcr(UIC1SR, 0xffffffff); /* clear all */
return 0;
}

14
board/quad100hd/quad100hd.c
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@ -40,13 +40,13 @@ DECLARE_GLOBAL_DATA_PTR;
int board_early_init_f(void)
{
/* taken from PPCBoot */
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr(uicer, 0x00000000); /* disable all ints */
mtdcr(uiccr, 0x00000000);
mtdcr(uicpr, 0xFFFF7FFE); /* set int polarities */
mtdcr(uictr, 0x00000000); /* set int trigger levels */
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */
mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
mtdcr(UIC0ER, 0x00000000); /* disable all ints */
mtdcr(UIC0CR, 0x00000000);
mtdcr(UIC0PR, 0xFFFF7FFE); /* set int polarities */
mtdcr(UIC0TR, 0x00000000); /* set int trigger levels */
mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority */
mtdcr(CPC0_SRR, 0x00040000); /* Hold PCI bridge in reset */

60
board/sandburst/karef/karef.c
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@ -212,36 +212,36 @@ int board_early_init_f (void)
* UIC2 UIC1
* UIC3 UIC2
*/
mtdcr (uic1sr, 0xffffffff); /* clear all */
mtdcr (uic1er, 0x00000000); /* disable all */
mtdcr (uic1cr, 0x00000000); /* all non- critical */
mtdcr (uic1pr, 0xfffffe03); /* polarity */
mtdcr (uic1tr, 0x01c00000); /* trigger edge vs level */
mtdcr (uic1vr, 0x00000001); /* int31 highest, base=0x000 */
mtdcr (uic1sr, 0xffffffff); /* clear all */
mtdcr (uic2sr, 0xffffffff); /* clear all */
mtdcr (uic2er, 0x00000000); /* disable all */
mtdcr (uic2cr, 0x00000000); /* all non-critical */
mtdcr (uic2pr, 0xffffc8ff); /* polarity */
mtdcr (uic2tr, 0x00ff0000); /* trigger edge vs level */
mtdcr (uic2vr, 0x00000001); /* int31 highest, base=0x000 */
mtdcr (uic2sr, 0xffffffff); /* clear all */
mtdcr (uic3sr, 0xffffffff); /* clear all */
mtdcr (uic3er, 0x00000000); /* disable all */
mtdcr (uic3cr, 0x00000000); /* all non-critical */
mtdcr (uic3pr, 0xffff83ff); /* polarity */
mtdcr (uic3tr, 0x00ff8c0f); /* trigger edge vs level */
mtdcr (uic3vr, 0x00000001); /* int31 highest, base=0x000 */
mtdcr (uic3sr, 0xffffffff); /* clear all */
mtdcr (uic0sr, 0xfc000000); /* clear all */
mtdcr (uic0er, 0x00000000); /* disable all */
mtdcr (uic0cr, 0x00000000); /* all non-critical */
mtdcr (uic0pr, 0xfc000000);
mtdcr (uic0tr, 0x00000000);
mtdcr (uic0vr, 0x00000001);
mtdcr (UIC1SR, 0xffffffff); /* clear all */
mtdcr (UIC1ER, 0x00000000); /* disable all */
mtdcr (UIC1CR, 0x00000000); /* all non- critical */
mtdcr (UIC1PR, 0xfffffe03); /* polarity */
mtdcr (UIC1TR, 0x01c00000); /* trigger edge vs level */
mtdcr (UIC1VR, 0x00000001); /* int31 highest, base=0x000 */
mtdcr (UIC1SR, 0xffffffff); /* clear all */
mtdcr (UIC2SR, 0xffffffff); /* clear all */
mtdcr (UIC2ER, 0x00000000); /* disable all */
mtdcr (UIC2CR, 0x00000000); /* all non-critical */
mtdcr (UIC2PR, 0xffffc8ff); /* polarity */
mtdcr (UIC2TR, 0x00ff0000); /* trigger edge vs level */
mtdcr (UIC2VR, 0x00000001); /* int31 highest, base=0x000 */
mtdcr (UIC2SR, 0xffffffff); /* clear all */
mtdcr (UIC3SR, 0xffffffff); /* clear all */
mtdcr (UIC3ER, 0x00000000); /* disable all */
mtdcr (UIC3CR, 0x00000000); /* all non-critical */
mtdcr (UIC3PR, 0xffff83ff); /* polarity */
mtdcr (UIC3TR, 0x00ff8c0f); /* trigger edge vs level */
mtdcr (UIC3VR, 0x00000001); /* int31 highest, base=0x000 */
mtdcr (UIC3SR, 0xffffffff); /* clear all */
mtdcr (UIC0SR, 0xfc000000); /* clear all */
mtdcr (UIC0ER, 0x00000000); /* disable all */
mtdcr (UIC0CR, 0x00000000); /* all non-critical */
mtdcr (UIC0PR, 0xfc000000);
mtdcr (UIC0TR, 0x00000000);
mtdcr (UIC0VR, 0x00000001);
fpga_init();

60
board/sandburst/metrobox/metrobox.c
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@ -202,36 +202,36 @@ int board_early_init_f (void)
* UIC2 UIC1
* UIC3 UIC2
*/
mtdcr (uic1sr, 0xffffffff); /* clear all */
mtdcr (uic1er, 0x00000000); /* disable all */
mtdcr (uic1cr, 0x00000000); /* all non- critical */
mtdcr (uic1pr, 0xfffffe03); /* polarity */
mtdcr (uic1tr, 0x01c00000); /* trigger edge vs level */
mtdcr (uic1vr, 0x00000001); /* int31 highest, base=0x000 */
mtdcr (uic1sr, 0xffffffff); /* clear all */
mtdcr (uic2sr, 0xffffffff); /* clear all */
mtdcr (uic2er, 0x00000000); /* disable all */
mtdcr (uic2cr, 0x00000000); /* all non-critical */
mtdcr (uic2pr, 0xffffc8ff); /* polarity */
mtdcr (uic2tr, 0x00ff0000); /* trigger edge vs level */
mtdcr (uic2vr, 0x00000001); /* int31 highest, base=0x000 */
mtdcr (uic2sr, 0xffffffff); /* clear all */
mtdcr (uic3sr, 0xffffffff); /* clear all */
mtdcr (uic3er, 0x00000000); /* disable all */
mtdcr (uic3cr, 0x00000000); /* all non-critical */
mtdcr (uic3pr, 0xffff83ff); /* polarity */
mtdcr (uic3tr, 0x00ff8c0f); /* trigger edge vs level */
mtdcr (uic3vr, 0x00000001); /* int31 highest, base=0x000 */
mtdcr (uic3sr, 0xffffffff); /* clear all */
mtdcr (uic0sr, 0xfc000000); /* clear all */
mtdcr (uic0er, 0x00000000); /* disable all */
mtdcr (uic0cr, 0x00000000); /* all non-critical */
mtdcr (uic0pr, 0xfc000000);
mtdcr (uic0tr, 0x00000000);
mtdcr (uic0vr, 0x00000001);
mtdcr (UIC1SR, 0xffffffff); /* clear all */
mtdcr (UIC1ER, 0x00000000); /* disable all */
mtdcr (UIC1CR, 0x00000000); /* all non- critical */
mtdcr (UIC1PR, 0xfffffe03); /* polarity */
mtdcr (UIC1TR, 0x01c00000); /* trigger edge vs level */
mtdcr (UIC1VR, 0x00000001); /* int31 highest, base=0x000 */
mtdcr (UIC1SR, 0xffffffff); /* clear all */
mtdcr (UIC2SR, 0xffffffff); /* clear all */
mtdcr (UIC2ER, 0x00000000); /* disable all */
mtdcr (UIC2CR, 0x00000000); /* all non-critical */
mtdcr (UIC2PR, 0xffffc8ff); /* polarity */
mtdcr (UIC2TR, 0x00ff0000); /* trigger edge vs level */
mtdcr (UIC2VR, 0x00000001); /* int31 highest, base=0x000 */
mtdcr (UIC2SR, 0xffffffff); /* clear all */
mtdcr (UIC3SR, 0xffffffff); /* clear all */
mtdcr (UIC3ER, 0x00000000); /* disable all */
mtdcr (UIC3CR, 0x00000000); /* all non-critical */
mtdcr (UIC3PR, 0xffff83ff); /* polarity */
mtdcr (UIC3TR, 0x00ff8c0f); /* trigger edge vs level */
mtdcr (UIC3VR, 0x00000001); /* int31 highest, base=0x000 */
mtdcr (UIC3SR, 0xffffffff); /* clear all */
mtdcr (UIC0SR, 0xfc000000); /* clear all */
mtdcr (UIC0ER, 0x00000000); /* disable all */
mtdcr (UIC0CR, 0x00000000); /* all non-critical */
mtdcr (UIC0PR, 0xfc000000);
mtdcr (UIC0TR, 0x00000000);
mtdcr (UIC0VR, 0x00000001);
fpga_init();

14
board/sbc405/sbc405.c
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@ -41,13 +41,13 @@ int board_early_init_f (void)
* IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
* IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
*/
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr(uicer, 0x00000000); /* disable all ints */
mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/
mtdcr(uicpr, 0xFFFFFF81); /* set int polarities */
mtdcr(uictr, 0x10000000); /* set int trigger levels */
mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
mtdcr(UIC0ER, 0x00000000); /* disable all ints */
mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/
mtdcr(UIC0PR, 0xFFFFFF81); /* set int polarities */
mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */
mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority*/
mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
/*
* EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us

18
board/sc3/sc3.c
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@ -294,22 +294,22 @@ int board_early_init_f (void)
writeb (cpldConfig_1, CPLD_CONTROL_1); /* disable everything in CPLD */
mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr (uicer, 0x00000000); /* disable all ints */
mtdcr (uiccr, 0x00000000); /* set all to be non-critical */
mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
mtdcr (UIC0ER, 0x00000000); /* disable all ints */
mtdcr (UIC0CR, 0x00000000); /* set all to be non-critical */
if (IS_CAMERON) {
sc3_cameron_init();
mtdcr (0x0B6, 0x18000000);
mtdcr (uicpr, 0xFFFFFFF0);
mtdcr (uictr, 0x10001030);
mtdcr (UIC0PR, 0xFFFFFFF0);
mtdcr (UIC0TR, 0x10001030);
} else {
mtdcr (0x0B6, 0x0000000);
mtdcr (uicpr, 0xFFFFFFE0);
mtdcr (uictr, 0x10000020);
mtdcr (UIC0PR, 0xFFFFFFE0);
mtdcr (UIC0TR, 0x10000020);
}
mtdcr (uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */
mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr (UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority */
mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
/* setup other implementation specific details */
mtdcr (CPC0_ECR, 0x60606000);

28
board/w7o/w7o.c
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@ -64,16 +64,16 @@ int board_early_init_f (void)
* IRQ 30 (EXT IRQ 5) Level One PHY; active low; level sensitive
* IRQ 31 (EXT IRQ 6) SAM 1; active high; level sensitive
*/
mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr (uicer, 0x00000000); /* disable all ints */
mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
mtdcr (UIC0ER, 0x00000000); /* disable all ints */
mtdcr (uiccr, 0x00000000); /* set all to be non-critical */
mtdcr (uicpr, 0xFFFFFF80); /* set int polarities */
mtdcr (uictr, 0x10000000); /* set int trigger levels */
mtdcr (uicvcr, 0x00000001); /* set vect base=0,
mtdcr (UIC0CR, 0x00000000); /* set all to be non-critical */
mtdcr (UIC0PR, 0xFFFFFF80); /* set int polarities */
mtdcr (UIC0TR, 0x10000000); /* set int trigger levels */
mtdcr (UIC0VCR, 0x00000001); /* set vect base=0,
INT0 highest priority */
mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
#elif defined(CONFIG_W7OLMC)
/*
@ -95,16 +95,16 @@ int board_early_init_f (void)
* IRQ 30 (EXT IRQ 5) RCMM Reset; active low; level sensitive
* IRQ 31 (EXT IRQ 6) PHY; active high; level sensitive
*/
mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr (uicer, 0x00000000); /* disable all ints */
mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
mtdcr (UIC0ER, 0x00000000); /* disable all ints */
mtdcr (uiccr, 0x00000000); /* set all to be non-critical */
mtdcr (uicpr, 0xFFFFFF80); /* set int polarities */
mtdcr (uictr, 0x10000000); /* set int trigger levels */
mtdcr (uicvcr, 0x00000001); /* set vect base=0,
mtdcr (UIC0CR, 0x00000000); /* set all to be non-critical */
mtdcr (UIC0PR, 0xFFFFFF80); /* set int polarities */
mtdcr (UIC0TR, 0x10000000); /* set int trigger levels */
mtdcr (UIC0VCR, 0x00000001); /* set vect base=0,
INT0 highest priority */
mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
#else /* Unknown */
# error "Unknown W7O board configuration"

60
board/xes/xpedite1000/xpedite1000.c
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@ -74,36 +74,36 @@ int board_early_init_f(void)
* UIC2 UIC1
* UIC3 UIC2
*/
mtdcr(uic1sr, 0xffffffff); /* clear all */
mtdcr(uic1er, 0x00000000); /* disable all */
mtdcr(uic1cr, 0x00000003); /* SMI & UIC1 crit are critical */
mtdcr(uic1pr, 0xfffffe00); /* per ref-board manual */
mtdcr(uic1tr, 0x01c00000); /* per ref-board manual */
mtdcr(uic1vr, 0x00000001); /* int31 highest, base=0x000 */
mtdcr(uic1sr, 0xffffffff); /* clear all */
mtdcr(uic2sr, 0xffffffff); /* clear all */
mtdcr(uic2er, 0x00000000); /* disable all */
mtdcr(uic2cr, 0x00000000); /* all non-critical */
mtdcr(uic2pr, 0xffffc0ff); /* per ref-board manual */
mtdcr(uic2tr, 0x00ff8000); /* per ref-board manual */
mtdcr(uic2vr, 0x00000001); /* int31 highest, base=0x000 */
mtdcr(uic2sr, 0xffffffff); /* clear all */
mtdcr(uic3sr, 0xffffffff); /* clear all */
mtdcr(uic3er, 0x00000000); /* disable all */
mtdcr(uic3cr, 0x00000000); /* all non-critical */
mtdcr(uic3pr, 0xffffffff); /* per ref-board manual */
mtdcr(uic3tr, 0x00ff8c0f); /* per ref-board manual */
mtdcr(uic3vr, 0x00000001); /* int31 highest, base=0x000 */
mtdcr(uic3sr, 0xffffffff); /* clear all */
mtdcr(uic0sr, 0xfc000000); /* clear all */
mtdcr(uic0er, 0x00000000); /* disable all */
mtdcr(uic0cr, 0x00000000); /* all non-critical */
mtdcr(uic0pr, 0xfc000000); /* */
mtdcr(uic0tr, 0x00000000); /* */
mtdcr(uic0vr, 0x00000001); /* */
mtdcr(UIC1SR, 0xffffffff); /* clear all */
mtdcr(UIC1ER, 0x00000000); /* disable all */
mtdcr(UIC1CR, 0x00000003); /* SMI & UIC1 crit are critical */
mtdcr(UIC1PR, 0xfffffe00); /* per ref-board manual */
mtdcr(UIC1TR, 0x01c00000); /* per ref-board manual */
mtdcr(UIC1VR, 0x00000001); /* int31 highest, base=0x000 */
mtdcr(UIC1SR, 0xffffffff); /* clear all */
mtdcr(UIC2SR, 0xffffffff); /* clear all */
mtdcr(UIC2ER, 0x00000000); /* disable all */
mtdcr(UIC2CR, 0x00000000); /* all non-critical */
mtdcr(UIC2PR, 0xffffc0ff); /* per ref-board manual */
mtdcr(UIC2TR, 0x00ff8000); /* per ref-board manual */
mtdcr(UIC2VR, 0x00000001); /* int31 highest, base=0x000 */
mtdcr(UIC2SR, 0xffffffff); /* clear all */
mtdcr(UIC3SR, 0xffffffff); /* clear all */
mtdcr(UIC3ER, 0x00000000); /* disable all */
mtdcr(UIC3CR, 0x00000000); /* all non-critical */
mtdcr(UIC3PR, 0xffffffff); /* per ref-board manual */
mtdcr(UIC3TR, 0x00ff8c0f); /* per ref-board manual */
mtdcr(UIC3VR, 0x00000001); /* int31 highest, base=0x000 */
mtdcr(UIC3SR, 0xffffffff); /* clear all */
mtdcr(UIC0SR, 0xfc000000); /* clear all */
mtdcr(UIC0ER, 0x00000000); /* disable all */
mtdcr(UIC0CR, 0x00000000); /* all non-critical */
mtdcr(UIC0PR, 0xfc000000); /* */
mtdcr(UIC0TR, 0x00000000); /* */
mtdcr(UIC0VR, 0x00000001); /* */
LED0_ON();

14
board/zeus/zeus.c
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@ -50,13 +50,13 @@ static u32 start_time;
int board_early_init_f(void)
{
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr(uicer, 0x00000000); /* disable all ints */
mtdcr(uiccr, 0x00000000);
mtdcr(uicpr, 0xFFFF7F00); /* set int polarities */
mtdcr(uictr, 0x00000000); /* set int trigger levels */
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */
mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
mtdcr(UIC0ER, 0x00000000); /* disable all ints */
mtdcr(UIC0CR, 0x00000000);
mtdcr(UIC0PR, 0xFFFF7F00); /* set int polarities */
mtdcr(UIC0TR, 0x00000000); /* set int trigger levels */
mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority */
/*
* Configure CPC0_PCI to enable PerWE as output

36
common/cmd_reginfo.c
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@ -93,17 +93,17 @@ int do_reginfo (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
#elif defined (CONFIG_405GP)
printf ("\n405GP registers; MSR=%08x\n",mfmsr());
printf ("\nUniversal Interrupt Controller Regs\n"
"uicsr uicer uiccr uicpr uictr uicmsr uicvr uicvcr"
"UIC0SR UIC0ER UIC0CR UIC0PR UIC0TR UIC0MSR UIC0VR UIC0VCR"
"\n"
"%08x %08x %08x %08x %08x %08x %08x %08x\n",
mfdcr(uicsr),
mfdcr(uicer),
mfdcr(uiccr),
mfdcr(uicpr),
mfdcr(uictr),
mfdcr(uicmsr),
mfdcr(uicvr),
mfdcr(uicvcr));
mfdcr(UIC0SR),
mfdcr(UIC0ER),
mfdcr(UIC0CR),
mfdcr(UIC0PR),
mfdcr(UIC0TR),
mfdcr(UIC0MSR),
mfdcr(UIC0VR),
mfdcr(UIC0VCR));
puts ("\nMemory (SDRAM) Configuration\n"
"besra besrsa besrb besrsb bear mcopt1 rtr pmit\n");
@ -180,17 +180,17 @@ int do_reginfo (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
#elif defined(CONFIG_405EP)
printf ("\n405EP registers; MSR=%08x\n",mfmsr());
printf ("\nUniversal Interrupt Controller Regs\n"
"uicsr uicer uiccr uicpr uictr uicmsr uicvr uicvcr"
"UIC0SR UIC0ER UIC0CR UIC0PR UIC0TR UIC0MSR UIC0VR UIC0VCR"
"\n"
"%08x %08x %08x %08x %08x %08x %08x %08x\n",
mfdcr(uicsr),
mfdcr(uicer),
mfdcr(uiccr),
mfdcr(uicpr),
mfdcr(uictr),
mfdcr(uicmsr),
mfdcr(uicvr),
mfdcr(uicvcr));
mfdcr(UIC0SR),
mfdcr(UIC0ER),
mfdcr(UIC0CR),
mfdcr(UIC0PR),
mfdcr(UIC0TR),
mfdcr(UIC0MSR),
mfdcr(UIC0VR),
mfdcr(UIC0VCR));
puts ("\nMemory (SDRAM) Configuration\n"
"mcopt1 rtr pmit mb0cf mb1cf sdtr1\n");

28
cpu/ppc4xx/uic.c
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@ -109,7 +109,7 @@ void external_interrupt(struct pt_regs *regs)
/*
* Read masked interrupt status register to determine interrupt source
*/
uic_msr = mfdcr(uic0msr);
uic_msr = mfdcr(UIC0MSR);
#if (UIC_MAX > 1)
if ((UIC_MASK(VECNUM_UIC1CI) & uic_msr) ||
@ -129,7 +129,7 @@ void external_interrupt(struct pt_regs *regs)
uic_interrupt(UIC3_DCR_BASE, 96);
#endif
mtdcr(uic0sr, (uic_msr & UICB0_ALL));
mtdcr(UIC0SR, (uic_msr & UICB0_ALL));
if (uic_msr & ~(UICB0_ALL))
uic_interrupt(UIC0_DCR_BASE, 0);
@ -140,13 +140,13 @@ void external_interrupt(struct pt_regs *regs)
void pic_irq_ack(unsigned int vec)
{
if ((vec >= 0) && (vec < 32))
mtdcr(uicsr, UIC_MASK(vec));
mtdcr(UIC0SR, UIC_MASK(vec));
else if ((vec >= 32) && (vec < 64))
mtdcr(uic1sr, UIC_MASK(vec));
mtdcr(UIC1SR, UIC_MASK(vec));
else if ((vec >= 64) && (vec < 96))
mtdcr(uic2sr, UIC_MASK(vec));
mtdcr(UIC2SR, UIC_MASK(vec));
else if (vec >= 96)
mtdcr(uic3sr, UIC_MASK(vec));
mtdcr(UIC3SR, UIC_MASK(vec));
}
/*
@ -156,13 +156,13 @@ void pic_irq_enable(unsigned int vec)
{
if ((vec >= 0) && (vec < 32))
mtdcr(uicer, mfdcr(uicer) | UIC_MASK(vec));
mtdcr(UIC0ER, mfdcr(UIC0ER) | UIC_MASK(vec));
else if ((vec >= 32) && (vec < 64))
mtdcr(uic1er, mfdcr(uic1er) | UIC_MASK(vec));
mtdcr(UIC1ER, mfdcr(UIC1ER) | UIC_MASK(vec));
else if ((vec >= 64) && (vec < 96))
mtdcr(uic2er, mfdcr(uic2er) | UIC_MASK(vec));
mtdcr(UIC2ER, mfdcr(UIC2ER) | UIC_MASK(vec));
else if (vec >= 96)
mtdcr(uic3er, mfdcr(uic3er) | UIC_MASK(vec));
mtdcr(UIC3ER, mfdcr(UIC3ER) | UIC_MASK(vec));
debug("Install interrupt vector %d\n", vec);
}
@ -170,11 +170,11 @@ void pic_irq_enable(unsigned int vec)
void pic_irq_disable(unsigned int vec)
{
if ((vec >= 0) && (vec < 32))
mtdcr(uicer, mfdcr(uicer) & ~UIC_MASK(vec));
mtdcr(UIC0ER, mfdcr(UIC0ER) & ~UIC_MASK(vec));
else if ((vec >= 32) && (vec < 64))
mtdcr(uic1er, mfdcr(uic1er) & ~UIC_MASK(vec));
mtdcr(UIC1ER, mfdcr(UIC1ER) & ~UIC_MASK(vec));
else if ((vec >= 64) && (vec < 96))
mtdcr(uic2er, mfdcr(uic2er) & ~UIC_MASK(vec));
mtdcr(UIC2ER, mfdcr(UIC2ER) & ~UIC_MASK(vec));
else if (vec >= 96)
mtdcr(uic3er, mfdcr(uic3er) & ~UIC_MASK(vec));
mtdcr(UIC3ER, mfdcr(UIC3ER) & ~UIC_MASK(vec));
}

86
include/asm-ppc/ppc4xx-uic.h
Unescape View File

@ -1,7 +1,7 @@
/*
* Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com>
*
* (C) Copyright 2008
* (C) Copyright 2008-2009
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* See file CREDITS for list of people who contributed to this
@ -43,7 +43,7 @@
#define UIC_MAX 1
#endif
#define IRQ_MAX UIC_MAX * 32
#define IRQ_MAX (UIC_MAX * 32)
/*
* UIC register
@ -74,53 +74,41 @@
#define UIC3_DCR_BASE 0xf0
#endif
#define uic0sr (UIC0_DCR_BASE+0x0) /* UIC0 status */
#define uic0er (UIC0_DCR_BASE+0x2) /* UIC0 enable */
#define uic0cr (UIC0_DCR_BASE+0x3) /* UIC0 critical */
#define uic0pr (UIC0_DCR_BASE+0x4) /* UIC0 polarity */
#define uic0tr (UIC0_DCR_BASE+0x5) /* UIC0 triggering */
#define uic0msr (UIC0_DCR_BASE+0x6) /* UIC0 masked status */
#define uic0vr (UIC0_DCR_BASE+0x7) /* UIC0 vector */
#define uic0vcr (UIC0_DCR_BASE+0x8) /* UIC0 vector configuration */
#define uic1sr (UIC1_DCR_BASE+0x0) /* UIC1 status */
#define uic1er (UIC1_DCR_BASE+0x2) /* UIC1 enable */
#define uic1cr (UIC1_DCR_BASE+0x3) /* UIC1 critical */
#define uic1pr (UIC1_DCR_BASE+0x4) /* UIC1 polarity */
#define uic1tr (UIC1_DCR_BASE+0x5) /* UIC1 triggering */
#define uic1msr (UIC1_DCR_BASE+0x6) /* UIC1 masked status */
#define uic1vr (UIC1_DCR_BASE+0x7) /* UIC1 vector */
#define uic1vcr (UIC1_DCR_BASE+0x8) /* UIC1 vector configuration */
#define uic2sr (UIC2_DCR_BASE+0x0) /* UIC2 status-Read Clear */
#define uic2srs (UIC2_DCR_BASE+0x1) /* UIC2 status-Read Set */
#define uic2er (UIC2_DCR_BASE+0x2) /* UIC2 enable */
#define uic2cr (UIC2_DCR_BASE+0x3) /* UIC2 critical */
#define uic2pr (UIC2_DCR_BASE+0x4) /* UIC2 polarity */
#define uic2tr (UIC2_DCR_BASE+0x5) /* UIC2 triggering */
#define uic2msr (UIC2_DCR_BASE+0x6) /* UIC2 masked status */
#define uic2vr (UIC2_DCR_BASE+0x7) /* UIC2 vector */
#define uic2vcr (UIC2_DCR_BASE+0x8) /* UIC2 vector configuration */
#define uic3sr (UIC3_DCR_BASE+0x0) /* UIC3 status-Read Clear */
#define uic3srs (UIC3_DCR_BASE+0x1) /* UIC3 status-Read Set */
#define uic3er (UIC3_DCR_BASE+0x2) /* UIC3 enable */
#define uic3cr (UIC3_DCR_BASE+0x3) /* UIC3 critical */
#define uic3pr (UIC3_DCR_BASE+0x4) /* UIC3 polarity */
#define uic3tr (UIC3_DCR_BASE+0x5) /* UIC3 triggering */
#define uic3msr (UIC3_DCR_BASE+0x6) /* UIC3 masked status */
#define uic3vr (UIC3_DCR_BASE+0x7) /* UIC3 vector */
#define uic3vcr (UIC3_DCR_BASE+0x8) /* UIC3 vector configuration */
/* The following is for compatibility with 405 code */
#define uicsr uic0sr
#define uicer uic0er
#define uiccr uic0cr
#define uicpr uic0pr
#define uictr uic0tr
#define uicmsr uic0msr
#define uicvr uic0vr
#define uicvcr uic0vcr
#define UIC0SR (UIC0_DCR_BASE+0x0) /* UIC0 status */
#define UIC0ER (UIC0_DCR_BASE+0x2) /* UIC0 enable */
#define UIC0CR (UIC0_DCR_BASE+0x3) /* UIC0 critical */
#define UIC0PR (UIC0_DCR_BASE+0x4) /* UIC0 polarity */
#define UIC0TR (UIC0_DCR_BASE+0x5) /* UIC0 triggering */
#define UIC0MSR (UIC0_DCR_BASE+0x6) /* UIC0 masked status */
#define UIC0VR (UIC0_DCR_BASE+0x7) /* UIC0 vector */
#define UIC0VCR (UIC0_DCR_BASE+0x8) /* UIC0 vector configuration */
#define UIC1SR (UIC1_DCR_BASE+0x0) /* UIC1 status */
#define UIC1ER (UIC1_DCR_BASE+0x2) /* UIC1 enable */
#define UIC1CR (UIC1_DCR_BASE+0x3) /* UIC1 critical */
#define UIC1PR (UIC1_DCR_BASE+0x4) /* UIC1 polarity */
#define UIC1TR (UIC1_DCR_BASE+0x5) /* UIC1 triggering */
#define UIC1MSR (UIC1_DCR_BASE+0x6) /* UIC1 masked status */
#define UIC1VR (UIC1_DCR_BASE+0x7) /* UIC1 vector */
#define UIC1VCR (UIC1_DCR_BASE+0x8) /* UIC1 vector configuration */
#define UIC2SR (UIC2_DCR_BASE+0x0) /* UIC2 status-Read Clear */
#define UIC2ER (UIC2_DCR_BASE+0x2) /* UIC2 enable */
#define UIC2CR (UIC2_DCR_BASE+0x3) /* UIC2 critical */
#define UIC2PR (UIC2_DCR_BASE+0x4) /* UIC2 polarity */
#define UIC2TR (UIC2_DCR_BASE+0x5) /* UIC2 triggering */
#define UIC2MSR (UIC2_DCR_BASE+0x6) /* UIC2 masked status */
#define UIC2VR (UIC2_DCR_BASE+0x7) /* UIC2 vector */
#define UIC2VCR (UIC2_DCR_BASE+0x8) /* UIC2 vector configuration */
#define UIC3SR (UIC3_DCR_BASE+0x0) /* UIC3 status-Read Clear */
#define UIC3ER (UIC3_DCR_BASE+0x2) /* UIC3 enable */
#define UIC3CR (UIC3_DCR_BASE+0x3) /* UIC3 critical */
#define UIC3PR (UIC3_DCR_BASE+0x4) /* UIC3 polarity */
#define UIC3TR (UIC3_DCR_BASE+0x5) /* UIC3 triggering */
#define UIC3MSR (UIC3_DCR_BASE+0x6) /* UIC3 masked status */
#define UIC3VR (UIC3_DCR_BASE+0x7) /* UIC3 vector */
#define UIC3VCR (UIC3_DCR_BASE+0x8) /* UIC3 vector configuration */
/*
* Now the interrupt vector definitions. They are different for most of

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