Last user of this option went away in commit:
fdc7718999
("board: usb_a9263: Update to support DT and DM")
Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi>
Acked-by: Wenyou Yang <wenyou.yang@microchip.com>
master
parent
7b7341d7f3
commit
95688de311
@ -1,184 +0,0 @@ |
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/*
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* Driver for ATMEL DataFlash support |
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* Author : Hamid Ikdoumi (Atmel) |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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/*
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* This driver desperately needs rework: |
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* |
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* - use structure SoC access |
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* - get rid of including asm/arch/at91_spi.h |
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* - remove asm/arch/at91_spi.h |
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* - get rid of all CONFIG_ATMEL_LEGACY defines and uses |
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* |
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* 02-Aug-2010 Reinhard Meyer <uboot@emk-elektronik.de> |
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*/ |
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#include <common.h> |
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#ifndef CONFIG_ATMEL_LEGACY |
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# define CONFIG_ATMEL_LEGACY |
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#endif |
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#include <spi.h> |
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#include <malloc.h> |
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#include <asm/io.h> |
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#include <asm/arch/clk.h> |
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#include <asm/arch/hardware.h> |
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#include "atmel_spi.h" |
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#include <asm/arch/gpio.h> |
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#include <asm/arch/at91_pio.h> |
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#include <asm/arch/at91_spi.h> |
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#include <dataflash.h> |
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#define AT91_SPI_PCS0_DATAFLASH_CARD 0xE /* Chip Select 0: NPCS0%1110 */ |
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#define AT91_SPI_PCS1_DATAFLASH_CARD 0xD /* Chip Select 1: NPCS1%1101 */ |
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#define AT91_SPI_PCS2_DATAFLASH_CARD 0xB /* Chip Select 2: NPCS2%1011 */ |
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#define AT91_SPI_PCS3_DATAFLASH_CARD 0x7 /* Chip Select 3: NPCS3%0111 */ |
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void AT91F_SpiInit(void) |
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{ |
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/* Reset the SPI */ |
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writel(AT91_SPI_SWRST, ATMEL_BASE_SPI0 + AT91_SPI_CR); |
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/* Configure SPI in Master Mode with No CS selected !!! */ |
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writel(AT91_SPI_MSTR | AT91_SPI_MODFDIS | AT91_SPI_PCS, |
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ATMEL_BASE_SPI0 + AT91_SPI_MR); |
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/* Configure CS0 */ |
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writel(AT91_SPI_NCPHA | |
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(AT91_SPI_DLYBS & DATAFLASH_TCSS) | |
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(AT91_SPI_DLYBCT & DATAFLASH_TCHS) | |
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((get_mck_clk_rate() / AT91_SPI_CLK) << 8), |
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ATMEL_BASE_SPI0 + AT91_SPI_CSR(0)); |
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#ifdef CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS1 |
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/* Configure CS1 */ |
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writel(AT91_SPI_NCPHA | |
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(AT91_SPI_DLYBS & DATAFLASH_TCSS) | |
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(AT91_SPI_DLYBCT & DATAFLASH_TCHS) | |
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((get_mck_clk_rate() / AT91_SPI_CLK) << 8), |
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ATMEL_BASE_SPI0 + AT91_SPI_CSR(1)); |
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#endif |
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#ifdef CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS2 |
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/* Configure CS2 */ |
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writel(AT91_SPI_NCPHA | |
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(AT91_SPI_DLYBS & DATAFLASH_TCSS) | |
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(AT91_SPI_DLYBCT & DATAFLASH_TCHS) | |
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((get_mck_clk_rate() / AT91_SPI_CLK) << 8), |
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ATMEL_BASE_SPI0 + AT91_SPI_CSR(2)); |
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#endif |
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#ifdef CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS3 |
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/* Configure CS3 */ |
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writel(AT91_SPI_NCPHA | |
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(AT91_SPI_DLYBS & DATAFLASH_TCSS) | |
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(AT91_SPI_DLYBCT & DATAFLASH_TCHS) | |
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((get_mck_clk_rate() / AT91_SPI_CLK) << 8), |
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ATMEL_BASE_SPI0 + AT91_SPI_CSR(3)); |
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#endif |
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/* SPI_Enable */ |
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writel(AT91_SPI_SPIEN, ATMEL_BASE_SPI0 + AT91_SPI_CR); |
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while (!(readl(ATMEL_BASE_SPI0 + AT91_SPI_SR) & AT91_SPI_SPIENS)) |
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; |
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/*
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* Add tempo to get SPI in a safe state. |
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* Should not be needed for new silicon (Rev B) |
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*/ |
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udelay(500000); |
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readl(ATMEL_BASE_SPI0 + AT91_SPI_SR); |
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readl(ATMEL_BASE_SPI0 + AT91_SPI_RDR); |
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} |
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void AT91F_SpiEnable(int cs) |
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{ |
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unsigned long mode; |
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mode = readl(ATMEL_BASE_SPI0 + AT91_SPI_MR); |
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mode &= ~AT91_SPI_PCS; |
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switch (cs) { |
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case 0: |
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mode |= AT91_SPI_PCS0_DATAFLASH_CARD << 16; |
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break; |
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case 1: |
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mode |= AT91_SPI_PCS1_DATAFLASH_CARD << 16; |
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break; |
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case 2: |
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mode |= AT91_SPI_PCS2_DATAFLASH_CARD << 16; |
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break; |
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case 3: |
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mode |= AT91_SPI_PCS3_DATAFLASH_CARD << 16; |
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break; |
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} |
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writel(mode, ATMEL_BASE_SPI0 + AT91_SPI_MR); |
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/* SPI_Enable */ |
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writel(AT91_SPI_SPIEN, ATMEL_BASE_SPI0 + AT91_SPI_CR); |
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} |
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unsigned int AT91F_SpiWrite1(AT91PS_DataflashDesc pDesc); |
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unsigned int AT91F_SpiWrite(AT91PS_DataflashDesc pDesc) |
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{ |
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unsigned int timeout; |
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unsigned int timebase; |
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pDesc->state = BUSY; |
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writel(AT91_SPI_TXTDIS + AT91_SPI_RXTDIS, |
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ATMEL_BASE_SPI0 + AT91_SPI_PTCR); |
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/* Initialize the Transmit and Receive Pointer */ |
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writel((unsigned int)pDesc->rx_cmd_pt, |
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ATMEL_BASE_SPI0 + AT91_SPI_RPR); |
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writel((unsigned int)pDesc->tx_cmd_pt, |
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ATMEL_BASE_SPI0 + AT91_SPI_TPR); |
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/* Intialize the Transmit and Receive Counters */ |
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writel(pDesc->rx_cmd_size, ATMEL_BASE_SPI0 + AT91_SPI_RCR); |
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writel(pDesc->tx_cmd_size, ATMEL_BASE_SPI0 + AT91_SPI_TCR); |
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if (pDesc->tx_data_size != 0) { |
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/* Initialize the Next Transmit and Next Receive Pointer */ |
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writel((unsigned int)pDesc->rx_data_pt, |
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ATMEL_BASE_SPI0 + AT91_SPI_RNPR); |
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writel((unsigned int)pDesc->tx_data_pt, |
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ATMEL_BASE_SPI0 + AT91_SPI_TNPR); |
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/* Intialize the Next Transmit and Next Receive Counters */ |
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writel(pDesc->rx_data_size, |
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ATMEL_BASE_SPI0 + AT91_SPI_RNCR); |
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writel(pDesc->tx_data_size, |
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ATMEL_BASE_SPI0 + AT91_SPI_TNCR); |
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} |
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/* arm simple, non interrupt dependent timer */ |
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timebase = get_timer(0); |
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timeout = 0; |
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writel(AT91_SPI_TXTEN + AT91_SPI_RXTEN, |
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ATMEL_BASE_SPI0 + AT91_SPI_PTCR); |
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while (!(readl(ATMEL_BASE_SPI0 + AT91_SPI_SR) & AT91_SPI_RXBUFF) && |
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((timeout = get_timer(timebase)) < CONFIG_SYS_SPI_WRITE_TOUT)) |
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; |
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writel(AT91_SPI_TXTDIS + AT91_SPI_RXTDIS, |
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ATMEL_BASE_SPI0 + AT91_SPI_PTCR); |
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pDesc->state = IDLE; |
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if (timeout >= CONFIG_SYS_SPI_WRITE_TOUT) { |
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printf("Error Timeout\n\r"); |
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return DATAFLASH_ERROR; |
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} |
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return DATAFLASH_OK; |
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} |
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