mpc83xx: cosmetic: MPC832XEMDS.h checkpatch compliance

Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>

include/configs/MPC832XEMDS.h

@@ -151,9 +151,10 @@
  * Initial RAM Base Address Setup
  */
 #define CONFIG_SYS_INIT_RAM_LOCK	1
-#define CONFIG_SYS_INIT_RAM_ADDR	0xE6000000	/* Initial RAM address */
+#define CONFIG_SYS_INIT_RAM_ADDR	0xE6000000	/* Initial RAM addr */
 #define CONFIG_SYS_INIT_RAM_SIZE	0x1000	/* Size of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET	\
+			(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 
 /*
  * Local Bus Configuration & Clock Setup
@@ -171,12 +172,13 @@
 #define CONFIG_SYS_FLASH_SIZE	16	/* FLASH size is 16M */
 #define CONFIG_SYS_FLASH_PROTECTION	1	/* Use h/w Flash protection. */
 
-#define CONFIG_SYS_LBLAWBAR0_PRELIM	CONFIG_SYS_FLASH_BASE	/* Window base at flash base */
+					/* Window base at flash base */
+#define CONFIG_SYS_LBLAWBAR0_PRELIM	CONFIG_SYS_FLASH_BASE
 #define CONFIG_SYS_LBLAWAR0_PRELIM	0x80000018	/* 32MB window size */
 
-#define CONFIG_SYS_BR0_PRELIM	(CONFIG_SYS_FLASH_BASE |	/* Flash Base address */ \
+#define CONFIG_SYS_BR0_PRELIM	(CONFIG_SYS_FLASH_BASE \
-			(2 << BR_PS_SHIFT) |	/* 16 bit port size */ \
+				| (2 << BR_PS_SHIFT)	/* 16 bit port */ \
-			BR_V)			/* valid */
+				| BR_V)			/* valid */
 #define CONFIG_SYS_OR0_PRELIM	0xfe006ff7		/* 16MB Flash size */
 
 #define CONFIG_SYS_MAX_FLASH_BANKS	1	/* number of banks */
@@ -188,10 +190,13 @@
  * BCSR on the Local Bus
  */
 #define CONFIG_SYS_BCSR			0xF8000000
-#define CONFIG_SYS_LBLAWBAR1_PRELIM	CONFIG_SYS_BCSR	/* Access window base at BCSR base */
+					/* Access window base at BCSR base */
-#define CONFIG_SYS_LBLAWAR1_PRELIM	0x8000000E	/* Access window size 32K */
+#define CONFIG_SYS_LBLAWBAR1_PRELIM	CONFIG_SYS_BCSR
+					/* Access window size 32K */
+#define CONFIG_SYS_LBLAWAR1_PRELIM	0x8000000E
 
-#define CONFIG_SYS_BR1_PRELIM		(CONFIG_SYS_BCSR|0x00000801)	/* Port size=8bit, MSEL=GPCM */
+					/* Port size=8bit, MSEL=GPCM */
+#define CONFIG_SYS_BR1_PRELIM		(CONFIG_SYS_BCSR|0x00000801)
 #define CONFIG_SYS_OR1_PRELIM		0xFFFFE9f7	/* length 32K */
 
 /*
@@ -243,8 +248,10 @@
 
 #define CONFIG_SYS_OR2_PRELIM	0xfc006901
 
-#define CONFIG_SYS_LBC_LSRT	0x32000000	/* LB sdram refresh timer, about 6us */
+				/* LB sdram refresh timer, about 6us */
-#define CONFIG_SYS_LBC_MRTPR	0x20000000	/* LB refresh timer prescal, 266MHz/32 */
+#define CONFIG_SYS_LBC_LSRT	0x32000000
+				/* LB refresh timer prescal, 266MHz/32 */
+#define CONFIG_SYS_LBC_MRTPR	0x20000000
 
 #define CONFIG_SYS_LBC_LSDMR_COMMON	0x0063b723
 
@@ -253,20 +260,26 @@
 /*
  * Windows to access PIB via local bus
  */
-#define CONFIG_SYS_LBLAWBAR3_PRELIM	0xf8008000	/* windows base 0xf8008000 */
+					/* windows base 0xf8008000 */
-#define CONFIG_SYS_LBLAWAR3_PRELIM	0x8000000f	/* windows size 64KB */
+#define CONFIG_SYS_LBLAWBAR3_PRELIM	0xf8008000
+					/* windows size 64KB */
+#define CONFIG_SYS_LBLAWAR3_PRELIM	0x8000000f
 
 /*
  * CS2 on Local Bus, to PIB
  */
-#define CONFIG_SYS_BR2_PRELIM	0xf8008801	/* CS2 base address at 0xf8008000 */
+				/* CS2 base address at 0xf8008000 */
-#define CONFIG_SYS_OR2_PRELIM	0xffffe9f7	/* size 32KB, port size 8bit, GPCM */
+#define CONFIG_SYS_BR2_PRELIM	0xf8008801
+				/* size 32KB, port size 8bit, GPCM */
+#define CONFIG_SYS_OR2_PRELIM	0xffffe9f7
 
 /*
  * CS3 on Local Bus, to PIB
  */
-#define CONFIG_SYS_BR3_PRELIM	0xf8010801	/* CS3 base address at 0xf8010000 */
+				/* CS3 base address at 0xf8010000 */
-#define CONFIG_SYS_OR3_PRELIM	0xffffe9f7	/* size 32KB, port size 8bit, GPCM */
+#define CONFIG_SYS_BR3_PRELIM	0xf8010801
+				/* size 32KB, port size 8bit, GPCM */
+#define CONFIG_SYS_OR3_PRELIM	0xffffe9f7
 
 /*
  * Serial Port
@@ -278,7 +291,7 @@
 #define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
 
 #define CONFIG_SYS_BAUDRATE_TABLE  \
-	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
+		{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
 
 #define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_IMMR+0x4500)
 #define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_IMMR+0x4600)
@@ -376,7 +389,8 @@
  */
 #ifndef CONFIG_SYS_RAMBOOT
 	#define CONFIG_ENV_IS_IN_FLASH	1
-	#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
+	#define CONFIG_ENV_ADDR		\
+			(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
 	#define CONFIG_ENV_SECT_SIZE	0x20000
 	#define CONFIG_ENV_SIZE		0x2000
 #else
@@ -432,9 +446,11 @@
 	#define CONFIG_SYS_CBSIZE	256	/* Console I/O Buffer Size */
 #endif
 
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
+				/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
 #define CONFIG_SYS_MAXARGS	16	/* max number of command args */
-#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
+				/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
 #define CONFIG_SYS_HZ		1000	/* decrementer freq: 1ms ticks */
 
 /*
@@ -442,7 +458,8 @@
  * have to be in the first 256 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CONFIG_SYS_BOOTMAPSZ		(256 << 20)	/* Initial Memory map for Linux */
+					/* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ		(256 << 20)
 
 /*
  * Core HID Setup
@@ -459,30 +476,52 @@
 #define CONFIG_HIGH_BATS	1	/* High BATs supported */
 
 /* DDR: cache cacheable */
-#define CONFIG_SYS_IBAT0L	(CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT0L	(CONFIG_SYS_SDRAM_BASE \
-#define CONFIG_SYS_IBAT0U	(CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+				| BATL_PP_10 \
+				| BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT0U	(CONFIG_SYS_SDRAM_BASE \
+				| BATU_BL_256M \
+				| BATU_VS \
+				| BATU_VP)
 #define CONFIG_SYS_DBAT0L	CONFIG_SYS_IBAT0L
 #define CONFIG_SYS_DBAT0U	CONFIG_SYS_IBAT0U
 
 /* IMMRBAR & PCI IO: cache-inhibit and guarded */
-#define CONFIG_SYS_IBAT1L	(CONFIG_SYS_IMMR | BATL_PP_10 | \
+#define CONFIG_SYS_IBAT1L	(CONFIG_SYS_IMMR \
-			BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+				| BATL_PP_10 \
-#define CONFIG_SYS_IBAT1U	(CONFIG_SYS_IMMR | BATU_BL_4M | BATU_VS | BATU_VP)
+				| BATL_CACHEINHIBIT \
+				| BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT1U	(CONFIG_SYS_IMMR \
+				| BATU_BL_4M \
+				| BATU_VS \
+				| BATU_VP)
 #define CONFIG_SYS_DBAT1L	CONFIG_SYS_IBAT1L
 #define CONFIG_SYS_DBAT1U	CONFIG_SYS_IBAT1U
 
 /* BCSR: cache-inhibit and guarded */
-#define CONFIG_SYS_IBAT2L	(CONFIG_SYS_BCSR | BATL_PP_10 | \
+#define CONFIG_SYS_IBAT2L	(CONFIG_SYS_BCSR \
-			BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+				| BATL_PP_10 \
-#define CONFIG_SYS_IBAT2U	(CONFIG_SYS_BCSR | BATU_BL_128K | BATU_VS | BATU_VP)
+				| BATL_CACHEINHIBIT \
+				| BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT2U	(CONFIG_SYS_BCSR \
+				| BATU_BL_128K \
+				| BATU_VS \
+				| BATU_VP)
 #define CONFIG_SYS_DBAT2L	CONFIG_SYS_IBAT2L
 #define CONFIG_SYS_DBAT2U	CONFIG_SYS_IBAT2U
 
 /* FLASH: icache cacheable, but dcache-inhibit and guarded */
-#define CONFIG_SYS_IBAT3L	(CONFIG_SYS_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT3L	(CONFIG_SYS_FLASH_BASE \
-#define CONFIG_SYS_IBAT3U	(CONFIG_SYS_FLASH_BASE | BATU_BL_32M | BATU_VS | BATU_VP)
+				| BATL_PP_10 \
-#define CONFIG_SYS_DBAT3L	(CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \
+				| BATL_MEMCOHERENCE)
-			BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT3U	(CONFIG_SYS_FLASH_BASE \
+				| BATU_BL_32M \
+				| BATU_VS \
+				| BATU_VP)
+#define CONFIG_SYS_DBAT3L	(CONFIG_SYS_FLASH_BASE \
+				| BATL_PP_10 \
+				| BATL_CACHEINHIBIT \
+				| BATL_GUARDEDSTORAGE)
 #define CONFIG_SYS_DBAT3U	CONFIG_SYS_IBAT3U
 
 #define CONFIG_SYS_IBAT4L	(0)
@@ -492,20 +531,33 @@
 
 /* Stack in dcache: cacheable, no memory coherence */
 #define CONFIG_SYS_IBAT5L	(CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10)
-#define CONFIG_SYS_IBAT5U	(CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT5U	(CONFIG_SYS_INIT_RAM_ADDR \
+				| BATU_BL_128K \
+				| BATU_VS \
+				| BATU_VP)
 #define CONFIG_SYS_DBAT5L	CONFIG_SYS_IBAT5L
 #define CONFIG_SYS_DBAT5U	CONFIG_SYS_IBAT5U
 
 #ifdef CONFIG_PCI
 /* PCI MEM space: cacheable */
-#define CONFIG_SYS_IBAT6L	(CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT6L	(CONFIG_SYS_PCI1_MEM_PHYS \
-#define CONFIG_SYS_IBAT6U	(CONFIG_SYS_PCI1_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
+				| BATL_PP_10 \
+				| BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT6U	(CONFIG_SYS_PCI1_MEM_PHYS \
+				| BATU_BL_256M \
+				| BATU_VS \
+				| BATU_VP)
 #define CONFIG_SYS_DBAT6L	CONFIG_SYS_IBAT6L
 #define CONFIG_SYS_DBAT6U	CONFIG_SYS_IBAT6U
 /* PCI MMIO space: cache-inhibit and guarded */
-#define CONFIG_SYS_IBAT7L	(CONFIG_SYS_PCI1_MMIO_PHYS | BATL_PP_10 | \
+#define CONFIG_SYS_IBAT7L	(CONFIG_SYS_PCI1_MMIO_PHYS \
-			BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+				| BATL_PP_10 \
-#define CONFIG_SYS_IBAT7U	(CONFIG_SYS_PCI1_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
+				| BATL_CACHEINHIBIT \
+				| BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT7U	(CONFIG_SYS_PCI1_MMIO_PHYS \
+				| BATU_BL_256M \
+				| BATU_VS \
+				| BATU_VP)
 #define CONFIG_SYS_DBAT7L	CONFIG_SYS_IBAT7L
 #define CONFIG_SYS_DBAT7U	CONFIG_SYS_IBAT7U
 #else
@@ -552,7 +604,8 @@
 #define CONFIG_NFSBOOTCOMMAND						\
 	"setenv bootargs root=/dev/nfs rw "				\
 		"nfsroot=$serverip:$rootpath "				\
-      "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off "	\
+		"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"	\
+							"$netdev:off "	\
 		"console=$consoledev,$baudrate $othbootargs;"		\
 	"tftp $loadaddr $bootfile;"					\
 	"tftp $fdtaddr $fdtfile;"					\