|
|
@ -290,7 +290,7 @@ |
|
|
|
#define CFG_UEC1_TX_CLK QE_CLK9 |
|
|
|
#define CFG_UEC1_TX_CLK QE_CLK9 |
|
|
|
#define CFG_UEC1_ETH_TYPE GIGA_ETH |
|
|
|
#define CFG_UEC1_ETH_TYPE GIGA_ETH |
|
|
|
#define CFG_UEC1_PHY_ADDR 2 |
|
|
|
#define CFG_UEC1_PHY_ADDR 2 |
|
|
|
#define CFG_UEC1_INTERFACE_MODE ENET_1000_GMII |
|
|
|
#define CFG_UEC1_INTERFACE_MODE ENET_1000_RGMII_RXID |
|
|
|
#endif |
|
|
|
#endif |
|
|
|
|
|
|
|
|
|
|
|
#define CONFIG_UEC_ETH2 /* GETH2 */ |
|
|
|
#define CONFIG_UEC_ETH2 /* GETH2 */ |
|
|
@ -301,7 +301,7 @@ |
|
|
|
#define CFG_UEC2_TX_CLK QE_CLK4 |
|
|
|
#define CFG_UEC2_TX_CLK QE_CLK4 |
|
|
|
#define CFG_UEC2_ETH_TYPE GIGA_ETH |
|
|
|
#define CFG_UEC2_ETH_TYPE GIGA_ETH |
|
|
|
#define CFG_UEC2_PHY_ADDR 4 |
|
|
|
#define CFG_UEC2_PHY_ADDR 4 |
|
|
|
#define CFG_UEC2_INTERFACE_MODE ENET_1000_GMII |
|
|
|
#define CFG_UEC2_INTERFACE_MODE ENET_1000_RGMII_RXID |
|
|
|
#endif |
|
|
|
#endif |
|
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
/*
|
|
|
|