@ -100,26 +100,38 @@ int cpu_mmc_init(bd_t *bis)
}
}
# endif
# endif
# if defined(CONFIG_DISPLAY_CPUINFO)
struct {
const char * const bsel_str [ ] = {
const char * mode ;
" Reserved " ,
const char * name ;
" FPGA (HPS2FPGA Bridge) " ,
} bsel_str [ ] = {
" NAND Flash (1.8V) " ,
{ " rsvd " , " Reserved " , } ,
" NAND Flash (3.0V) " ,
{ " fpga " , " FPGA (HPS2FPGA Bridge) " , } ,
" SD/MMC External Transceiver (1.8V) " ,
{ " nand " , " NAND Flash (1.8V) " , } ,
" SD/MMC Internal Transceiver (3.0V) " ,
{ " nand " , " NAND Flash (3.0V) " , } ,
" QSPI Flash (1.8V) " ,
{ " sd " , " SD/MMC External Transceiver (1.8V) " , } ,
" QSPI Flash (3.0V) " ,
{ " sd " , " SD/MMC Internal Transceiver (3.0V) " , } ,
{ " qspi " , " QSPI Flash (1.8V) " , } ,
{ " qspi " , " QSPI Flash (3.0V) " , } ,
} ;
} ;
/*
/*
* Print CPU information
* Print CPU information
*/
*/
# if defined(CONFIG_DISPLAY_CPUINFO)
int print_cpuinfo ( void )
int print_cpuinfo ( void )
{
{
const u32 bsel = readl ( & sysmgr_regs - > bootinfo ) & 0x7 ;
const u32 bsel = readl ( & sysmgr_regs - > bootinfo ) & 0x7 ;
puts ( " CPU: Altera SoCFPGA Platform \n " ) ;
puts ( " CPU: Altera SoCFPGA Platform \n " ) ;
printf ( " BOOT: %s \n " , bsel_str [ bsel ] ) ;
printf ( " BOOT: %s \n " , bsel_str [ bsel ] . name ) ;
return 0 ;
}
# endif
# ifdef CONFIG_ARCH_MISC_INIT
int arch_misc_init ( void )
{
const u32 bsel = readl ( & sysmgr_regs - > bootinfo ) & 0x7 ;
setenv ( " bootmode " , bsel_str [ bsel ] . mode ) ;
return 0 ;
return 0 ;
}
}
# endif
# endif