There are two LS series processors are built on ARMv8 Layersacpe architecture currently, LS2085A and LS1043A. They are based on ARMv8 core although use different chassis, so create fsl-layerscape to refactor the common code for the LS series processors which also paves the way for adding LS1043A platform. Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>master
Mingkai Hu
9 years ago
committed by
York Sun
parent
23e1acaf4b
commit
9f3183d2d6
@ -0,0 +1,21 @@ |
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#
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# Copyright 2014-2015, Freescale Semiconductor
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y += cpu.o
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obj-y += lowlevel.o
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obj-y += soc.o
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obj-$(CONFIG_MP) += mp.o
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obj-$(CONFIG_OF_LIBFDT) += fdt.o
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obj-$(CONFIG_SPL) += spl.o
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ifneq ($(CONFIG_FSL_LSCH3),) |
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obj-y += fsl_lsch3_speed.o
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obj-$(CONFIG_SYS_HAS_SERDES) += fsl_lsch3_serdes.o
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endif |
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ifneq ($(CONFIG_LS2085A),) |
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obj-$(CONFIG_SYS_HAS_SERDES) += ls2085a_serdes.o
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endif |
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@ -1,5 +1,5 @@ |
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# |
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# Copyright 2014 Freescale Semiconductor |
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# Copyright 2014-2015 Freescale Semiconductor |
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# |
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# SPDX-License-Identifier: GPL-2.0+ |
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# |
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@ -1,5 +1,5 @@ |
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/*
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* Copyright 2014, Freescale Semiconductor |
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* Copyright 2014-2015, Freescale Semiconductor |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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@ -1,12 +1,11 @@ |
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/*
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* Copyright 2015 Freescale Semiconductor, Inc. |
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* Copyright 2014-2015 Freescale Semiconductor, Inc. |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <asm/arch/fsl_serdes.h> |
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#include <asm/arch-fsl-lsch3/immap_lsch3.h> |
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struct serdes_config { |
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u8 protocol; |
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@ -0,0 +1,76 @@ |
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/*
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* Copyright 2014-2015 Freescale Semiconductor, Inc. |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <spl.h> |
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#include <asm/io.h> |
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#include <fsl_ifc.h> |
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#include <fsl_csu.h> |
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#include <i2c.h> |
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DECLARE_GLOBAL_DATA_PTR; |
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u32 spl_boot_device(void) |
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{ |
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#ifdef CONFIG_SPL_MMC_SUPPORT |
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return BOOT_DEVICE_MMC1; |
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#endif |
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#ifdef CONFIG_SPL_NAND_SUPPORT |
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return BOOT_DEVICE_NAND; |
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#endif |
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return 0; |
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} |
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u32 spl_boot_mode(void) |
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{ |
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switch (spl_boot_device()) { |
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case BOOT_DEVICE_MMC1: |
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#ifdef CONFIG_SPL_FAT_SUPPORT |
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return MMCSD_MODE_FAT; |
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#else |
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return MMCSD_MODE_RAW; |
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#endif |
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case BOOT_DEVICE_NAND: |
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return 0; |
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default: |
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puts("spl: error: unsupported device\n"); |
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hang(); |
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} |
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} |
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#ifdef CONFIG_SPL_BUILD |
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void board_init_f(ulong dummy) |
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{ |
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/* Set global data pointer */ |
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gd = &gdata; |
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/* Clear global data */ |
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memset((void *)gd, 0, sizeof(gd_t)); |
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#ifdef CONFIG_LS2085A |
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arch_cpu_init(); |
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#endif |
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#ifdef CONFIG_FSL_IFC |
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init_early_memctl_regs(); |
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#endif |
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board_early_init_f(); |
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timer_init(); |
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#ifdef CONFIG_LS2085A |
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env_init(); |
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#endif |
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get_clocks(); |
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preloader_console_init(); |
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#ifdef CONFIG_SPL_I2C_SUPPORT |
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i2c_init_all(); |
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#endif |
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dram_init(); |
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/* Clear the BSS */ |
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memset(__bss_start, 0, __bss_end - __bss_start); |
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board_init_r(NULL, 0); |
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} |
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#endif |
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@ -1,13 +0,0 @@ |
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#
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# Copyright 2014, Freescale Semiconductor
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y += cpu.o
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obj-y += lowlevel.o
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obj-y += soc.o
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obj-y += speed.o
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obj-$(CONFIG_SYS_HAS_SERDES) += fsl_lsch3_serdes.o ls2085a_serdes.o
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obj-$(CONFIG_MP) += mp.o
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obj-$(CONFIG_OF_LIBFDT) += fdt.o
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@ -1,7 +0,0 @@ |
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/*
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* Copyright 2014, Freescale Semiconductor, Inc. |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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void get_sys_info(struct sys_info *sys_info); |
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@ -0,0 +1,96 @@ |
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/*
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* Copyright 2015, Freescale Semiconductor |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#ifndef _ASM_ARMV8_FSL_LAYERSCAPE_CONFIG_H_ |
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#define _ASM_ARMV8_FSL_LAYERSCAPE_CONFIG_H_ |
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#include <fsl_ddrc_version.h> |
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#ifdef CONFIG_SYS_FSL_DDR4 |
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#define CONFIG_SYS_FSL_DDRC_GEN4 |
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#else |
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#define CONFIG_SYS_FSL_DDRC_ARM_GEN3 /* Enable Freescale ARM DDR3 driver */ |
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#endif |
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#define CONFIG_SYS_FSL_DDR /* Freescale DDR driver */ |
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#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0 |
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#if defined(CONFIG_LS2085A) |
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#define CONFIG_MAX_CPUS 16 |
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#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 |
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#define CONFIG_NUM_DDR_CONTROLLERS 3 |
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#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4, 4 } |
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#define SRDS_MAX_LANES 8 |
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#define CONFIG_SYS_FSL_SRDS_1 |
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#define CONFIG_SYS_FSL_SRDS_2 |
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#define CONFIG_SYS_PAGE_SIZE 0x10000 |
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#define CONFIG_SYS_CACHELINE_SIZE 64 |
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#ifndef L1_CACHE_BYTES |
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#define L1_CACHE_SHIFT 6 |
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#define L1_CACHE_BYTES BIT(L1_CACHE_SHIFT) |
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#endif |
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#define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */ |
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#define CONFIG_SYS_FSL_OCRAM_SIZE 0x00200000 /* 2M */ |
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/* DDR */ |
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#define CONFIG_SYS_FSL_DDR_LE |
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#define CONFIG_SYS_LS2_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) |
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#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_LS2_DDR_BLOCK1_SIZE |
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#define CONFIG_SYS_FSL_CCSR_GUR_LE |
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#define CONFIG_SYS_FSL_CCSR_SCFG_LE |
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#define CONFIG_SYS_FSL_ESDHC_LE |
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#define CONFIG_SYS_FSL_IFC_LE |
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#define CONFIG_SYS_MEMAC_LITTLE_ENDIAN |
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/* Generic Interrupt Controller Definitions */ |
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#define GICD_BASE 0x06000000 |
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#define GICR_BASE 0x06100000 |
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/* SMMU Defintions */ |
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#define SMMU_BASE 0x05000000 /* GR0 Base */ |
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/* Cache Coherent Interconnect */ |
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#define CCI_MN_BASE 0x04000000 |
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#define CCI_MN_RNF_NODEID_LIST 0x180 |
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#define CCI_MN_DVM_DOMAIN_CTL 0x200 |
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#define CCI_MN_DVM_DOMAIN_CTL_SET 0x210 |
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#define CCI_RN_I_0_BASE (CCI_MN_BASE + 0x800000) |
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#define CCI_RN_I_2_BASE (CCI_MN_BASE + 0x820000) |
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#define CCI_RN_I_6_BASE (CCI_MN_BASE + 0x860000) |
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#define CCI_RN_I_12_BASE (CCI_MN_BASE + 0x8C0000) |
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#define CCI_RN_I_16_BASE (CCI_MN_BASE + 0x900000) |
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#define CCI_RN_I_20_BASE (CCI_MN_BASE + 0x940000) |
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#define CCI_S0_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x10) |
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#define CCI_S1_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x110) |
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#define CCI_S2_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x210) |
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/* TZ Protection Controller Definitions */ |
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#define TZPC_BASE 0x02200000 |
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#define TZPCR0SIZE_BASE (TZPC_BASE) |
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#define TZPCDECPROT_0_STAT_BASE (TZPC_BASE + 0x800) |
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#define TZPCDECPROT_0_SET_BASE (TZPC_BASE + 0x804) |
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#define TZPCDECPROT_0_CLR_BASE (TZPC_BASE + 0x808) |
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#define TZPCDECPROT_1_STAT_BASE (TZPC_BASE + 0x80C) |
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#define TZPCDECPROT_1_SET_BASE (TZPC_BASE + 0x810) |
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#define TZPCDECPROT_1_CLR_BASE (TZPC_BASE + 0x814) |
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#define TZPCDECPROT_2_STAT_BASE (TZPC_BASE + 0x818) |
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#define TZPCDECPROT_2_SET_BASE (TZPC_BASE + 0x81C) |
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#define TZPCDECPROT_2_CLR_BASE (TZPC_BASE + 0x820) |
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#define CONFIG_SYS_FSL_ERRATUM_A008336 |
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#define CONFIG_SYS_FSL_ERRATUM_A008511 |
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#define CONFIG_SYS_FSL_ERRATUM_A008514 |
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#define CONFIG_SYS_FSL_ERRATUM_A008585 |
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#define CONFIG_SYS_FSL_ERRATUM_A008751 |
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#else |
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#error SoC not defined |
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#endif |
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#endif /* _ASM_ARMV8_FSL_LAYERSCAPE_CONFIG_H_ */ |
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@ -0,0 +1,165 @@ |
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/*
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* Copyright 2014-2015, Freescale Semiconductor |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#ifndef _FSL_LAYERSCAPE_CPU_H |
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#define _FSL_LAYERSCAPE_CPU_H |
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static struct cpu_type cpu_type_list[] = { |
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CPU_TYPE_ENTRY(LS2085, LS2085, 8), |
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CPU_TYPE_ENTRY(LS2080, LS2080, 8), |
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CPU_TYPE_ENTRY(LS2045, LS2045, 4), |
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}; |
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#ifndef CONFIG_SYS_DCACHE_OFF |
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#define SECTION_SHIFT_L0 39UL |
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#define SECTION_SHIFT_L1 30UL |
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#define SECTION_SHIFT_L2 21UL |
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#define BLOCK_SIZE_L0 0x8000000000 |
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#define BLOCK_SIZE_L1 0x40000000 |
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#define BLOCK_SIZE_L2 0x200000 |
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#define NUM_OF_ENTRY 512 |
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#define TCR_EL2_PS_40BIT (2 << 16) |
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#define LAYERSCAPE_VA_BITS (40) |
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#define LAYERSCAPE_TCR (TCR_TG0_4K | \ |
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TCR_EL2_PS_40BIT | \
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TCR_SHARED_NON | \
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TCR_ORGN_NC | \
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TCR_IRGN_NC | \
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TCR_T0SZ(LAYERSCAPE_VA_BITS)) |
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#define LAYERSCAPE_TCR_FINAL (TCR_TG0_4K | \ |
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TCR_EL2_PS_40BIT | \
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TCR_SHARED_OUTER | \
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TCR_ORGN_WBWA | \
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TCR_IRGN_WBWA | \
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TCR_T0SZ(LAYERSCAPE_VA_BITS)) |
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#ifdef CONFIG_FSL_LSCH3 |
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#define CONFIG_SYS_FSL_CCSR_BASE 0x00000000 |
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#define CONFIG_SYS_FSL_CCSR_SIZE 0x10000000 |
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#define CONFIG_SYS_FSL_QSPI_BASE1 0x20000000 |
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#define CONFIG_SYS_FSL_QSPI_SIZE1 0x10000000 |
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#define CONFIG_SYS_FSL_IFC_BASE1 0x30000000 |
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#define CONFIG_SYS_FSL_IFC_SIZE1 0x10000000 |
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#define CONFIG_SYS_FSL_IFC_SIZE1_1 0x400000 |
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#define CONFIG_SYS_FSL_DRAM_BASE1 0x80000000 |
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#define CONFIG_SYS_FSL_DRAM_SIZE1 0x80000000 |
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#define CONFIG_SYS_FSL_QSPI_BASE2 0x400000000 |
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#define CONFIG_SYS_FSL_QSPI_SIZE2 0x100000000 |
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#define CONFIG_SYS_FSL_IFC_BASE2 0x500000000 |
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#define CONFIG_SYS_FSL_IFC_SIZE2 0x100000000 |
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#define CONFIG_SYS_FSL_DCSR_BASE 0x700000000 |
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#define CONFIG_SYS_FSL_DCSR_SIZE 0x40000000 |
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#define CONFIG_SYS_FSL_MC_BASE 0x80c000000 |
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#define CONFIG_SYS_FSL_MC_SIZE 0x4000000 |
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#define CONFIG_SYS_FSL_NI_BASE 0x810000000 |
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#define CONFIG_SYS_FSL_NI_SIZE 0x8000000 |
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#define CONFIG_SYS_FSL_QBMAN_BASE 0x818000000 |
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#define CONFIG_SYS_FSL_QBMAN_SIZE 0x8000000 |
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#define CONFIG_SYS_FSL_QBMAN_SIZE_1 0x4000000 |
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#define CONFIG_SYS_PCIE1_PHYS_SIZE 0x200000000 |
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#define CONFIG_SYS_PCIE2_PHYS_SIZE 0x200000000 |
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#define CONFIG_SYS_PCIE3_PHYS_SIZE 0x200000000 |
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#define CONFIG_SYS_PCIE4_PHYS_SIZE 0x200000000 |
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#define CONFIG_SYS_FSL_WRIOP1_BASE 0x4300000000 |
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#define CONFIG_SYS_FSL_WRIOP1_SIZE 0x100000000 |
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#define CONFIG_SYS_FSL_AIOP1_BASE 0x4b00000000 |
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#define CONFIG_SYS_FSL_AIOP1_SIZE 0x100000000 |
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#define CONFIG_SYS_FSL_PEBUF_BASE 0x4c00000000 |
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#define CONFIG_SYS_FSL_PEBUF_SIZE 0x400000000 |
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#define CONFIG_SYS_FSL_DRAM_BASE2 0x8080000000 |
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#define CONFIG_SYS_FSL_DRAM_SIZE2 0x7F80000000 |
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#endif |
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struct sys_mmu_table { |
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u64 virt_addr; |
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u64 phys_addr; |
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u64 size; |
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u64 memory_type; |
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u64 share; |
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}; |
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struct table_info { |
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u64 *ptr; |
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u64 table_base; |
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u64 entry_size; |
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}; |
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static const struct sys_mmu_table early_mmu_table[] = { |
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#ifdef CONFIG_FSL_LSCH3 |
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{ CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE, |
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CONFIG_SYS_FSL_CCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, |
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{ CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE, |
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CONFIG_SYS_FSL_OCRAM_SIZE, MT_NORMAL, PMD_SECT_NON_SHARE }, |
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/* For IFC Region #1, only the first 4MB is cache-enabled */ |
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{ CONFIG_SYS_FSL_IFC_BASE1, CONFIG_SYS_FSL_IFC_BASE1, |
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CONFIG_SYS_FSL_IFC_SIZE1_1, MT_NORMAL, PMD_SECT_NON_SHARE }, |
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{ CONFIG_SYS_FSL_IFC_BASE1 + CONFIG_SYS_FSL_IFC_SIZE1_1, |
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CONFIG_SYS_FSL_IFC_BASE1 + CONFIG_SYS_FSL_IFC_SIZE1_1, |
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CONFIG_SYS_FSL_IFC_SIZE1 - CONFIG_SYS_FSL_IFC_SIZE1_1, |
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MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, |
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{ CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FSL_IFC_BASE1, |
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CONFIG_SYS_FSL_IFC_SIZE1, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, |
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{ CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1, |
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CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL, PMD_SECT_OUTER_SHARE }, |
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{ CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE, |
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CONFIG_SYS_FSL_DCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, |
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{ CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2, |
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CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL, PMD_SECT_OUTER_SHARE }, |
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#endif |
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}; |
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static const struct sys_mmu_table final_mmu_table[] = { |
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#ifdef CONFIG_FSL_LSCH3 |
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{ CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE, |
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CONFIG_SYS_FSL_CCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, |
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{ CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE, |
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CONFIG_SYS_FSL_OCRAM_SIZE, MT_NORMAL, PMD_SECT_NON_SHARE }, |
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{ CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1, |
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CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL, PMD_SECT_OUTER_SHARE }, |
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{ CONFIG_SYS_FSL_QSPI_BASE2, CONFIG_SYS_FSL_QSPI_BASE2, |
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CONFIG_SYS_FSL_QSPI_SIZE2, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, |
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{ CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2, |
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CONFIG_SYS_FSL_IFC_SIZE2, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, |
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{ CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE, |
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CONFIG_SYS_FSL_DCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, |
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{ CONFIG_SYS_FSL_MC_BASE, CONFIG_SYS_FSL_MC_BASE, |
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CONFIG_SYS_FSL_MC_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, |
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{ CONFIG_SYS_FSL_NI_BASE, CONFIG_SYS_FSL_NI_BASE, |
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CONFIG_SYS_FSL_NI_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, |
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/* For QBMAN portal, only the first 64MB is cache-enabled */ |
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{ CONFIG_SYS_FSL_QBMAN_BASE, CONFIG_SYS_FSL_QBMAN_BASE, |
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CONFIG_SYS_FSL_QBMAN_SIZE_1, MT_NORMAL, PMD_SECT_NON_SHARE }, |
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{ CONFIG_SYS_FSL_QBMAN_BASE + CONFIG_SYS_FSL_QBMAN_SIZE_1, |
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CONFIG_SYS_FSL_QBMAN_BASE + CONFIG_SYS_FSL_QBMAN_SIZE_1, |
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CONFIG_SYS_FSL_QBMAN_SIZE - CONFIG_SYS_FSL_QBMAN_SIZE_1, |
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MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, |
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{ CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR, |
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CONFIG_SYS_PCIE1_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, |
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{ CONFIG_SYS_PCIE2_PHYS_ADDR, CONFIG_SYS_PCIE2_PHYS_ADDR, |
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CONFIG_SYS_PCIE2_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, |
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{ CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR, |
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CONFIG_SYS_PCIE3_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, |
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#ifdef CONFIG_LS2085A |
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{ CONFIG_SYS_PCIE4_PHYS_ADDR, CONFIG_SYS_PCIE4_PHYS_ADDR, |
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CONFIG_SYS_PCIE4_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, |
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#endif |
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{ CONFIG_SYS_FSL_WRIOP1_BASE, CONFIG_SYS_FSL_WRIOP1_BASE, |
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CONFIG_SYS_FSL_WRIOP1_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, |
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{ CONFIG_SYS_FSL_AIOP1_BASE, CONFIG_SYS_FSL_AIOP1_BASE, |
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CONFIG_SYS_FSL_AIOP1_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, |
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{ CONFIG_SYS_FSL_PEBUF_BASE, CONFIG_SYS_FSL_PEBUF_BASE, |
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CONFIG_SYS_FSL_PEBUF_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, |
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{ CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2, |
||||
CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL, PMD_SECT_OUTER_SHARE }, |
||||
#endif |
||||
}; |
||||
#endif |
||||
|
||||
int fsl_qoriq_core_to_cluster(unsigned int core); |
||||
u32 cpu_mask(void); |
||||
#endif /* _FSL_LAYERSCAPE_CPU_H */ |
||||
@ -0,0 +1,55 @@ |
||||
/*
|
||||
* Copyright 2015 Freescale Semiconductor, Inc. |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
* |
||||
*/ |
||||
|
||||
#ifndef __ASM_ARCH_FSL_LAYERSCAPE_IMX_REGS_H__ |
||||
#define __ASM_ARCH_FSL_LAYERSCAPE_IMX_REGS_H__ |
||||
|
||||
#define I2C_QUIRK_REG /* enable 8-bit driver */ |
||||
|
||||
#ifdef CONFIG_FSL_LPUART |
||||
#ifdef CONFIG_LPUART_32B_REG |
||||
struct lpuart_fsl { |
||||
u32 baud; |
||||
u32 stat; |
||||
u32 ctrl; |
||||
u32 data; |
||||
u32 match; |
||||
u32 modir; |
||||
u32 fifo; |
||||
u32 water; |
||||
}; |
||||
#else |
||||
struct lpuart_fsl { |
||||
u8 ubdh; |
||||
u8 ubdl; |
||||
u8 uc1; |
||||
u8 uc2; |
||||
u8 us1; |
||||
u8 us2; |
||||
u8 uc3; |
||||
u8 ud; |
||||
u8 uma1; |
||||
u8 uma2; |
||||
u8 uc4; |
||||
u8 uc5; |
||||
u8 ued; |
||||
u8 umodem; |
||||
u8 uir; |
||||
u8 reserved; |
||||
u8 upfifo; |
||||
u8 ucfifo; |
||||
u8 usfifo; |
||||
u8 utwfifo; |
||||
u8 utcfifo; |
||||
u8 urwfifo; |
||||
u8 urcfifo; |
||||
u8 rsvd[28]; |
||||
}; |
||||
#endif |
||||
#endif /* CONFIG_FSL_LPUART */ |
||||
|
||||
#endif /* __ASM_ARCH_FSL_LAYERSCAPE_IMX_REGS_H__ */ |
||||
@ -0,0 +1,10 @@ |
||||
/*
|
||||
* Copyright 2015, Freescale Semiconductor |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#ifndef _ASM_ARMV8_FSL_LAYERSCAPE_MMU_H_ |
||||
#define _ASM_ARMV8_FSL_LAYERSCAPE_MMU_H_ |
||||
#include <asm/arch-armv8/mmu.h> |
||||
#endif /* _ASM_ARMV8_FSL_LAYERSCAPE_MMU_H_ */ |
||||
@ -0,0 +1,10 @@ |
||||
/*
|
||||
* Copyright 2014-2015, Freescale Semiconductor, Inc. |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#ifndef _FSL_LAYERSCAPE_SPEED_H |
||||
#define _FSL_LAYERSCAPE_SPEED_H |
||||
void get_sys_info(struct sys_info *sys_info); |
||||
#endif /* _FSL_LAYERSCAPE_SPEED_H */ |
||||
@ -1,185 +0,0 @@ |
||||
/*
|
||||
* Copyright 2014, Freescale Semiconductor |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#ifndef _ASM_ARMV8_FSL_LSCH3_CONFIG_ |
||||
#define _ASM_ARMV8_FSL_LSCH3_CONFIG_ |
||||
|
||||
#include <fsl_ddrc_version.h> |
||||
|
||||
#define CONFIG_SYS_PAGE_SIZE 0x10000 |
||||
#define CONFIG_SYS_CACHELINE_SIZE 64 |
||||
|
||||
#ifndef L1_CACHE_BYTES |
||||
#define L1_CACHE_SHIFT 6 |
||||
#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) |
||||
#endif |
||||
|
||||
#define CONFIG_MP |
||||
#define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */ |
||||
#define CONFIG_SYS_FSL_OCRAM_SIZE 0x00200000 /* 2M */ |
||||
/* Link Definitions */ |
||||
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0) |
||||
|
||||
#define CONFIG_SYS_IMMR 0x01000000 |
||||
#define CONFIG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000) |
||||
#define CONFIG_SYS_FSL_DDR2_ADDR (CONFIG_SYS_IMMR + 0x00090000) |
||||
#define CONFIG_SYS_FSL_DDR3_ADDR 0x08210000 |
||||
#define CONFIG_SYS_FSL_GUTS_ADDR (CONFIG_SYS_IMMR + 0x00E00000) |
||||
#define CONFIG_SYS_FSL_PMU_ADDR (CONFIG_SYS_IMMR + 0x00E30000) |
||||
#define CONFIG_SYS_FSL_RST_ADDR (CONFIG_SYS_IMMR + 0x00E60000) |
||||
#define CONFIG_SYS_FSL_CH3_CLK_GRPA_ADDR (CONFIG_SYS_IMMR + 0x00300000) |
||||
#define CONFIG_SYS_FSL_CH3_CLK_GRPB_ADDR (CONFIG_SYS_IMMR + 0x00310000) |
||||
#define CONFIG_SYS_FSL_CH3_CLK_CTRL_ADDR (CONFIG_SYS_IMMR + 0x00370000) |
||||
#define CONFIG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x01140000) |
||||
#define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x01240000) |
||||
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011C0500) |
||||
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011C0600) |
||||
#define CONFIG_SYS_FSL_TIMER_ADDR 0x023d0000 |
||||
#define CONFIG_SYS_FSL_PMU_CLTBENR (CONFIG_SYS_FSL_PMU_ADDR + \ |
||||
0x18A0) |
||||
|
||||
#define CONFIG_SYS_FSL_WRIOP1_ADDR (CONFIG_SYS_IMMR + 0x7B80000) |
||||
#define CONFIG_SYS_FSL_WRIOP1_MDIO1 (CONFIG_SYS_FSL_WRIOP1_ADDR + 0x16000) |
||||
#define CONFIG_SYS_FSL_WRIOP1_MDIO2 (CONFIG_SYS_FSL_WRIOP1_ADDR + 0x17000) |
||||
#define CONFIG_SYS_FSL_LSCH3_SERDES_ADDR (CONFIG_SYS_IMMR + 0xEA0000) |
||||
|
||||
/* SP (Cortex-A5) related */ |
||||
#define CONFIG_SYS_FSL_SP_ADDR (CONFIG_SYS_IMMR + 0x00F00000) |
||||
#define CONFIG_SYS_FSL_SP_VSG_GIC_ADDR (CONFIG_SYS_FSL_SP_ADDR) |
||||
#define CONFIG_SYS_FSL_SP_VSG_GIC_VIGR1 (CONFIG_SYS_FSL_SP_ADDR) |
||||
#define CONFIG_SYS_FSL_SP_VSG_GIC_VIGR2 \ |
||||
(CONFIG_SYS_FSL_SP_ADDR + 0x0008) |
||||
#define CONFIG_SYS_FSL_SP_LOOPBACK_DUART \ |
||||
(CONFIG_SYS_FSL_SP_ADDR + 0x1000) |
||||
|
||||
#define CONFIG_SYS_FSL_DCSR_DDR_ADDR 0x70012c000ULL |
||||
#define CONFIG_SYS_FSL_DCSR_DDR2_ADDR 0x70012d000ULL |
||||
#define CONFIG_SYS_FSL_DCSR_DDR3_ADDR 0x700132000ULL |
||||
#define CONFIG_SYS_FSL_DCSR_DDR4_ADDR 0x700133000ULL |
||||
|
||||
#define I2C1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01000000) |
||||
#define I2C2_BASE_ADDR (CONFIG_SYS_IMMR + 0x01010000) |
||||
#define I2C3_BASE_ADDR (CONFIG_SYS_IMMR + 0x01020000) |
||||
#define I2C4_BASE_ADDR (CONFIG_SYS_IMMR + 0x01030000) |
||||
|
||||
#define CONFIG_SYS_LS2085A_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x02100000) |
||||
#define CONFIG_SYS_LS2085A_XHCI_USB2_ADDR (CONFIG_SYS_IMMR + 0x02110000) |
||||
|
||||
/* TZ Protection Controller Definitions */ |
||||
#define TZPC_BASE 0x02200000 |
||||
#define TZPCR0SIZE_BASE (TZPC_BASE) |
||||
#define TZPCDECPROT_0_STAT_BASE (TZPC_BASE + 0x800) |
||||
#define TZPCDECPROT_0_SET_BASE (TZPC_BASE + 0x804) |
||||
#define TZPCDECPROT_0_CLR_BASE (TZPC_BASE + 0x808) |
||||
#define TZPCDECPROT_1_STAT_BASE (TZPC_BASE + 0x80C) |
||||
#define TZPCDECPROT_1_SET_BASE (TZPC_BASE + 0x810) |
||||
#define TZPCDECPROT_1_CLR_BASE (TZPC_BASE + 0x814) |
||||
#define TZPCDECPROT_2_STAT_BASE (TZPC_BASE + 0x818) |
||||
#define TZPCDECPROT_2_SET_BASE (TZPC_BASE + 0x81C) |
||||
#define TZPCDECPROT_2_CLR_BASE (TZPC_BASE + 0x820) |
||||
|
||||
/* TZ Address Space Controller Definitions */ |
||||
#define TZASC1_BASE 0x01100000 /* as per CCSR map. */ |
||||
#define TZASC2_BASE 0x01110000 /* as per CCSR map. */ |
||||
#define TZASC3_BASE 0x01120000 /* as per CCSR map. */ |
||||
#define TZASC4_BASE 0x01130000 /* as per CCSR map. */ |
||||
#define TZASC_BUILD_CONFIG_REG(x) ((TZASC1_BASE + (x * 0x10000))) |
||||
#define TZASC_ACTION_REG(x) ((TZASC1_BASE + (x * 0x10000)) + 0x004) |
||||
#define TZASC_GATE_KEEPER(x) ((TZASC1_BASE + (x * 0x10000)) + 0x008) |
||||
#define TZASC_REGION_BASE_LOW_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x100) |
||||
#define TZASC_REGION_BASE_HIGH_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x104) |
||||
#define TZASC_REGION_TOP_LOW_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x108) |
||||
#define TZASC_REGION_TOP_HIGH_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x10C) |
||||
#define TZASC_REGION_ATTRIBUTES_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x110) |
||||
#define TZASC_REGION_ID_ACCESS_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x114) |
||||
|
||||
/* Generic Interrupt Controller Definitions */ |
||||
#define GICD_BASE 0x06000000 |
||||
#define GICR_BASE 0x06100000 |
||||
|
||||
/* SMMU Defintions */ |
||||
#define SMMU_BASE 0x05000000 /* GR0 Base */ |
||||
|
||||
/* DDR */ |
||||
#define CONFIG_SYS_FSL_DDR_LE |
||||
#define CONFIG_VERY_BIG_RAM |
||||
#ifdef CONFIG_SYS_FSL_DDR4 |
||||
#define CONFIG_SYS_FSL_DDRC_GEN4 |
||||
#else |
||||
#define CONFIG_SYS_FSL_DDRC_ARM_GEN3 /* Enable Freescale ARM DDR3 driver */ |
||||
#endif |
||||
#define CONFIG_SYS_FSL_DDR /* Freescale DDR driver */ |
||||
#define CONFIG_SYS_LS2_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) |
||||
#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_LS2_DDR_BLOCK1_SIZE |
||||
#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0 |
||||
|
||||
#define CONFIG_SYS_FSL_ESDHC_LE |
||||
/* IFC */ |
||||
#define CONFIG_SYS_FSL_IFC_LE |
||||
#define CONFIG_SYS_MEMAC_LITTLE_ENDIAN |
||||
|
||||
/* PCIe */ |
||||
#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000) |
||||
#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000) |
||||
#define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_IMMR + 0x2600000) |
||||
#define CONFIG_SYS_PCIE4_ADDR (CONFIG_SYS_IMMR + 0x2700000) |
||||
#define CONFIG_SYS_PCIE1_PHYS_ADDR 0x1000000000ULL |
||||
#define CONFIG_SYS_PCIE2_PHYS_ADDR 0x1200000000ULL |
||||
#define CONFIG_SYS_PCIE3_PHYS_ADDR 0x1400000000ULL |
||||
#define CONFIG_SYS_PCIE4_PHYS_ADDR 0x1600000000ULL |
||||
|
||||
/* Cache Coherent Interconnect */ |
||||
#define CCI_MN_BASE 0x04000000 |
||||
#define CCI_MN_RNF_NODEID_LIST 0x180 |
||||
#define CCI_MN_DVM_DOMAIN_CTL 0x200 |
||||
#define CCI_MN_DVM_DOMAIN_CTL_SET 0x210 |
||||
|
||||
#define CCI_RN_I_0_BASE (CCI_MN_BASE + 0x800000) |
||||
#define CCI_RN_I_2_BASE (CCI_MN_BASE + 0x820000) |
||||
#define CCI_RN_I_6_BASE (CCI_MN_BASE + 0x860000) |
||||
#define CCI_RN_I_12_BASE (CCI_MN_BASE + 0x8C0000) |
||||
#define CCI_RN_I_16_BASE (CCI_MN_BASE + 0x900000) |
||||
#define CCI_RN_I_20_BASE (CCI_MN_BASE + 0x940000) |
||||
|
||||
#define CCI_S0_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x10) |
||||
#define CCI_S1_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x110) |
||||
#define CCI_S2_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x210) |
||||
|
||||
/* Device Configuration */ |
||||
#define DCFG_BASE 0x01e00000 |
||||
#define DCFG_PORSR1 0x000 |
||||
#define DCFG_PORSR1_RCW_SRC 0xff800000 |
||||
#define DCFG_PORSR1_RCW_SRC_NOR 0x12f00000 |
||||
#define DCFG_RCWSR13 0x130 |
||||
#define DCFG_RCWSR13_DSPI (0 << 8) |
||||
|
||||
#define DCFG_DCSR_BASE 0X700100000ULL |
||||
#define DCFG_DCSR_PORCR1 0x000 |
||||
|
||||
/* Supplemental Configuration */ |
||||
#define SCFG_BASE 0x01fc0000 |
||||
#define SCFG_USB3PRM1CR 0x000 |
||||
|
||||
#ifdef CONFIG_LS2085A |
||||
#define CONFIG_MAX_CPUS 16 |
||||
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 |
||||
#define CONFIG_NUM_DDR_CONTROLLERS 3 |
||||
#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4, 4 } |
||||
#define CONFIG_SYS_FSL_SRDS_1 |
||||
#define CONFIG_SYS_FSL_SRDS_2 |
||||
#else |
||||
#error SoC not defined |
||||
#endif |
||||
|
||||
#ifdef CONFIG_LS2085A |
||||
#define CONFIG_SYS_FSL_ERRATUM_A008336 |
||||
#define CONFIG_SYS_FSL_ERRATUM_A008511 |
||||
#define CONFIG_SYS_FSL_ERRATUM_A008514 |
||||
#define CONFIG_SYS_FSL_ERRATUM_A008585 |
||||
#define CONFIG_SYS_FSL_ERRATUM_A008751 |
||||
#endif |
||||
|
||||
#endif /* _ASM_ARMV8_FSL_LSCH3_CONFIG_ */ |
||||
@ -1,9 +0,0 @@ |
||||
/*
|
||||
* Copyright 2014, Freescale Semiconductor |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#ifndef _ASM_ARMV8_FSL_LSCH3_GPIO_H_ |
||||
#define _ASM_ARMV8_FSL_LSCH3_GPIO_H_ |
||||
#endif /* _ASM_ARMV8_FSL_LSCH3_GPIO_H_ */ |
||||
@ -1,13 +0,0 @@ |
||||
/*
|
||||
* Copyright 2014 Freescale Semiconductor, Inc. |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
* |
||||
*/ |
||||
|
||||
#ifndef __ASM_ARCH_FSL_LSCH3_IMX_REGS_H_ |
||||
#define __ASM_ARCH_FSL_LSCH3_IMX_REGS_H_ |
||||
|
||||
#define I2C_QUIRK_REG /* enable 8-bit driver */ |
||||
|
||||
#endif /* __ASM_ARCH_FSL_LSCH3_IMX_REGS_H_ */ |
||||
Loading…
Reference in new issue