This driver initializes PIC32 DDR2 SDRAM controller and internal DDR2 Phy module. DDR2 controller operates in half-rate mode (upto 533MHZ frequency). Signed-off-by: Paul Thacker <paul.thacker@microchip.com> Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>master
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/*
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* (c) 2015 Purna Chandra Mandal <purna.mandal@microchip.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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* |
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*/ |
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#ifndef __MICROCHIP_PIC32_DDR_H |
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#define __MICROCHIP_PIC32_DDR_H |
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/* called by initdram() function */ |
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void ddr2_phy_init(void); |
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void ddr2_ctrl_init(void); |
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phys_size_t ddr2_calculate_size(void); |
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/* Maximum number of agents */ |
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#define NUM_AGENTS 5 |
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/* Board can provide agent specific parameters for arbitration by
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* filling struct ddr2_arbiter_params for all the agents and |
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* implementing board_get_ddr_arbiter_params() to return the filled |
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* structure. |
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*/ |
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struct ddr2_arbiter_params { |
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u32 min_limit; /* min bursts to execute per arbitration */ |
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u32 req_period; /* request period threshold for accepted cmds */ |
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u32 min_cmd_acpt; /* min number of accepted cmds */ |
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}; |
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const struct ddr2_arbiter_params *board_get_ddr_arbiter_params(void); |
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#endif /* __MICROCHIP_PIC32_DDR_H */ |
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#
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# Copyright (C) 2015 Microchip Technology Inc.
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-$(CONFIG_MACH_PIC32) += ddr2.o
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/*
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* (c) 2015 Paul Thacker <paul.thacker@microchip.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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* |
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*/ |
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#include <common.h> |
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#include <wait_bit.h> |
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#include <linux/kernel.h> |
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#include <linux/bitops.h> |
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#include <mach/pic32.h> |
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#include <mach/ddr.h> |
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#include "ddr2_regs.h" |
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#include "ddr2_timing.h" |
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/* init DDR2 Phy */ |
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void ddr2_phy_init(void) |
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{ |
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struct ddr2_phy_regs *ddr2_phy; |
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u32 pad_ctl; |
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ddr2_phy = ioremap(PIC32_DDR2P_BASE, sizeof(*ddr2_phy)); |
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/* PHY_DLL_RECALIB */ |
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writel(DELAY_START_VAL(3) | DISABLE_RECALIB(0) | |
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RECALIB_CNT(0x10), &ddr2_phy->dll_recalib); |
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/* PHY_PAD_CTRL */ |
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pad_ctl = ODT_SEL | ODT_EN | DRIVE_SEL(0) | |
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ODT_PULLDOWN(2) | ODT_PULLUP(3) | |
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EXTRA_OEN_CLK(0) | NOEXT_DLL | |
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DLR_DFT_WRCMD | HALF_RATE | |
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DRVSTR_PFET(0xe) | DRVSTR_NFET(0xe) | |
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RCVR_EN | PREAMBLE_DLY(2); |
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writel(pad_ctl, &ddr2_phy->pad_ctrl); |
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/* SCL_CONFIG_0 */ |
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writel(SCL_BURST8 | SCL_DDR_CONNECTED | SCL_RCAS_LAT(RL) | |
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SCL_ODTCSWW, &ddr2_phy->scl_config_1); |
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/* SCL_CONFIG_1 */ |
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writel(SCL_CSEN | SCL_WCAS_LAT(WL), &ddr2_phy->scl_config_2); |
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/* SCL_LAT */ |
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writel(SCL_CAPCLKDLY(3) | SCL_DDRCLKDLY(4), &ddr2_phy->scl_latency); |
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} |
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/* start phy self calibration logic */ |
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static int ddr2_phy_calib_start(void) |
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{ |
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struct ddr2_phy_regs *ddr2_phy; |
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ddr2_phy = ioremap(PIC32_DDR2P_BASE, sizeof(*ddr2_phy)); |
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/* DDR Phy SCL Start */ |
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writel(SCL_START | SCL_EN, &ddr2_phy->scl_start); |
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/* Wait for SCL for data byte to pass */ |
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return wait_for_bit(__func__, &ddr2_phy->scl_start, SCL_LUBPASS, |
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true, CONFIG_SYS_HZ, false); |
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} |
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/* DDR2 Controller initialization */ |
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/* Target Agent Arbiter */ |
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static void ddr_set_arbiter(struct ddr2_ctrl_regs *ctrl, |
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const struct ddr2_arbiter_params *const param) |
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{ |
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int i; |
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for (i = 0; i < NUM_AGENTS; i++) { |
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/* set min burst size */ |
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writel(i * MIN_LIM_WIDTH, &ctrl->tsel); |
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writel(param->min_limit, &ctrl->minlim); |
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/* set request period (4 * req_period clocks) */ |
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writel(i * RQST_PERIOD_WIDTH, &ctrl->tsel); |
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writel(param->req_period, &ctrl->reqprd); |
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/* set number of burst accepted */ |
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writel(i * MIN_CMDACPT_WIDTH, &ctrl->tsel); |
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writel(param->min_cmd_acpt, &ctrl->mincmd); |
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} |
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} |
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const struct ddr2_arbiter_params *__weak board_get_ddr_arbiter_params(void) |
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{ |
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/* default arbiter parameters */ |
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static const struct ddr2_arbiter_params arb_params[] = { |
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{ .min_limit = 0x1f, .req_period = 0xff, .min_cmd_acpt = 0x04,}, |
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{ .min_limit = 0x1f, .req_period = 0xff, .min_cmd_acpt = 0x10,}, |
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{ .min_limit = 0x1f, .req_period = 0xff, .min_cmd_acpt = 0x10,}, |
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{ .min_limit = 0x04, .req_period = 0xff, .min_cmd_acpt = 0x04,}, |
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{ .min_limit = 0x04, .req_period = 0xff, .min_cmd_acpt = 0x04,}, |
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}; |
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return &arb_params[0]; |
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} |
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static void host_load_cmd(struct ddr2_ctrl_regs *ctrl, u32 cmd_idx, |
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u32 hostcmd2, u32 hostcmd1, u32 delay) |
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{ |
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u32 hc_delay; |
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hc_delay = max_t(u32, DIV_ROUND_UP(delay, T_CK), 2) - 2; |
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writel(hostcmd1, &ctrl->cmd10[cmd_idx]); |
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writel((hostcmd2 & 0x7ff) | (hc_delay << 11), &ctrl->cmd20[cmd_idx]); |
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} |
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/* init DDR2 Controller */ |
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void ddr2_ctrl_init(void) |
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{ |
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u32 wr2prech, rd2prech, wr2rd, wr2rd_cs; |
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u32 ras2ras, ras2cas, prech2ras, temp; |
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const struct ddr2_arbiter_params *arb_params; |
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struct ddr2_ctrl_regs *ctrl; |
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ctrl = ioremap(PIC32_DDR2C_BASE, sizeof(*ctrl)); |
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/* PIC32 DDR2 controller always work in HALF_RATE */ |
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writel(HALF_RATE_MODE, &ctrl->memwidth); |
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/* Set arbiter configuration per target */ |
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arb_params = board_get_ddr_arbiter_params(); |
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ddr_set_arbiter(ctrl, arb_params); |
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/* Address Configuration, model {CS, ROW, BA, COL} */ |
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writel((ROW_ADDR_RSHIFT | (BA_RSHFT << 8) | (CS_ADDR_RSHIFT << 16) | |
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(COL_HI_RSHFT << 24) | (SB_PRI << 29) | |
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(EN_AUTO_PRECH << 30)), &ctrl->memcfg0); |
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writel(ROW_ADDR_MASK, &ctrl->memcfg1); |
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writel(COL_HI_MASK, &ctrl->memcfg2); |
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writel(COL_LO_MASK, &ctrl->memcfg3); |
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writel(BA_MASK | (CS_ADDR_MASK << 8), &ctrl->memcfg4); |
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/* Refresh Config */ |
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writel(REFCNT_CLK(DIV_ROUND_UP(T_RFI, T_CK_CTRL) - 2) | |
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REFDLY_CLK(DIV_ROUND_UP(T_RFC_MIN, T_CK_CTRL) - 2) | |
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MAX_PEND_REF(7), |
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&ctrl->refcfg); |
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/* Power Config */ |
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writel(ECC_EN(0) | ERR_CORR_EN(0) | EN_AUTO_PWR_DN(0) | |
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EN_AUTO_SELF_REF(3) | PWR_DN_DLY(8) | |
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SELF_REF_DLY(17) | PRECH_PWR_DN_ONLY(0), |
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&ctrl->pwrcfg); |
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/* Delay Config */ |
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wr2rd = max_t(u32, DIV_ROUND_UP(T_WTR, T_CK_CTRL), |
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DIV_ROUND_UP(T_WTR_TCK, 2)) + WL + BL; |
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wr2rd_cs = max_t(u32, wr2rd - 1, 3); |
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wr2prech = DIV_ROUND_UP(T_WR, T_CK_CTRL) + WL + BL; |
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rd2prech = max_t(u32, DIV_ROUND_UP(T_RTP, T_CK_CTRL), |
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DIV_ROUND_UP(T_RTP_TCK, 2)) + BL - 2; |
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ras2ras = max_t(u32, DIV_ROUND_UP(T_RRD, T_CK_CTRL), |
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DIV_ROUND_UP(T_RRD_TCK, 2)) - 1; |
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ras2cas = DIV_ROUND_UP(T_RCD, T_CK_CTRL) - 1; |
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prech2ras = DIV_ROUND_UP(T_RP, T_CK_CTRL) - 1; |
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writel(((wr2rd & 0x0f) | |
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((wr2rd_cs & 0x0f) << 4) | |
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((BL - 1) << 8) | |
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(BL << 12) | |
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((BL - 1) << 16) | |
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((BL - 1) << 20) | |
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((BL + 2) << 24) | |
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((RL - WL + 3) << 28)), &ctrl->dlycfg0); |
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writel(((T_CKE_TCK - 1) | |
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(((DIV_ROUND_UP(T_DLLK, 2) - 2) & 0xff) << 8) | |
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((T_CKE_TCK - 1) << 16) | |
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((max_t(u32, T_XP_TCK, T_CKE_TCK) - 1) << 20) | |
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((wr2prech >> 4) << 26) | |
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((wr2rd >> 4) << 27) | |
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((wr2rd_cs >> 4) << 28) | |
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(((RL + 5) >> 4) << 29) | |
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((DIV_ROUND_UP(T_DLLK, 2) >> 8) << 30)), &ctrl->dlycfg1); |
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writel((DIV_ROUND_UP(T_RP, T_CK_CTRL) | |
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(rd2prech << 8) | |
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((wr2prech & 0x0f) << 12) | |
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(ras2ras << 16) | |
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(ras2cas << 20) | |
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(prech2ras << 24) | |
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((RL + 3) << 28)), &ctrl->dlycfg2); |
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writel(((DIV_ROUND_UP(T_RAS_MIN, T_CK_CTRL) - 1) | |
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((DIV_ROUND_UP(T_RC, T_CK_CTRL) - 1) << 8) | |
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((DIV_ROUND_UP(T_FAW, T_CK_CTRL) - 1) << 16)), |
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&ctrl->dlycfg3); |
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/* ODT Config */ |
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writel(0x0, &ctrl->odtcfg); |
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writel(BIT(16), &ctrl->odtencfg); |
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writel(ODTRDLY(RL - 3) | ODTWDLY(WL - 3) | ODTRLEN(2) | ODTWLEN(3), |
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&ctrl->odtcfg); |
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/* Transfer Configuration */ |
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writel(NXTDATRQDLY(2) | NXDATAVDLY(4) | RDATENDLY(2) | |
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MAX_BURST(3) | (7 << 28) | BIG_ENDIAN(0), |
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&ctrl->xfercfg); |
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/* DRAM Initialization */ |
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/* CKE high after reset and wait 400 nsec */ |
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host_load_cmd(ctrl, 0, 0, IDLE_NOP, 400000); |
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/* issue precharge all command */ |
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host_load_cmd(ctrl, 1, 0x04, PRECH_ALL_CMD, T_RP + T_CK); |
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/* initialize EMR2 */ |
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host_load_cmd(ctrl, 2, 0x200, LOAD_MODE_CMD, T_MRD_TCK * T_CK); |
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/* initialize EMR3 */ |
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host_load_cmd(ctrl, 3, 0x300, LOAD_MODE_CMD, T_MRD_TCK * T_CK); |
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/*
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* RDQS disable, DQSB enable, OCD exit, 150 ohm termination, |
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* AL=0, DLL enable |
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*/ |
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host_load_cmd(ctrl, 4, 0x100, |
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LOAD_MODE_CMD | (0x40 << 24), T_MRD_TCK * T_CK); |
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/*
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* PD fast exit, WR REC = T_WR in clocks -1, |
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* DLL reset, CAS = RL, burst = 4 |
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*/ |
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temp = ((DIV_ROUND_UP(T_WR, T_CK) - 1) << 1) | 1; |
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host_load_cmd(ctrl, 5, temp, LOAD_MODE_CMD | (RL << 28) | (2 << 24), |
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T_MRD_TCK * T_CK); |
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/* issue precharge all command */ |
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host_load_cmd(ctrl, 6, 4, PRECH_ALL_CMD, T_RP + T_CK); |
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/* issue refresh command */ |
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host_load_cmd(ctrl, 7, 0, REF_CMD, T_RFC_MIN); |
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/* issue refresh command */ |
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host_load_cmd(ctrl, 8, 0, REF_CMD, T_RFC_MIN); |
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/* Mode register programming as before without DLL reset */ |
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host_load_cmd(ctrl, 9, temp, LOAD_MODE_CMD | (RL << 28) | (3 << 24), |
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T_MRD_TCK * T_CK); |
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/* extended mode register same as before with OCD default */ |
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host_load_cmd(ctrl, 10, 0x103, LOAD_MODE_CMD | (0xc << 24), |
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T_MRD_TCK * T_CK); |
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/* extended mode register same as before with OCD exit */ |
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host_load_cmd(ctrl, 11, 0x100, LOAD_MODE_CMD | (0x4 << 28), |
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140 * T_CK); |
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writel(CMD_VALID | NUMHOSTCMD(11), &ctrl->cmdissue); |
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/* start memory initialization */ |
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writel(INIT_START, &ctrl->memcon); |
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/* wait for all host cmds to be transmitted */ |
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wait_for_bit(__func__, &ctrl->cmdissue, CMD_VALID, false, |
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CONFIG_SYS_HZ, false); |
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/* inform all cmds issued, ready for normal operation */ |
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writel(INIT_START | INIT_DONE, &ctrl->memcon); |
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/* perform phy caliberation */ |
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if (ddr2_phy_calib_start()) |
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printf("ddr2: phy calib failed\n"); |
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} |
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phys_size_t ddr2_calculate_size(void) |
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{ |
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u32 temp; |
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temp = 1 << (COL_BITS + BA_BITS + ROW_BITS); |
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/* 16-bit data width between controller and DIMM */ |
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temp = temp * CS_BITS * (16 / 8); |
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return (phys_size_t)temp; |
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} |
@ -0,0 +1,148 @@ |
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/*
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* (c) 2015 Purna Chandra Mandal <purna.mandal@microchip.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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* |
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*/ |
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#ifndef __MICROCHIP_DDR2_REGS_H |
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#define __MICROCHIP_DDR2_REGS_H |
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#include <linux/bitops.h> |
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/* DDR2 Controller */ |
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struct ddr2_ctrl_regs { |
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u32 tsel; |
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u32 minlim; |
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u32 reqprd; |
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u32 mincmd; |
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u32 memcon; |
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u32 memcfg0; |
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u32 memcfg1; |
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u32 memcfg2; |
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u32 memcfg3; |
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u32 memcfg4; |
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u32 refcfg; |
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u32 pwrcfg; |
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u32 dlycfg0; |
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u32 dlycfg1; |
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u32 dlycfg2; |
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u32 dlycfg3; |
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u32 odtcfg; |
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u32 xfercfg; |
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u32 cmdissue; |
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u32 odtencfg; |
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u32 memwidth; |
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u32 unused[11]; |
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u32 cmd10[16]; |
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u32 cmd20[16]; |
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}; |
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/* Arbiter Config */ |
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#define MIN_LIM_WIDTH 5 |
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#define RQST_PERIOD_WIDTH 8 |
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#define MIN_CMDACPT_WIDTH 8 |
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/* Refresh Config */ |
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#define REFCNT_CLK(x) (x) |
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#define REFDLY_CLK(x) ((x) << 16) |
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#define MAX_PEND_REF(x) ((x) << 24) |
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|
|
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/* Power Config */ |
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#define PRECH_PWR_DN_ONLY(x) ((x) << 22) |
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#define SELF_REF_DLY(x) ((x) << 12) |
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#define PWR_DN_DLY(x) ((x) << 4) |
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#define EN_AUTO_SELF_REF(x) ((x) << 3) |
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#define EN_AUTO_PWR_DN(x) ((x) << 2) |
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#define ERR_CORR_EN(x) ((x) << 1) |
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#define ECC_EN(x) (x) |
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|
|
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/* Memory Width */ |
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#define HALF_RATE_MODE BIT(3) |
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|
||||||
|
/* Delay Config */ |
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#define ODTWLEN(x) ((x) << 20) |
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#define ODTRLEN(x) ((x) << 16) |
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#define ODTWDLY(x) ((x) << 12) |
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#define ODTRDLY(x) ((x) << 8) |
||||||
|
|
||||||
|
/* Xfer Config */ |
||||||
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#define BIG_ENDIAN(x) ((x) << 31) |
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#define MAX_BURST(x) ((x) << 24) |
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#define RDATENDLY(x) ((x) << 16) |
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#define NXDATAVDLY(x) ((x) << 4) |
||||||
|
#define NXTDATRQDLY(x) ((x) << 0) |
||||||
|
|
||||||
|
/* Host Commands */ |
||||||
|
#define IDLE_NOP 0x00ffffff |
||||||
|
#define PRECH_ALL_CMD 0x00fff401 |
||||||
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#define REF_CMD 0x00fff801 |
||||||
|
#define LOAD_MODE_CMD 0x00fff001 |
||||||
|
#define CKE_LOW 0x00ffeffe |
||||||
|
|
||||||
|
#define NUM_HOST_CMDS 12 |
||||||
|
|
||||||
|
/* Host CMD Issue */ |
||||||
|
#define CMD_VALID BIT(4) |
||||||
|
#define NUMHOSTCMD(x) (x) |
||||||
|
|
||||||
|
/* Memory Control */ |
||||||
|
#define INIT_DONE BIT(1) |
||||||
|
#define INIT_START BIT(0) |
||||||
|
|
||||||
|
/* Address Control */ |
||||||
|
#define EN_AUTO_PRECH 0 |
||||||
|
#define SB_PRI 1 |
||||||
|
|
||||||
|
/* DDR2 Phy Register */ |
||||||
|
struct ddr2_phy_regs { |
||||||
|
u32 scl_start; |
||||||
|
u32 unused1[2]; |
||||||
|
u32 scl_latency; |
||||||
|
u32 unused2[2]; |
||||||
|
u32 scl_config_1; |
||||||
|
u32 scl_config_2; |
||||||
|
u32 pad_ctrl; |
||||||
|
u32 dll_recalib; |
||||||
|
}; |
||||||
|
|
||||||
|
/* PHY PAD CONTROL */ |
||||||
|
#define ODT_SEL BIT(0) |
||||||
|
#define ODT_EN BIT(1) |
||||||
|
#define DRIVE_SEL(x) ((x) << 2) |
||||||
|
#define ODT_PULLDOWN(x) ((x) << 4) |
||||||
|
#define ODT_PULLUP(x) ((x) << 6) |
||||||
|
#define EXTRA_OEN_CLK(x) ((x) << 8) |
||||||
|
#define NOEXT_DLL BIT(9) |
||||||
|
#define DLR_DFT_WRCMD BIT(13) |
||||||
|
#define HALF_RATE BIT(14) |
||||||
|
#define DRVSTR_PFET(x) ((x) << 16) |
||||||
|
#define DRVSTR_NFET(x) ((x) << 20) |
||||||
|
#define RCVR_EN BIT(28) |
||||||
|
#define PREAMBLE_DLY(x) ((x) << 29) |
||||||
|
|
||||||
|
/* PHY DLL RECALIBRATE */ |
||||||
|
#define RECALIB_CNT(x) ((x) << 8) |
||||||
|
#define DISABLE_RECALIB(x) ((x) << 26) |
||||||
|
#define DELAY_START_VAL(x) ((x) << 28) |
||||||
|
|
||||||
|
/* PHY SCL CONFIG1 */ |
||||||
|
#define SCL_BURST8 BIT(0) |
||||||
|
#define SCL_DDR_CONNECTED BIT(1) |
||||||
|
#define SCL_RCAS_LAT(x) ((x) << 4) |
||||||
|
#define SCL_ODTCSWW BIT(24) |
||||||
|
|
||||||
|
/* PHY SCL CONFIG2 */ |
||||||
|
#define SCL_CSEN BIT(0) |
||||||
|
#define SCL_WCAS_LAT(x) ((x) << 8) |
||||||
|
|
||||||
|
/* PHY SCL Latency */ |
||||||
|
#define SCL_CAPCLKDLY(x) ((x) << 0) |
||||||
|
#define SCL_DDRCLKDLY(x) ((x) << 4) |
||||||
|
|
||||||
|
/* PHY SCL START */ |
||||||
|
#define SCL_START BIT(28) |
||||||
|
#define SCL_EN BIT(26) |
||||||
|
#define SCL_LUBPASS (BIT(1) | BIT(0)) |
||||||
|
|
||||||
|
#endif /* __MICROCHIP_DDR2_REGS_H */ |
@ -0,0 +1,65 @@ |
|||||||
|
/*
|
||||||
|
* (c) 2015 Purna Chandra Mandal <purna.mandal@microchip.com> |
||||||
|
* |
||||||
|
* SPDX-License-Identifier: GPL-2.0+ |
||||||
|
* |
||||||
|
*/ |
||||||
|
|
||||||
|
#ifndef __MICROCHIP_DDR2_TIMING_H |
||||||
|
#define __MICROCHIP_DDR2_TIMING_H |
||||||
|
|
||||||
|
/* MPLL freq is 400MHz */ |
||||||
|
#define T_CK 2500 /* 2500 psec */ |
||||||
|
#define T_CK_CTRL (T_CK * 2) |
||||||
|
|
||||||
|
/* Burst length in cycles */ |
||||||
|
#define BL 2 |
||||||
|
/* default CAS latency for all speed grades */ |
||||||
|
#define RL 5 |
||||||
|
/* default write latency for all speed grades = CL-1 */ |
||||||
|
#define WL 4 |
||||||
|
|
||||||
|
/* From Micron MT47H64M16HR-3 data sheet */ |
||||||
|
#define T_RFC_MIN 127500 /* psec */ |
||||||
|
#define T_WR 15000 /* psec */ |
||||||
|
#define T_RP 12500 /* psec */ |
||||||
|
#define T_RCD 12500 /* psec */ |
||||||
|
#define T_RRD 7500 /* psec */ |
||||||
|
/* T_RRD_TCK is minimum of 2 clk periods, regardless of freq */ |
||||||
|
#define T_RRD_TCK 2 |
||||||
|
#define T_WTR 7500 /* psec */ |
||||||
|
/* T_WTR_TCK is minimum of 2 clk periods, regardless of freq */ |
||||||
|
#define T_WTR_TCK 2 |
||||||
|
#define T_RTP 7500 /* psec */ |
||||||
|
#define T_RTP_TCK (BL / 2) |
||||||
|
#define T_XP_TCK 2 /* clocks */ |
||||||
|
#define T_CKE_TCK 3 /* clocks */ |
||||||
|
#define T_XSNR (T_RFC_MIN + 10000) /* psec */ |
||||||
|
#define T_DLLK 200 /* clocks */ |
||||||
|
#define T_RAS_MIN 45000 /* psec */ |
||||||
|
#define T_RC 57500 /* psec */ |
||||||
|
#define T_FAW 35000 /* psec */ |
||||||
|
#define T_MRD_TCK 2 /* clocks */ |
||||||
|
#define T_RFI 7800000 /* psec */ |
||||||
|
|
||||||
|
/* DDR Addressing */ |
||||||
|
#define COL_BITS 10 |
||||||
|
#define BA_BITS 3 |
||||||
|
#define ROW_BITS 13 |
||||||
|
#define CS_BITS 1 |
||||||
|
|
||||||
|
/* DDR Addressing scheme: {CS, ROW, BA, COL} */ |
||||||
|
#define COL_HI_RSHFT 0 |
||||||
|
#define COL_HI_MASK 0 |
||||||
|
#define COL_LO_MASK ((1 << COL_BITS) - 1) |
||||||
|
|
||||||
|
#define BA_RSHFT COL_BITS |
||||||
|
#define BA_MASK ((1 << BA_BITS) - 1) |
||||||
|
|
||||||
|
#define ROW_ADDR_RSHIFT (BA_RSHFT + BA_BITS) |
||||||
|
#define ROW_ADDR_MASK ((1 << ROW_BITS) - 1) |
||||||
|
|
||||||
|
#define CS_ADDR_RSHIFT 0 |
||||||
|
#define CS_ADDR_MASK 0 |
||||||
|
|
||||||
|
#endif /* __MICROCHIP_DDR2_TIMING_H */ |
Loading…
Reference in new issue