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dts: import stm32mp1 device tree from linux kernel

Browse Source 
This patch rebase the stm32mp1 device tree source from
linux kernel v4.18-rc1.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
lime2-spi
Patrick Delaunay 6 years ago committed by Tom Rini
parent 1f6ca3f42f
commit a674313c2c
11 changed files with 1676 additions and 844 deletions
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  1. 12
      arch/arm/dts/stm32mp15-ddr.dtsi
  2. 359
      arch/arm/dts/stm32mp157-pinctrl.dtsi
  3. 20
      arch/arm/dts/stm32mp157-u-boot.dtsi
  4. 380
      arch/arm/dts/stm32mp157.dtsi
  5. 2
      arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi
  6. 156
      arch/arm/dts/stm32mp157c-ed1.dts
  7. 935
      arch/arm/dts/stm32mp157c.dtsi
  8. 445
      include/dt-bindings/clock/stm32mp1-clks.h
  9. 6
      include/dt-bindings/pinctrl/stm32-pinfunc.h
  10. 97
      include/dt-bindings/reset-controller/stm32mp1-resets.h
  11. 108
      include/dt-bindings/reset/stm32mp1-resets.h

12
arch/arm/dts/stm32mp15-ddr.dtsi
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@ -13,12 +13,12 @@
reg = <0x5A003000 0x550 reg = <0x5A003000 0x550
0x5A004000 0x234>; 0x5A004000 0x234>;
clocks = <&rcc_clk AXIDCG>, clocks = <&rcc AXIDCG>,
<&rcc_clk DDRC1>, <&rcc DDRC1>,
<&rcc_clk DDRC2>, <&rcc DDRC2>,
<&rcc_clk DDRPHYC>, <&rcc DDRPHYC>,
<&rcc_clk DDRCAPB>, <&rcc DDRCAPB>,
<&rcc_clk DDRPHYCAPB>; <&rcc DDRPHYCAPB>;
clock-names = "axidcg", clock-names = "axidcg",
"ddrc1", "ddrc1",

359
arch/arm/dts/stm32mp157-pinctrl.dtsi
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@ -0,0 +1,359 @@
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* Copyright (C) STMicroelectronics 2017 - All Rights Reserved
* Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
*/
#include <dt-bindings/pinctrl/stm32-pinfunc.h>
/ {
soc {
pinctrl: pin-controller@50002000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "st,stm32mp157-pinctrl";
ranges = <0 0x50002000 0xa400>;
interrupt-parent = <&exti>;
st,syscfg = <&exti 0x60 0xff>;
pins-are-numbered;
gpioa: gpio@50002000 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x0 0x400>;
clocks = <&rcc GPIOA>;
st,bank-name = "GPIOA";
ngpios = <16>;
gpio-ranges = <&pinctrl 0 0 16>;
};
gpiob: gpio@50003000 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x1000 0x400>;
clocks = <&rcc GPIOB>;
st,bank-name = "GPIOB";
ngpios = <16>;
gpio-ranges = <&pinctrl 0 16 16>;
};
gpioc: gpio@50004000 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x2000 0x400>;
clocks = <&rcc GPIOC>;
st,bank-name = "GPIOC";
ngpios = <16>;
gpio-ranges = <&pinctrl 0 32 16>;
};
gpiod: gpio@50005000 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x3000 0x400>;
clocks = <&rcc GPIOD>;
st,bank-name = "GPIOD";
ngpios = <16>;
gpio-ranges = <&pinctrl 0 48 16>;
};
gpioe: gpio@50006000 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x4000 0x400>;
clocks = <&rcc GPIOE>;
st,bank-name = "GPIOE";
ngpios = <16>;
gpio-ranges = <&pinctrl 0 64 16>;
};
gpiof: gpio@50007000 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x5000 0x400>;
clocks = <&rcc GPIOF>;
st,bank-name = "GPIOF";
ngpios = <16>;
gpio-ranges = <&pinctrl 0 80 16>;
};
gpiog: gpio@50008000 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x6000 0x400>;
clocks = <&rcc GPIOG>;
st,bank-name = "GPIOG";
ngpios = <16>;
gpio-ranges = <&pinctrl 0 96 16>;
};
gpioh: gpio@50009000 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x7000 0x400>;
clocks = <&rcc GPIOH>;
st,bank-name = "GPIOH";
ngpios = <16>;
gpio-ranges = <&pinctrl 0 112 16>;
};
gpioi: gpio@5000a000 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x8000 0x400>;
clocks = <&rcc GPIOI>;
st,bank-name = "GPIOI";
ngpios = <16>;
gpio-ranges = <&pinctrl 0 128 16>;
};
gpioj: gpio@5000b000 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x9000 0x400>;
clocks = <&rcc GPIOJ>;
st,bank-name = "GPIOJ";
ngpios = <16>;
gpio-ranges = <&pinctrl 0 144 16>;
};
gpiok: gpio@5000c000 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0xa000 0x400>;
clocks = <&rcc GPIOK>;
st,bank-name = "GPIOK";
ngpios = <8>;
gpio-ranges = <&pinctrl 0 160 8>;
};
cec_pins_a: cec-0 {
pins {
pinmux = <STM32_PINMUX('A', 15, AF4)>;
bias-disable;
drive-open-drain;
slew-rate = <0>;
};
};
i2c1_pins_a: i2c1-0 {
pins {
pinmux = <STM32_PINMUX('D', 12, AF5)>, /* I2C1_SCL */
<STM32_PINMUX('F', 15, AF5)>; /* I2C1_SDA */
bias-disable;
drive-open-drain;
slew-rate = <0>;
};
};
i2c2_pins_a: i2c2-0 {
pins {
pinmux = <STM32_PINMUX('H', 4, AF4)>, /* I2C2_SCL */
<STM32_PINMUX('H', 5, AF4)>; /* I2C2_SDA */
bias-disable;
drive-open-drain;
slew-rate = <0>;
};
};
i2c5_pins_a: i2c5-0 {
pins {
pinmux = <STM32_PINMUX('A', 11, AF4)>, /* I2C5_SCL */
<STM32_PINMUX('A', 12, AF4)>; /* I2C5_SDA */
bias-disable;
drive-open-drain;
slew-rate = <0>;
};
};
pwm2_pins_a: pwm2-0 {
pins {
pinmux = <STM32_PINMUX('A', 3, AF1)>; /* TIM2_CH4 */
bias-pull-down;
drive-push-pull;
slew-rate = <0>;
};
};
pwm8_pins_a: pwm8-0 {
pins {
pinmux = <STM32_PINMUX('I', 2, AF3)>; /* TIM8_CH4 */
bias-pull-down;
drive-push-pull;
slew-rate = <0>;
};
};
pwm12_pins_a: pwm12-0 {
pins {
pinmux = <STM32_PINMUX('H', 6, AF2)>; /* TIM12_CH1 */
bias-pull-down;
drive-push-pull;
slew-rate = <0>;
};
};
qspi_clk_pins_a: qspi-clk-0 {
pins {
pinmux = <STM32_PINMUX('F', 10, AF9)>; /* QSPI_CLK */
bias-disable;
drive-push-pull;
slew-rate = <3>;
};
};
qspi_bk1_pins_a: qspi-bk1-0 {
pins1 {
pinmux = <STM32_PINMUX('F', 8, AF10)>, /* QSPI_BK1_IO0 */
<STM32_PINMUX('F', 9, AF10)>, /* QSPI_BK1_IO1 */
<STM32_PINMUX('F', 7, AF9)>, /* QSPI_BK1_IO2 */
<STM32_PINMUX('F', 6, AF9)>; /* QSPI_BK1_IO3 */
bias-disable;
drive-push-pull;
slew-rate = <3>;
};
pins2 {
pinmux = <STM32_PINMUX('B', 6, AF10)>; /* QSPI_BK1_NCS */
bias-pull-up;
drive-push-pull;
slew-rate = <3>;
};
};
qspi_bk2_pins_a: qspi-bk2-0 {
pins1 {
pinmux = <STM32_PINMUX('H', 2, AF9)>, /* QSPI_BK2_IO0 */
<STM32_PINMUX('H', 3, AF9)>, /* QSPI_BK2_IO1 */
<STM32_PINMUX('G', 10, AF11)>, /* QSPI_BK2_IO2 */
<STM32_PINMUX('G', 7, AF11)>; /* QSPI_BK2_IO3 */
bias-disable;
drive-push-pull;
slew-rate = <3>;
};
pins2 {
pinmux = <STM32_PINMUX('C', 0, AF10)>; /* QSPI_BK2_NCS */
bias-pull-up;
drive-push-pull;
slew-rate = <3>;
};
};
sdmmc1_b4_pins_a: sdmmc1-b4@0 {
pins {
pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
<STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
<STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */
<STM32_PINMUX('C', 11, AF12)>, /* SDMMC1_D3 */
<STM32_PINMUX('C', 12, AF12)>, /* SDMMC1_CK */
<STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
slew-rate = <3>;
drive-push-pull;
bias-disable;
};
};
sdmmc1_dir_pins_a: sdmmc1-dir@0 {
pins {
pinmux = <STM32_PINMUX('F', 2, AF11)>, /* SDMMC1_D0DIR */
<STM32_PINMUX('C', 7, AF8)>, /* SDMMC1_D123DIR */
<STM32_PINMUX('B', 9, AF11)>, /* SDMMC1_CDIR */
<STM32_PINMUX('E', 4, AF8)>; /* SDMMC1_CKIN */
slew-rate = <3>;
drive-push-pull;
bias-pull-up;
};
};
sdmmc2_b4_pins_a: sdmmc2-b4@0 {
pins {
pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */
<STM32_PINMUX('B', 15, AF9)>, /* SDMMC2_D1 */
<STM32_PINMUX('B', 3, AF9)>, /* SDMMC2_D2 */
<STM32_PINMUX('B', 4, AF9)>, /* SDMMC2_D3 */
<STM32_PINMUX('E', 3, AF9)>, /* SDMMC2_CK */
<STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */
slew-rate = <3>;
drive-push-pull;
bias-pull-up;
};
};
sdmmc2_d47_pins_a: sdmmc2-d47@0 {
pins {
pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */
<STM32_PINMUX('A', 9, AF10)>, /* SDMMC2_D5 */
<STM32_PINMUX('E', 5, AF9)>, /* SDMMC2_D6 */
<STM32_PINMUX('D', 3, AF9)>; /* SDMMC2_D7 */
slew-rate = <3>;
drive-push-pull;
bias-pull-up;
};
};
uart4_pins_a: uart4-0 {
pins1 {
pinmux = <STM32_PINMUX('G', 11, AF6)>; /* UART4_TX */
bias-disable;
drive-push-pull;
slew-rate = <0>;
};
pins2 {
pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */
bias-disable;
};
};
};
pinctrl_z: pin-controller-z@54004000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "st,stm32mp157-z-pinctrl";
ranges = <0 0x54004000 0x400>;
pins-are-numbered;
interrupt-parent = <&exti>;
st,syscfg = <&exti 0x60 0xff>;
gpioz: gpio@54004000 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0 0x400>;
clocks = <&rcc GPIOZ>;
st,bank-name = "GPIOZ";
st,bank-ioport = <11>;
ngpios = <8>;
gpio-ranges = <&pinctrl_z 0 400 8>;
};
i2c4_pins_a: i2c4-0 {
pins {
pinmux = <STM32_PINMUX('Z', 4, AF6)>, /* I2C4_SCL */
<STM32_PINMUX('Z', 5, AF6)>; /* I2C4_SDA */
bias-disable;
drive-open-drain;
slew-rate = <0>;
};
};
};
};
};

20
arch/arm/dts/stm32mp157-u-boot.dtsi
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@ -29,13 +29,13 @@
soc { soc {
u-boot,dm-pre-reloc; u-boot,dm-pre-reloc;
};
stgen: stgen@5C008000 { stgen: stgen@5C008000 {
compatible = "st,stm32-stgen"; compatible = "st,stm32-stgen";
reg = <0x5C008000 0x1000>; reg = <0x5C008000 0x1000>;
status = "okay"; status = "okay";
u-boot,dm-pre-reloc; u-boot,dm-pre-reloc;
};
}; };
}; };
@ -63,14 +63,6 @@
u-boot,dm-pre-reloc; u-boot,dm-pre-reloc;
}; };
&rcc_clk {
u-boot,dm-pre-reloc;
};
&rcc_rst {
u-boot,dm-pre-reloc;
};
&rcc_reboot { &rcc_reboot {
u-boot,dm-pre-reloc; u-boot,dm-pre-reloc;
}; };

380
arch/arm/dts/stm32mp157.dtsi
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@ -1,380 +0,0 @@
/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
/*
* Copyright (C) STMicroelectronics 2018 - All Rights Reserved
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/stm32mp1-clks.h>
#include <dt-bindings/reset-controller/stm32mp1-resets.h>
/ {
#address-cells = <1>;
#size-cells = <1>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@0 {
compatible = "arm,cortex-a7";
device_type = "cpu";
reg = <0>;
};
cpu1: cpu@1 {
compatible = "arm,cortex-a7";
device_type = "cpu";
reg = <1>;
};
};
aliases {
serial3 = &uart4;
};
intc: interrupt-controller@a0021000 {
compatible = "arm,cortex-a7-gic";
#interrupt-cells = <3>;
interrupt-controller;
reg = <0xa0021000 0x1000>,
<0xa0022000 0x2000>;
};
clocks {
clk_hse: clk-hse {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <24000000>;
};
clk_hsi: clk-hsi {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <64000000>;
};
clk_lse: clk-lse {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <32768>;
};
clk_lsi: clk-lsi {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <32000>;
};
clk_csi: clk-csi {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <4000000>;
};
};
soc {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
interrupt-parent = <&intc>;
ranges;
uart4: serial@40010000 {
compatible = "st,stm32h7-uart";
reg = <0x40010000 0x400>;
clocks = <&rcc_clk UART4_K>;
status = "disabled";
};
sdmmc3: sdmmc@48004000 {
compatible = "st,stm32-sdmmc2";
reg = <0x48004000 0x400>, <0x48005000 0x400>;
reg-names = "sdmmc", "delay";
interrupts = <GIC_SPI 137 IRQ_TYPE_NONE>;
clocks = <&rcc_clk SDMMC3_K>;
resets = <&rcc_rst SDMMC3_R>;
st,idma = <1>;
cap-sd-highspeed;
cap-mmc-highspeed;
max-frequency = <120000000>;
status = "disabled";
};
rcc: rcc@50000000 {
compatible = "syscon", "simple-mfd";
reg = <0x50000000 0x1000>;
rcc_clk: rcc-clk@50000000 {
#clock-cells = <1>;
compatible = "st,stm32mp1-rcc-clk";
};
rcc_rst: rcc-reset@50000000 {
#reset-cells = <1>;
compatible = "st,stm32mp1-rcc-rst";
};
rcc_reboot: rcc-reboot@50000000 {
compatible = "syscon-reboot";
regmap = <&rcc>;
offset = <0x404>;
mask = <0x1>;
};
};
pwr: pwr@50001000 {
compatible = "st,stm32mp1-pwr", "st,stm32-pwr", "syscon", "simple-mfd";
reg = <0x50001000 0x400>;
system-power-controller;
interrupts = <GIC_SPI 149 IRQ_TYPE_NONE>;
st,sysrcc = <&rcc>;
clocks = <&rcc_clk PLL2_R>;
clock-names = "phyclk";
pwr-regulators@c {
compatible = "st,stm32mp1,pwr-reg";
st,tzcr = <&rcc 0x0 0x1>;
reg11: reg11 {
regulator-name = "reg11";
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1100000>;
};
reg18: reg18 {
regulator-name = "reg18";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
usb33: usb33 {
regulator-name = "usb33";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
};
};
vrefbuf: vrefbuf@50025000 {
compatible = "st,stm32-vrefbuf";
reg = <0x50025000 0x8>;
regulator-min-microvolt = <1500000>;
regulator-max-microvolt = <2500000>;
clocks = <&rcc_clk VREF>;
status = "disabled";
};
pinctrl: pin-controller {
compatible = "st,stm32mp157-pinctrl";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x50002000 0xa400>;
pins-are-numbered;
gpioa: gpio@50002000 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x0 0x400>;
clocks = <&rcc_clk GPIOA>;
st,bank-name = "GPIOA";
ngpios = <16>;
gpio-ranges = <&pinctrl 0 0 16>;
status = "disabled";
};
gpiob: gpio@50003000 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x1000 0x400>;
clocks = <&rcc_clk GPIOB>;
st,bank-name = "GPIOB";
ngpios = <16>;
gpio-ranges = <&pinctrl 0 16 16>;
status = "disabled";
};
gpioc: gpio@50004000 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x2000 0x400>;
clocks = <&rcc_clk GPIOC>;
st,bank-name = "GPIOC";
ngpios = <16>;
gpio-ranges = <&pinctrl 0 32 16>;
status = "disabled";
};
gpiod: gpio@50005000 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x3000 0x400>;
clocks = <&rcc_clk GPIOD>;
st,bank-name = "GPIOD";
ngpios = <16>;
gpio-ranges = <&pinctrl 0 48 16>;
status = "disabled";
};
gpioe: gpio@50006000 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x4000 0x400>;
clocks = <&rcc_clk GPIOE>;
st,bank-name = "GPIOE";
ngpios = <16>;
gpio-ranges = <&pinctrl 0 64 16>;
status = "disabled";
};
gpiof: gpio@50007000 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x5000 0x400>;
clocks = <&rcc_clk GPIOF>;
st,bank-name = "GPIOF";
ngpios = <16>;
gpio-ranges = <&pinctrl 0 80 16>;
status = "disabled";
};
gpiog: gpio@50008000 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x6000 0x400>;
clocks = <&rcc_clk GPIOG>;
st,bank-name = "GPIOG";
ngpios = <16>;
gpio-ranges = <&pinctrl 0 96 16>;
status = "disabled";
};
gpioh: gpio@50009000 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x7000 0x400>;
clocks = <&rcc_clk GPIOH>;
st,bank-name = "GPIOH";
ngpios = <16>;
gpio-ranges = <&pinctrl 0 112 16>;
status = "disabled";
};
gpioi: gpio@5000a000 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x8000 0x400>;
clocks = <&rcc_clk GPIOI>;
st,bank-name = "GPIOI";
ngpios = <16>;
gpio-ranges = <&pinctrl 0 128 16>;
status = "disabled";
};
gpioj: gpio@5000b000 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x9000 0x400>;
clocks = <&rcc_clk GPIOJ>;
st,bank-name = "GPIOJ";
ngpios = <16>;
gpio-ranges = <&pinctrl 0 144 16>;
status = "disabled";
};
gpiok: gpio@5000c000 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0xa000 0x400>;
clocks = <&rcc_clk GPIOK>;
st,bank-name = "GPIOK";
ngpios = <8>;
gpio-ranges = <&pinctrl 0 160 8>;
status = "disabled";
};
};
pinctrl_z: pin-controller-z {
compatible = "st,stm32mp157-z-pinctrl";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x54004000 0x400>;
pins-are-numbered;
gpioz: gpio@54004000 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0 0x400>;
clocks = <&rcc_clk GPIOZ>;
st,bank-name = "GPIOZ";
st,bank-ioport = <11>;
ngpios = <8>;
gpio-ranges = <&pinctrl_z 0 400 8>;
status = "disabled";
};
};
sdmmc1: sdmmc@58005000 {
compatible = "st,stm32-sdmmc2";
reg = <0x58005000 0x1000>, <0x58006000 0x1000>;
reg-names = "sdmmc", "delay";
clocks = <&rcc_clk SDMMC1_K>;
resets = <&rcc_rst SDMMC1_R>;
st,idma = <1>;
cap-sd-highspeed;
cap-mmc-highspeed;
max-frequency = <120000000>;
status = "disabled";
};
sdmmc2: sdmmc@58007000 {
compatible = "st,stm32-sdmmc2";
reg = <0x58007000 0x1000>, <0x58008000 0x1000>;
reg-names = "sdmmc", "delay";
interrupts = <GIC_SPI 124 IRQ_TYPE_NONE>;
clocks = <&rcc_clk SDMMC2_K>;
resets = <&rcc_rst SDMMC2_R>;
st,idma = <1>;
cap-sd-highspeed;
cap-mmc-highspeed;
max-frequency = <120000000>;
status = "disabled";
};
i2c4: i2c@5c002000 {
compatible = "st,stm32f7-i2c";
reg = <0x5c002000 0x400>;
interrupt-names = "event", "error", "wakeup";
clocks = <&rcc_clk I2C4_K>;
resets = <&rcc_rst I2C4_R>;
#address-cells = <1>;
#size-cells = <0>;
wakeup-source;
status = "disabled";
};
};
};

2
arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi
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@ -45,7 +45,7 @@
}; };
/* CLOCK init */ /* CLOCK init */
&rcc_clk { &rcc {
st,clksrc = < st,clksrc = <
CLK_MPU_PLL1P CLK_MPU_PLL1P
CLK_AXI_PLL2P CLK_AXI_PLL2P

156
arch/arm/dts/stm32mp157c-ed1.dts
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@ -1,27 +1,24 @@
/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */ // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/* /*
* Copyright (C) STMicroelectronics 2017 - All Rights Reserved * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
* Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics. * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
*/ */
/dts-v1/; /dts-v1/;
#include "stm32mp157.dtsi" #include "stm32mp157c.dtsi"
#include "stm32mp157-pinctrl.dtsi"
#include <dt-bindings/gpio/gpio.h> #include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/pinctrl/stm32-pinfunc.h>
#include <dt-bindings/mfd/st,stpmu1.h> #include <dt-bindings/mfd/st,stpmu1.h>
/ { / {
model = "STMicroelectronics STM32MP157C pmic eval daughter"; model = "STMicroelectronics STM32MP157C eval daughter";
compatible = "st,stm32mp157c-ed1", "st,stm32mp157"; compatible = "st,stm32mp157c-ed1", "st,stm32mp157";
chosen { chosen {
bootargs = "earlyprintk console=ttyS3,115200 root=/dev/ram";
stdout-path = "serial3:115200n8"; stdout-path = "serial3:115200n8";
}; };
memory { memory@c0000000 {
reg = <0xC0000000 0x40000000>; reg = <0xC0000000 0x40000000>;
}; };
@ -39,129 +36,14 @@
}; };
}; };
&gpioa { &rng1 {
status = "okay";
};
&gpiob {
status = "okay";
};
&gpioc {
status = "okay";
};
&gpiod {
status = "okay";
};
&gpioe {
status = "okay";
};
&gpiof {
status = "okay";
};
&gpiog {
status = "okay"; status = "okay";
}; };
&gpioh { &timers6 {
status = "okay"; status = "okay";
}; timer@5 {
status = "okay";
&gpioi {
status = "okay";
};
&gpioj {
status = "okay";
};
&gpiok {
status = "okay";
};
&gpioz {
status = "okay";
};
&pinctrl {
uart4_pins_a: uart4@0 {
pins1 {
pinmux = <STM32_PINMUX('G', 11, AF6)>; /* UART4_TX */
bias-disable;
drive-push-pull;
slew-rate = <0>;
};
pins2 {
pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */
bias-disable;
};
};
sdmmc1_b4_pins_a: sdmmc1-b4@0 {
pins {
pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
<STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
<STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */
<STM32_PINMUX('C', 11, AF12)>, /* SDMMC1_D3 */
<STM32_PINMUX('C', 12, AF12)>, /* SDMMC1_CK */
<STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
slew-rate = <3>;
drive-push-pull;
bias-disable;
};
};
sdmmc1_dir_pins_a: sdmmc1-dir@0 {
pins {
pinmux = <STM32_PINMUX('F', 2, AF11)>, /* SDMMC1_D0DIR */
<STM32_PINMUX('C', 7, AF8)>, /* SDMMC1_D123DIR */
<STM32_PINMUX('B', 9, AF11)>, /* SDMMC1_CDIR */
<STM32_PINMUX('E', 4, AF8)>; /* SDMMC1_CKIN */
slew-rate = <3>;
drive-push-pull;
bias-pull-up;
};
};
sdmmc2_b4_pins_a: sdmmc2-b4@0 {
pins {
pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */
<STM32_PINMUX('B', 15, AF9)>, /* SDMMC2_D1 */
<STM32_PINMUX('B', 3, AF9)>, /* SDMMC2_D2 */
<STM32_PINMUX('B', 4, AF9)>, /* SDMMC2_D3 */
<STM32_PINMUX('E', 3, AF9)>, /* SDMMC2_CK */
<STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */
slew-rate = <3>;
drive-push-pull;
bias-pull-up;
};
};
sdmmc2_d47_pins_a: sdmmc2-d47@0 {
pins {
pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */
<STM32_PINMUX('A', 9, AF10)>, /* SDMMC2_D5 */
<STM32_PINMUX('E', 5, AF9)>, /* SDMMC2_D6 */
<STM32_PINMUX('D', 3, AF9)>; /* SDMMC2_D7 */
slew-rate = <3>;
drive-push-pull;
bias-pull-up;
};
};
};
&pinctrl_z {
i2c4_pins_a: i2c4@0 {
pins {
pinmux = <STM32_PINMUX('Z', 4, AF6)>, /* I2C4_SCL */
<STM32_PINMUX('Z', 5, AF6)>; /* I2C4_SDA */
bias-disable;
drive-open-drain;
slew-rate = <0>;
};
}; };
}; };
@ -439,8 +321,11 @@
}; };
}; };
&pwr {
pwr-supply = <&vdd>;
};
&sdmmc1 { &sdmmc1 {
pinctrl-names = "default";
pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_a>; pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_a>;
broken-cd; broken-cd;
st,dirpol; st,dirpol;
@ -458,7 +343,6 @@
}; };
&sdmmc2 { &sdmmc2 {
pinctrl-names = "default";
pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_a>; pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_a>;
non-removable; non-removable;
no-sd; no-sd;
@ -466,6 +350,8 @@
st,dirpol; st,dirpol;
st,negedge; st,negedge;
bus-width = <8>; bus-width = <8>;
vmmc-supply = <&v3v3>;
vqmmc-supply = <&vdd>;
status = "okay"; status = "okay";
}; };
@ -474,3 +360,15 @@
pinctrl-0 = <&uart4_pins_a>; pinctrl-0 = <&uart4_pins_a>;
status = "okay"; status = "okay";
}; };
&usbphyc_port0 {
phy-supply = <&vdd_usb>;
vdda1v1-supply = <&reg11>;
vdda1v8-supply = <&reg18>;
};
&usbphyc_port1 {
phy-supply = <&vdd_usb>;
vdda1v1-supply = <&reg11>;
vdda1v8-supply = <&reg18>;
};

935
arch/arm/dts/stm32mp157c.dtsi
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@ -0,0 +1,935 @@
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* Copyright (C) STMicroelectronics 2017 - All Rights Reserved
* Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/stm32mp1-clks.h>
#include <dt-bindings/reset/stm32mp1-resets.h>
/ {
#address-cells = <1>;
#size-cells = <1>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@0 {
compatible = "arm,cortex-a7";
device_type = "cpu";
reg = <0>;
};
cpu1: cpu@1 {
compatible = "arm,cortex-a7";
device_type = "cpu";
reg = <1>;
};
};
psci {
compatible = "arm,psci";
method = "smc";
cpu_off = <0x84000002>;
cpu_on = <0x84000003>;
};
aliases {
gpio0 = &gpioa;
gpio1 = &gpiob;
gpio2 = &gpioc;
gpio3 = &gpiod;
gpio4 = &gpioe;
gpio5 = &gpiof;
gpio6 = &gpiog;
gpio7 = &gpioh;
gpio8 = &gpioi;
gpio9 = &gpioj;
gpio10 = &gpiok;
serial0 = &usart1;
serial1 = &usart2;
serial2 = &usart3;
serial3 = &uart4;
serial4 = &uart5;
serial5 = &usart6;
serial6 = &uart7;
serial7 = &uart8;
};
intc: interrupt-controller@a0021000 {
compatible = "arm,cortex-a7-gic";
#interrupt-cells = <3>;
interrupt-controller;
reg = <0xa0021000 0x1000>,
<0xa0022000 0x2000>;
};
timer {
compatible = "arm,armv7-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
interrupt-parent = <&intc>;
};
clocks {
clk_hse: clk-hse {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <24000000>;
};
clk_hsi: clk-hsi {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <64000000>;
};
clk_lse: clk-lse {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <32768>;
};
clk_lsi: clk-lsi {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <32000>;
};
clk_csi: clk-csi {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <4000000>;
};
};
soc {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
interrupt-parent = <&intc>;
ranges;
timers2: timer@40000000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "st,stm32-timers";
reg = <0x40000000 0x400>;
clocks = <&rcc TIM2_K>;
clock-names = "int";
status = "disabled";
pwm {
compatible = "st,stm32-pwm";
status = "disabled";
};
timer@1 {
compatible = "st,stm32h7-timer-trigger";
reg = <1>;
status = "disabled";
};
};
timers3: timer@40001000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "st,stm32-timers";
reg = <0x40001000 0x400>;
clocks = <&rcc TIM3_K>;
clock-names = "int";
status = "disabled";
pwm {
compatible = "st,stm32-pwm";
status = "disabled";
};
timer@2 {
compatible = "st,stm32h7-timer-trigger";
reg = <2>;
status = "disabled";
};
};
timers4: timer@40002000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "st,stm32-timers";
reg = <0x40002000 0x400>;
clocks = <&rcc TIM4_K>;
clock-names = "int";
status = "disabled";
pwm {
compatible = "st,stm32-pwm";
status = "disabled";
};
timer@3 {
compatible = "st,stm32h7-timer-trigger";
reg = <3>;
status = "disabled";
};
};
timers5: timer@40003000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "st,stm32-timers";
reg = <0x40003000 0x400>;
clocks = <&rcc TIM5_K>;
clock-names = "int";
status = "disabled";
pwm {
compatible = "st,stm32-pwm";
status = "disabled";
};
timer@4 {
compatible = "st,stm32h7-timer-trigger";
reg = <4>;
status = "disabled";
};
};
timers6: timer@40004000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "st,stm32-timers";
reg = <0x40004000 0x400>;
clocks = <&rcc TIM6_K>;
clock-names = "int";
status = "disabled";
timer@5 {
compatible = "st,stm32h7-timer-trigger";
reg = <5>;
status = "disabled";
};
};
timers7: timer@40005000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "st,stm32-timers";
reg = <0x40005000 0x400>;
clocks = <&rcc TIM7_K>;
clock-names = "int";
status = "disabled";
timer@6 {
compatible = "st,stm32h7-timer-trigger";
reg = <6>;
status = "disabled";
};
};
timers12: timer@40006000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "st,stm32-timers";
reg = <0x40006000 0x400>;
clocks = <&rcc TIM12_K>;
clock-names = "int";
status = "disabled";
pwm {
compatible = "st,stm32-pwm";
status = "disabled";
};
timer@11 {
compatible = "st,stm32h7-timer-trigger";
reg = <11>;
status = "disabled";
};
};
timers13: timer@40007000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "st,stm32-timers";
reg = <0x40007000 0x400>;
clocks = <&rcc TIM13_K>;
clock-names = "int";
status = "disabled";
pwm {
compatible = "st,stm32-pwm";
status = "disabled";
};
timer@12 {
compatible = "st,stm32h7-timer-trigger";
reg = <12>;
status = "disabled";
};
};
timers14: timer@40008000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "st,stm32-timers";
reg = <0x40008000 0x400>;
clocks = <&rcc TIM14_K>;
clock-names = "int";
status = "disabled";
pwm {
compatible = "st,stm32-pwm";
status = "disabled";
};
timer@13 {
compatible = "st,stm32h7-timer-trigger";
reg = <13>;
status = "disabled";
};
};
lptimer1: timer@40009000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "st,stm32-lptimer";
reg = <0x40009000 0x400>;
clocks = <&rcc LPTIM1_K>;
clock-names = "mux";
status = "disabled";
pwm {
compatible = "st,stm32-pwm-lp";
#pwm-cells = <3>;
status = "disabled";
};
trigger@0 {
compatible = "st,stm32-lptimer-trigger";
reg = <0>;
status = "disabled";
};
counter {
compatible = "st,stm32-lptimer-counter";
status = "disabled";
};
};
usart2: serial@4000e000 {
compatible = "st,stm32h7-uart";
reg = <0x4000e000 0x400>;
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc USART2_K>;
status = "disabled";
};
usart3: serial@4000f000 {
compatible = "st,stm32h7-uart";
reg = <0x4000f000 0x400>;
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc USART3_K>;
status = "disabled";
};
uart4: serial@40010000 {
compatible = "st,stm32h7-uart";
reg = <0x40010000 0x400>;
interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc UART4_K>;
status = "disabled";
};
uart5: serial@40011000 {
compatible = "st,stm32h7-uart";
reg = <0x40011000 0x400>;
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc UART5_K>;
status = "disabled";
};
i2c1: i2c@40012000 {
compatible = "st,stm32f7-i2c";
reg = <0x40012000 0x400>;
interrupt-names = "event", "error";
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc I2C1_K>;
resets = <&rcc I2C1_R>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c2: i2c@40013000 {
compatible = "st,stm32f7-i2c";
reg = <0x40013000 0x400>;
interrupt-names = "event", "error";
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc I2C2_K>;
resets = <&rcc I2C2_R>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c3: i2c@40014000 {
compatible = "st,stm32f7-i2c";
reg = <0x40014000 0x400>;
interrupt-names = "event", "error";
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc I2C3_K>;
resets = <&rcc I2C3_R>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c5: i2c@40015000 {
compatible = "st,stm32f7-i2c";
reg = <0x40015000 0x400>;
interrupt-names = "event", "error";
interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc I2C5_K>;
resets = <&rcc I2C5_R>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
cec: cec@40016000 {
compatible = "st,stm32-cec";
reg = <0x40016000 0x400>;
interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc CEC_K>, <&clk_lse>;
clock-names = "cec", "hdmi-cec";
status = "disabled";
};
dac: dac@40017000 {
compatible = "st,stm32h7-dac-core";
reg = <0x40017000 0x400>;
clocks = <&rcc DAC12>;
clock-names = "pclk";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
dac1: dac@1 {
compatible = "st,stm32-dac";
#io-channels-cells = <1>;
reg = <1>;
status = "disabled";
};
dac2: dac@2 {
compatible = "st,stm32-dac";
#io-channels-cells = <1>;
reg = <2>;
status = "disabled";
};
};
uart7: serial@40018000 {
compatible = "st,stm32h7-uart";
reg = <0x40018000 0x400>;
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc UART7_K>;
status = "disabled";
};
uart8: serial@40019000 {
compatible = "st,stm32h7-uart";
reg = <0x40019000 0x400>;
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc UART8_K>;
status = "disabled";
};
timers1: timer@44000000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "st,stm32-timers";
reg = <0x44000000 0x400>;
clocks = <&rcc TIM1_K>;
clock-names = "int";
status = "disabled";
pwm {
compatible = "st,stm32-pwm";
status = "disabled";
};
timer@0 {
compatible = "st,stm32h7-timer-trigger";
reg = <0>;
status = "disabled";
};
};
timers8: timer@44001000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "st,stm32-timers";
reg = <0x44001000 0x400>;
clocks = <&rcc TIM8_K>;
clock-names = "int";
status = "disabled";
pwm {
compatible = "st,stm32-pwm";
status = "disabled";
};
timer@7 {
compatible = "st,stm32h7-timer-trigger";
reg = <7>;
status = "disabled";
};
};
usart6: serial@44003000 {
compatible = "st,stm32h7-uart";
reg = <0x44003000 0x400>;
interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc USART6_K>;
status = "disabled";
};
timers15: timer@44006000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "st,stm32-timers";
reg = <0x44006000 0x400>;
clocks = <&rcc TIM15_K>;
clock-names = "int";
status = "disabled";
pwm {
compatible = "st,stm32-pwm";
status = "disabled";
};
timer@14 {
compatible = "st,stm32h7-timer-trigger";
reg = <14>;
status = "disabled";
};
};
timers16: timer@44007000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "st,stm32-timers";
reg = <0x44007000 0x400>;
clocks = <&rcc TIM16_K>;
clock-names = "int";
status = "disabled";
pwm {
compatible = "st,stm32-pwm";
status = "disabled";
};
timer@15 {
compatible = "st,stm32h7-timer-trigger";
reg = <15>;
status = "disabled";
};
};
timers17: timer@44008000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "st,stm32-timers";
reg = <0x44008000 0x400>;
clocks = <&rcc TIM17_K>;
clock-names = "int";
status = "disabled";
pwm {
compatible = "st,stm32-pwm";
status = "disabled";
};
timer@16 {
compatible = "st,stm32h7-timer-trigger";
reg = <16>;
status = "disabled";
};
};
dma1: dma@48000000 {
compatible = "st,stm32-dma";
reg = <0x48000000 0x400>;
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc DMA1>;
#dma-cells = <4>;
st,mem2mem;
dma-requests = <8>;
};
dma2: dma@48001000 {
compatible = "st,stm32-dma";
reg = <0x48001000 0x400>;
interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc DMA2>;
#dma-cells = <4>;
st,mem2mem;
dma-requests = <8>;
};
dmamux1: dma-router@48002000 {
compatible = "st,stm32h7-dmamux";
reg = <0x48002000 0x1c>;
#dma-cells = <3>;
dma-requests = <128>;
dma-masters = <&dma1 &dma2>;
dma-channels = <16>;
clocks = <&rcc DMAMUX>;
};
sdmmc3: sdmmc@48004000 {
compatible = "st,stm32-sdmmc2";
reg = <0x48004000 0x400>, <0x48005000 0x400>;
reg-names = "sdmmc", "delay";
interrupts = <GIC_SPI 137 IRQ_TYPE_NONE>;
clocks = <&rcc SDMMC3_K>;
resets = <&rcc SDMMC3_R>;
st,idma = <1>;
cap-sd-highspeed;
cap-mmc-highspeed;
max-frequency = <120000000>;
status = "disabled";
};
rcc: rcc@50000000 {
compatible = "st,stm32mp1-rcc", "syscon";
reg = <0x50000000 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
};
rcc_reboot: rcc-reboot@50000000 {
compatible = "syscon-reboot";
regmap = <&rcc>;
offset = <0x404>;
mask = <0x1>;
};
pwr: pwr@50001000 {
compatible = "st,stm32mp1-pwr", "st,stm32-pwr", "syscon", "simple-mfd";
reg = <0x50001000 0x400>;
system-power-controller;
interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
st,sysrcc = <&rcc>;
clocks = <&rcc PLL2_R>;
clock-names = "phyclk";
pwr-regulators@c {
compatible = "st,stm32mp1,pwr-reg";
st,tzcr = <&rcc 0x0 0x1>;
reg11: reg11 {
regulator-name = "reg11";
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1100000>;
};
reg18: reg18 {
regulator-name = "reg18";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
usb33: usb33 {
regulator-name = "usb33";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
};
};
exti: interrupt-controller@5000d000 {
compatible = "st,stm32mp1-exti", "syscon";
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x5000d000 0x400>;
};
syscfg: system-config@50020000 {
compatible = "st,stm32-syscfg", "syscon";
reg = <0x50020000 0x400>;
};
lptimer2: timer@50021000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "st,stm32-lptimer";
reg = <0x50021000 0x400>;
clocks = <&rcc LPTIM2_K>;
clock-names = "mux";
status = "disabled";
pwm {
compatible = "st,stm32-pwm-lp";
#pwm-cells = <3>;
status = "disabled";
};
trigger@1 {
compatible = "st,stm32-lptimer-trigger";
reg = <1>;
status = "disabled";
};
counter {
compatible = "st,stm32-lptimer-counter";
status = "disabled";
};
};
lptimer3: timer@50022000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "st,stm32-lptimer";
reg = <0x50022000 0x400>;
clocks = <&rcc LPTIM3_K>;
clock-names = "mux";
status = "disabled";
pwm {
compatible = "st,stm32-pwm-lp";
#pwm-cells = <3>;
status = "disabled";
};
trigger@2 {
compatible = "st,stm32-lptimer-trigger";
reg = <2>;
status = "disabled";
};
};
lptimer4: timer@50023000 {
compatible = "st,stm32-lptimer";
reg = <0x50023000 0x400>;
clocks = <&rcc LPTIM4_K>;
clock-names = "mux";
status = "disabled";
pwm {
compatible = "st,stm32-pwm-lp";
#pwm-cells = <3>;
status = "disabled";
};
};
lptimer5: timer@50024000 {
compatible = "st,stm32-lptimer";
reg = <0x50024000 0x400>;
clocks = <&rcc LPTIM5_K>;
clock-names = "mux";
status = "disabled";
pwm {
compatible = "st,stm32-pwm-lp";
#pwm-cells = <3>;
status = "disabled";
};
};
vrefbuf: vrefbuf@50025000 {
compatible = "st,stm32-vrefbuf";
reg = <0x50025000 0x8>;
regulator-min-microvolt = <1500000>;
regulator-max-microvolt = <2500000>;
clocks = <&rcc VREF>;
status = "disabled";
};
cryp1: cryp@54001000 {
compatible = "st,stm32mp1-cryp";
reg = <0x54001000 0x400>;
interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc CRYP1>;
resets = <&rcc CRYP1_R>;
status = "disabled";
};
rng1: rng@54003000 {
compatible = "st,stm32-rng";
reg = <0x54003000 0x400>;
clocks = <&rcc RNG1_K>;
resets = <&rcc RNG1_R>;
status = "disabled";
};
mdma1: dma@58000000 {
compatible = "st,stm32h7-mdma";
reg = <0x58000000 0x1000>;
interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc MDMA>;
#dma-cells = <5>;
dma-channels = <32>;
dma-requests = <48>;
};
qspi: qspi@58003000 {
compatible = "st,stm32f469-qspi";
reg = <0x58003000 0x1000>, <0x70000000 0x10000000>;
reg-names = "qspi", "qspi_mm";
interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc QSPI_K>;
resets = <&rcc QSPI_R>;
status = "disabled";
};
sdmmc1: sdmmc@58005000 {
compatible = "st,stm32-sdmmc2";
reg = <0x58005000 0x1000>, <0x58006000 0x1000>;
reg-names = "sdmmc", "delay";
clocks = <&rcc SDMMC1_K>;
resets = <&rcc SDMMC1_R>;
st,idma = <1>;
cap-sd-highspeed;
cap-mmc-highspeed;
max-frequency = <120000000>;
status = "disabled";
};
sdmmc2: sdmmc@58007000 {
compatible = "st,stm32-sdmmc2";
reg = <0x58007000 0x1000>, <0x58008000 0x1000>;
reg-names = "sdmmc", "delay";
interrupts = <GIC_SPI 124 IRQ_TYPE_NONE>;
clocks = <&rcc SDMMC2_K>;
resets = <&rcc SDMMC2_R>;
st,idma = <1>;
cap-sd-highspeed;
cap-mmc-highspeed;
max-frequency = <120000000>;
status = "disabled";
};
crc1: crc@58009000 {
compatible = "st,stm32f7-crc";
reg = <0x58009000 0x400>;
clocks = <&rcc CRC1>;
status = "disabled";
};
usbh_ohci: usbh-ohci@5800c000 {
compatible = "generic-ohci";
reg = <0x5800c000 0x1000>;
clocks = <&rcc USBH>;
resets = <&rcc USBH_R>;
interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
usbh_ehci: usbh-ehci@5800d000 {
compatible = "generic-ehci";
reg = <0x5800d000 0x1000>;
clocks = <&rcc USBH>;
resets = <&rcc USBH_R>;
interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
companion = <&usbh_ohci>;
status = "disabled";
};
dsi: dsi@5a000000 {
compatible = "st,stm32-dsi";
reg = <0x5a000000 0x800>;
clocks = <&rcc DSI_K>, <&clk_hse>, <&rcc DSI_PX>;
clock-names = "pclk", "ref", "px_clk";
resets = <&rcc DSI_R>;
reset-names = "apb";
status = "disabled";
};
ltdc: display-controller@5a001000 {
compatible = "st,stm32-ltdc";
reg = <0x5a001000 0x400>;
interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc LTDC_PX>;
clock-names = "lcd";
resets = <&rcc LTDC_R>;
status = "disabled";
};
usbphyc: usbphyc@5a006000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "st,stm32mp1-usbphyc";
reg = <0x5a006000 0x1000>;
clocks = <&rcc USBPHY_K>;
resets = <&rcc USBPHY_R>;
status = "disabled";
usbphyc_port0: usb-phy@0 {
#phy-cells = <0>;
reg = <0>;
};
usbphyc_port1: usb-phy@1 {
#phy-cells = <1>;
reg = <1>;
};
};
usart1: serial@5c000000 {
compatible = "st,stm32h7-uart";
reg = <0x5c000000 0x400>;
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc USART1_K>;
status = "disabled";
};
i2c4: i2c@5c002000 {
compatible = "st,stm32f7-i2c";
reg = <0x5c002000 0x400>;
interrupt-names = "event", "error";
interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc I2C4_K>;
resets = <&rcc I2C4_R>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c6: i2c@5c009000 {
compatible = "st,stm32f7-i2c";
reg = <0x5c009000 0x400>;
interrupt-names = "event", "error";
interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc I2C6_K>;
resets = <&rcc I2C6_R>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
};
};

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include/dt-bindings/clock/stm32mp1-clks.h
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/* SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause */ /* SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause */
/* /*
* Copyright (C) STMicroelectronics 2017 - All Rights Reserved * Copyright (C) STMicroelectronics 2018 - All Rights Reserved
* Author: Gabriel Fernandez <gabriel.fernandez@st.com> for STMicroelectronics. * Author: Gabriel Fernandez <gabriel.fernandez@st.com> for STMicroelectronics.
*/ */
#ifndef _DT_BINDINGS_STM32MP1_CLKS_H_
#define _DT_BINDINGS_STM32MP1_CLKS_H_
/* OSCILLATOR clocks */ /* OSCILLATOR clocks */
#define CK_HSE 0 #define CK_HSE 0
#define CK_CSI 1 #define CK_CSI 1
#define CK_LSI 2 #define CK_LSI 2
#define CK_LSE 3 #define CK_LSE 3
#define CK_HSI 4 #define CK_HSI 4
#define CK_HSE_DIV2 5 #define CK_HSE_DIV2 5
/* Bus clocks */ /* Bus clocks */
#define TIM2 6 #define TIM2 6
#define TIM3 7 #define TIM3 7
#define TIM4 8 #define TIM4 8
#define TIM5 9 #define TIM5 9
#define TIM6 10 #define TIM6 10
#define TIM7 11 #define TIM7 11
#define TIM12 12 #define TIM12 12
#define TIM13 13 #define TIM13 13
#define TIM14 14 #define TIM14 14
#define LPTIM1 15 #define LPTIM1 15
#define SPI2 16 #define SPI2 16
#define SPI3 17 #define SPI3 17
#define USART2 18 #define USART2 18
#define USART3 19 #define USART3 19
#define UART4 20 #define UART4 20
#define UART5 21 #define UART5 21
#define UART7 22 #define UART7 22
#define UART8 23 #define UART8 23
#define I2C1 24 #define I2C1 24
#define I2C2 25 #define I2C2 25
#define I2C3 26 #define I2C3 26
#define I2C5 27 #define I2C5 27
#define SPDIF 28 #define SPDIF 28
#define CEC 29 #define CEC 29
#define DAC12 30 #define DAC12 30
#define MDIO 31 #define MDIO 31
#define TIM1 32 #define TIM1 32
#define TIM8 33 #define TIM8 33
#define TIM15 34 #define TIM15 34
#define TIM16 35 #define TIM16 35
#define TIM17 36 #define TIM17 36
#define SPI1 37 #define SPI1 37
#define SPI4 38 #define SPI4 38
#define SPI5 39 #define SPI5 39
#define USART6 40 #define USART6 40
#define SAI1 41 #define SAI1 41
#define SAI2 42 #define SAI2 42
#define SAI3 43 #define SAI3 43
#define DFSDM 44 #define DFSDM 44
#define FDCAN 45 #define FDCAN 45
#define LPTIM2 46 #define LPTIM2 46
#define LPTIM3 47 #define LPTIM3 47
#define LPTIM4 48 #define LPTIM4 48
#define LPTIM5 49 #define LPTIM5 49
#define SAI4 50 #define SAI4 50
#define SYSCFG 51 #define SYSCFG 51
#define VREF 52 #define VREF 52
#define TMPSENS 53 #define TMPSENS 53
#define PMBCTRL 54 #define PMBCTRL 54
#define HDP 55 #define HDP 55
#define LTDC 56 #define LTDC 56
#define DSI 57 #define DSI 57
#define IWDG2 58 #define IWDG2 58
#define USBPHY 59 #define USBPHY 59
#define STGENRO 60 #define STGENRO 60
#define SPI6 61 #define SPI6 61
#define I2C4 62 #define I2C4 62
#define I2C6 63 #define I2C6 63
#define USART1 64 #define USART1 64
#define RTCAPB 65 #define RTCAPB 65
#define TZC 66 #define TZC1 66
#define TZPC 67 #define TZPC 67
#define IWDG1 68 #define IWDG1 68
#define BSEC 69 #define BSEC 69
#define STGEN 70 #define STGEN 70
#define DMA1 71 #define DMA1 71
#define DMA2 72 #define DMA2 72
#define DMAMUX 73 #define DMAMUX 73
#define ADC12 74 #define ADC12 74
#define USBO 75 #define USBO 75
#define SDMMC3 76 #define SDMMC3 76
#define DCMI 77 #define DCMI 77
#define CRYP2 78 #define CRYP2 78
#define HASH2 79 #define HASH2 79
#define RNG2 80 #define RNG2 80
#define CRC2 81 #define CRC2 81
#define HSEM 82 #define HSEM 82
#define IPCC 83 #define IPCC 83
#define GPIOA 84 #define GPIOA 84
#define GPIOB 85 #define GPIOB 85
#define GPIOC 86 #define GPIOC 86
#define GPIOD 87 #define GPIOD 87
#define GPIOE 88 #define GPIOE 88
#define GPIOF 89 #define GPIOF 89
#define GPIOG 90 #define GPIOG 90
#define GPIOH 91 #define GPIOH 91
#define GPIOI 92 #define GPIOI 92
#define GPIOJ 93 #define GPIOJ 93
#define GPIOK 94 #define GPIOK 94
#define GPIOZ 95 #define GPIOZ 95
#define CRYP1 96 #define CRYP1 96
#define HASH1 97 #define HASH1 97
#define RNG1 98 #define RNG1 98
#define BKPSRAM 99 #define BKPSRAM 99
#define MDMA 100 #define MDMA 100
#define DMA2D 101 #define GPU 101
#define GPU 102 #define ETHCK 102
#define ETHCK 103 #define ETHTX 103
#define ETHTX 104 #define ETHRX 104
#define ETHRX 105 #define ETHMAC 105
#define ETHMAC 106 #define FMC 106
#define FMC 107 #define QSPI 107
#define QSPI 108 #define SDMMC1 108
#define SDMMC1 109 #define SDMMC2 109
#define SDMMC2 110 #define CRC1 110
#define CRC1 111 #define USBH 111
#define USBH 112 #define ETHSTP 112
#define ETHSTP 113 #define TZC2 113
/* Kernel clocks */ /* Kernel clocks */
#define SDMMC1_K 114 #define SDMMC1_K 118
#define SDMMC2_K 115 #define SDMMC2_K 119
#define SDMMC3_K 116 #define SDMMC3_K 120
#define FMC_K 117 #define FMC_K 121
#define QSPI_K 118 #define QSPI_K 122
#define ETHMAC_K 119 #define ETHCK_K 123
#define RNG1_K 120 #define RNG1_K 124
#define RNG2_K 121 #define RNG2_K 125
#define GPU_K 122 #define GPU_K 126
#define USBPHY_K 123 #define USBPHY_K 127
#define STGEN_K 124 #define STGEN_K 128
#define SPDIF_K 125 #define SPDIF_K 129
#define SPI1_K 126 #define SPI1_K 130
#define SPI2_K 127 #define SPI2_K 131
#define SPI3_K 128 #define SPI3_K 132
#define SPI4_K 129 #define SPI4_K 133
#define SPI5_K 130 #define SPI5_K 134
#define SPI6_K 131 #define SPI6_K 135
#define CEC_K 132 #define CEC_K 136
#define I2C1_K 133 #define I2C1_K 137
#define I2C2_K 134 #define I2C2_K 138
#define I2C3_K 135 #define I2C3_K 139
#define I2C4_K 136 #define I2C4_K 140
#define I2C5_K 137 #define I2C5_K 141
#define I2C6_K 138 #define I2C6_K 142
#define LPTIM1_K 139 #define LPTIM1_K 143
#define LPTIM2_K 140 #define LPTIM2_K 144
#define LPTIM3_K 141 #define LPTIM3_K 145
#define LPTIM4_K 142 #define LPTIM4_K 146
#define LPTIM5_K 143 #define LPTIM5_K 147
#define USART1_K 144 #define USART1_K 148
#define USART2_K 145 #define USART2_K 149
#define USART3_K 146 #define USART3_K 150
#define UART4_K 147 #define UART4_K 151
#define UART5_K 148 #define UART5_K 152
#define USART6_K 149 #define USART6_K 153
#define UART7_K 150 #define UART7_K 154
#define UART8_K 151 #define UART8_K 155
#define DFSDM_K 152 #define DFSDM_K 156
#define FDCAN_K 153 #define FDCAN_K 157
#define SAI1_K 154 #define SAI1_K 158
#define SAI2_K 155 #define SAI2_K 159
#define SAI3_K 156 #define SAI3_K 160
#define SAI4_K 157 #define SAI4_K 161
#define ADC12_K 158 #define ADC12_K 162
#define DSI_K 159 #define DSI_K 163
#define ADFSDM_K 160 #define DSI_PX 164
#define USBO_K 161 #define ADFSDM_K 165
#define LTDC_K 162 #define USBO_K 166
#define LTDC_PX 167
#define DAC12_K 168
#define ETHPTP_K 169
/* PLL */ /* PLL */
#define PLL1 163 #define PLL1 176
#define PLL2 164 #define PLL2 177
#define PLL3 165 #define PLL3 178
#define PLL4 166 #define PLL4 179
/* ODF */ /* ODF */
#define PLL1_P 167 #define PLL1_P 180
#define PLL1_Q 168 #define PLL1_Q 181
#define PLL1_R 169 #define PLL1_R 182
#define PLL2_P 170 #define PLL2_P 183
#define PLL2_Q 171 #define PLL2_Q 184
#define PLL2_R 172 #define PLL2_R 185
#define PLL3_P 173 #define PLL3_P 186
#define PLL3_Q 174 #define PLL3_Q 187
#define PLL3_R 175 #define PLL3_R 188
#define PLL4_P 176 #define PLL4_P 189
#define PLL4_Q 177 #define PLL4_Q 190
#define PLL4_R 178 #define PLL4_R 191
/* AUX */ /* AUX */
#define RTC 179 #define RTC 192
/* MCLK */ /* MCLK */
#define CK_PER 180 #define CK_PER 193
#define CK_MPU 181 #define CK_MPU 194
#define CK_AXI 182 #define CK_AXI 195
#define CK_MCU 183 #define CK_MCU 196
/* Time base */ /* Time base */
#define TIM2_K 184 #define TIM2_K 197
#define TIM3_K 185 #define TIM3_K 198
#define TIM4_K 186 #define TIM4_K 199
#define TIM5_K 187 #define TIM5_K 200
#define TIM6_K 188 #define TIM6_K 201
#define TIM7_K 189 #define TIM7_K 202
#define TIM12_K 190 #define TIM12_K 203
#define TIM13_K 191 #define TIM13_K 204
#define TIM14_K 192 #define TIM14_K 205
#define TIM1_K 193 #define TIM1_K 206
#define TIM8_K 194 #define TIM8_K 207
#define TIM15_K 195 #define TIM15_K 208
#define TIM16_K 196 #define TIM16_K 209
#define TIM17_K 197 #define TIM17_K 210
/* MCO clocks */ /* MCO clocks */
#define CK_MCO1 198 #define CK_MCO1 211
#define CK_MCO2 199 #define CK_MCO2 212
/* TRACE & DEBUG clocks */ /* TRACE & DEBUG clocks */
#define DBG 200 #define CK_DBG 214
#define CK_DBG 201 #define CK_TRACE 215
#define CK_TRACE 202
/* DDR */ /* DDR */
#define DDRC1 203 #define DDRC1 220
#define DDRC1LP 204 #define DDRC1LP 221
#define DDRC2 205 #define DDRC2 222
#define DDRC2LP 206 #define DDRC2LP 223
#define DDRPHYC 207 #define DDRPHYC 224
#define DDRPHYCLP 208 #define DDRPHYCLP 225
#define DDRCAPB 209 #define DDRCAPB 226
#define DDRCAPBLP 210 #define DDRCAPBLP 227
#define AXIDCG 211 #define AXIDCG 228
#define DDRPHYCAPB 212 #define DDRPHYCAPB 229
#define DDRPHYCAPBLP 213 #define DDRPHYCAPBLP 230
#define DDRPERFM 214 #define DDRPERFM 231
#define STM32MP1_LAST_CLK 232
#define LTDC_K LTDC_PX
#define ETHMAC_K ETHCK_K
#define STM32MP1_LAST_CLK 215 #endif /* _DT_BINDINGS_STM32MP1_CLKS_H_ */

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include/dt-bindings/pinctrl/stm32-pinfunc.h
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/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
/*
* Copyright (C) STMicroelectronics 2017 - All Rights Reserved
* Author: Torgue Alexandre <alexandre.torgue@st.com> for STMicroelectronics.
*/
#ifndef _DT_BINDINGS_STM32_PINFUNC_H #ifndef _DT_BINDINGS_STM32_PINFUNC_H
#define _DT_BINDINGS_STM32_PINFUNC_H #define _DT_BINDINGS_STM32_PINFUNC_H

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include/dt-bindings/reset-controller/stm32mp1-resets.h
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#define LTDC_R 3072
#define DSI_R 3076
#define DDRPERFM_R 3080
#define USBPHY_R 3088
#define SPI6_R 3136
#define I2C4_R 3138
#define I2C6_R 3139
#define USART1_R 3140
#define STGEN_R 3156
#define GPIOZ_R 3200
#define CRYP1_R 3204
#define HASH1_R 3205
#define RNG1_R 3206
#define AXIM_R 3216
#define GPU_R 3269
#define ETHMAC_R 3274
#define FMC_R 3276
#define QSPI_R 3278
#define SDMMC1_R 3280
#define SDMMC2_R 3281
#define CRC1_R 3284
#define USBH_R 3288
#define MDMA_R 3328
#define MCU_R 8225
#define TIM2_R 19456
#define TIM3_R 19457
#define TIM4_R 19458
#define TIM5_R 19459
#define TIM6_R 19460
#define TIM7_R 19461
#define TIM12_R 16462
#define TIM13_R 16463
#define TIM14_R 16464
#define LPTIM1_R 19465
#define SPI2_R 19467
#define SPI3_R 19468
#define USART2_R 19470
#define USART3_R 19471
#define UART4_R 19472
#define UART5_R 19473
#define UART7_R 19474
#define UART8_R 19475
#define I2C1_R 19477
#define I2C2_R 19478
#define I2C3_R 19479
#define I2C5_R 19480
#define SPDIF_R 19482
#define CEC_R 19483
#define DAC12_R 19485
#define MDIO_R 19847
#define TIM1_R 19520
#define TIM8_R 19521
#define TIM15_R 19522
#define TIM16_R 19523
#define TIM17_R 19524
#define SPI1_R 19528
#define SPI4_R 19529
#define SPI5_R 19530
#define USART6_R 19533
#define SAI1_R 19536
#define SAI2_R 19537
#define SAI3_R 19538
#define DFSDM_R 19540
#define FDCAN_R 19544
#define LPTIM2_R 19584
#define LPTIM3_R 19585
#define LPTIM4_R 19586
#define LPTIM5_R 19587
#define SAI4_R 19592
#define SYSCFG_R 19595
#define VREF_R 19597
#define TMPSENS_R 19600
#define PMBCTRL_R 19601
#define DMA1_R 19648
#define DMA2_R 19649
#define DMAMUX_R 19650
#define ADC12_R 19653
#define USBO_R 19656
#define SDMMC3_R 19664
#define CAMITF_R 19712
#define CRYP2_R 19716
#define HASH2_R 19717
#define RNG2_R 19718
#define CRC2_R 19719
#define HSEM_R 19723
#define MBOX_R 19724
#define GPIOA_R 19776
#define GPIOB_R 19777
#define GPIOC_R 19778
#define GPIOD_R 19779
#define GPIOE_R 19780
#define GPIOF_R 19781
#define GPIOG_R 19782
#define GPIOH_R 19783
#define GPIOI_R 19784
#define GPIOJ_R 19785
#define GPIOK_R 19786

108
include/dt-bindings/reset/stm32mp1-resets.h
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/* SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause */
/*
* Copyright (C) STMicroelectronics 2018 - All Rights Reserved
* Author: Gabriel Fernandez <gabriel.fernandez@st.com> for STMicroelectronics.
*/
#ifndef _DT_BINDINGS_STM32MP1_RESET_H_
#define _DT_BINDINGS_STM32MP1_RESET_H_
#define LTDC_R 3072
#define DSI_R 3076
#define DDRPERFM_R 3080
#define USBPHY_R 3088
#define SPI6_R 3136
#define I2C4_R 3138
#define I2C6_R 3139
#define USART1_R 3140
#define STGEN_R 3156
#define GPIOZ_R 3200
#define CRYP1_R 3204
#define HASH1_R 3205
#define RNG1_R 3206
#define AXIM_R 3216
#define GPU_R 3269
#define ETHMAC_R 3274
#define FMC_R 3276
#define QSPI_R 3278
#define SDMMC1_R 3280
#define SDMMC2_R 3281
#define CRC1_R 3284
#define USBH_R 3288
#define MDMA_R 3328
#define MCU_R 8225
#define TIM2_R 19456
#define TIM3_R 19457
#define TIM4_R 19458
#define TIM5_R 19459
#define TIM6_R 19460
#define TIM7_R 19461
#define TIM12_R 16462
#define TIM13_R 16463
#define TIM14_R 16464
#define LPTIM1_R 19465
#define SPI2_R 19467
#define SPI3_R 19468
#define USART2_R 19470
#define USART3_R 19471
#define UART4_R 19472
#define UART5_R 19473
#define UART7_R 19474
#define UART8_R 19475
#define I2C1_R 19477
#define I2C2_R 19478
#define I2C3_R 19479
#define I2C5_R 19480
#define SPDIF_R 19482
#define CEC_R 19483
#define DAC12_R 19485
#define MDIO_R 19847
#define TIM1_R 19520
#define TIM8_R 19521
#define TIM15_R 19522
#define TIM16_R 19523
#define TIM17_R 19524
#define SPI1_R 19528
#define SPI4_R 19529
#define SPI5_R 19530
#define USART6_R 19533
#define SAI1_R 19536
#define SAI2_R 19537
#define SAI3_R 19538
#define DFSDM_R 19540
#define FDCAN_R 19544
#define LPTIM2_R 19584
#define LPTIM3_R 19585
#define LPTIM4_R 19586
#define LPTIM5_R 19587
#define SAI4_R 19592
#define SYSCFG_R 19595
#define VREF_R 19597
#define TMPSENS_R 19600
#define PMBCTRL_R 19601
#define DMA1_R 19648
#define DMA2_R 19649
#define DMAMUX_R 19650
#define ADC12_R 19653
#define USBO_R 19656
#define SDMMC3_R 19664
#define CAMITF_R 19712
#define CRYP2_R 19716
#define HASH2_R 19717
#define RNG2_R 19718
#define CRC2_R 19719
#define HSEM_R 19723
#define MBOX_R 19724
#define GPIOA_R 19776
#define GPIOB_R 19777
#define GPIOC_R 19778
#define GPIOD_R 19779
#define GPIOE_R 19780
#define GPIOF_R 19781
#define GPIOG_R 19782
#define GPIOH_R 19783
#define GPIOI_R 19784
#define GPIOJ_R 19785
#define GPIOK_R 19786
#endif /* _DT_BINDINGS_STM32MP1_RESET_H_ */
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