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ppc4xx: Consolidate pci_pre_init() function

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This patch removes the duplicted implementations of the pci_pre_init()
function by introducing a weak default function for it. This weak default
has a different implementation for some PPC variants. It can be
overridden by a board specific version.

Signed-off-by: Stefan Roese <sr@denx.de>
master
Stefan Roese 16 years ago
parent 1095493a5d
commit a760b02031
28 changed files with 130 additions and 837 deletions
Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL
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  1. 55
      board/amcc/bamboo/bamboo.c
  2. 31
      board/amcc/ebony/ebony.c
  3. 31
      board/amcc/katmai/katmai.c
  4. 19
      board/amcc/kilauea/kilauea.c
  5. 33
      board/amcc/luan/luan.c
  6. 19
      board/amcc/makalu/makalu.c
  7. 32
      board/amcc/ocotea/ocotea.c
  8. 59
      board/amcc/sequoia/sequoia.c
  9. 31
      board/amcc/taishan/taishan.c
  10. 55
      board/amcc/yosemite/yosemite.c
  11. 31
      board/amcc/yucca/yucca.c
  12. 54
      board/esd/du440/du440.c
  13. 60
      board/esd/pmc440/pmc440.c
  14. 49
      board/gdsys/gdppc440etx/gdppc440etx.c
  15. 60
      board/korat/korat.c
  16. 55
      board/lwmon5/lwmon5.c
  17. 55
      board/pcs440ep/pcs440ep.c
  18. 30
      board/prodrive/alpr/alpr.c
  19. 31
      board/prodrive/p3p440/p3p440.c
  20. 32
      board/sandburst/common/sb_common.c
  21. 3
      board/xes/xpedite1000/xpedite1000.c
  22. 111
      cpu/ppc4xx/4xx_pci.c
  23. 2
      cpu/ppc4xx/cpu.c
  24. 5
      include/asm-ppc/4xx_pci.h
  25. 1
      include/configs/PMC440.h
  26. 1
      include/configs/korat.h
  27. 1
      include/configs/sequoia.h
  28. 3
      include/ppc440.h

55
board/amcc/bamboo/bamboo.c
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@ -467,61 +467,6 @@ phys_size_t initdram (int board_type)
}
/*************************************************************************
* pci_pre_init
*
* This routine is called just prior to registering the hose and gives
* the board the opportunity to check things. Returning a value of zero
* indicates that things are bad & PCI initialization should be aborted.
*
* Different boards may wish to customize the pci controller structure
* (add regions, override default access routines, etc) or perform
* certain pre-initialization actions.
*
************************************************************************/
#if defined(CONFIG_PCI)
int pci_pre_init(struct pci_controller *hose)
{
unsigned long addr;
/*-------------------------------------------------------------------------+
| Set priority for all PLB3 devices to 0.
| Set PLB3 arbiter to fair mode.
+-------------------------------------------------------------------------*/
mfsdr(SD0_AMP1, addr);
mtsdr(SD0_AMP1, (addr & 0x000000FF) | 0x0000FF00);
addr = mfdcr(PLB3_ACR);
mtdcr(PLB3_ACR, addr | 0x80000000);
/*-------------------------------------------------------------------------+
| Set priority for all PLB4 devices to 0.
+-------------------------------------------------------------------------*/
mfsdr(SD0_AMP0, addr);
mtsdr(SD0_AMP0, (addr & 0x000000FF) | 0x0000FF00);
addr = mfdcr(PLB4_ACR) | 0xa0000000; /* Was 0x8---- */
mtdcr(PLB4_ACR, addr);
/*-------------------------------------------------------------------------+
| Set Nebula PLB4 arbiter to fair mode.
+-------------------------------------------------------------------------*/
/* Segment0 */
addr = (mfdcr(PLB0_ACR) & ~PLB0_ACR_PPM_MASK) | PLB0_ACR_PPM_FAIR;
addr = (addr & ~PLB0_ACR_HBU_MASK) | PLB0_ACR_HBU_ENABLED;
addr = (addr & ~PLB0_ACR_RDP_MASK) | PLB0_ACR_RDP_4DEEP;
addr = (addr & ~PLB0_ACR_WRP_MASK) | PLB0_ACR_WRP_2DEEP;
mtdcr(PLB0_ACR, addr);
/* Segment1 */
addr = (mfdcr(PLB1_ACR) & ~PLB1_ACR_PPM_MASK) | PLB1_ACR_PPM_FAIR;
addr = (addr & ~PLB1_ACR_HBU_MASK) | PLB1_ACR_HBU_ENABLED;
addr = (addr & ~PLB1_ACR_RDP_MASK) | PLB1_ACR_RDP_4DEEP;
addr = (addr & ~PLB1_ACR_WRP_MASK) | PLB1_ACR_WRP_2DEEP;
mtdcr(PLB1_ACR, addr);
return 1;
}
#endif /* defined(CONFIG_PCI) */
/*************************************************************************
* pci_master_init
*
************************************************************************/

31
board/amcc/ebony/ebony.c
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@ -164,34 +164,3 @@ long int fixed_sdram(void)
return (128 * 1024 * 1024); /* 128 MB */
}
#endif /* !defined(CONFIG_SPD_EEPROM) */
/*************************************************************************
* pci_pre_init
*
* This routine is called just prior to registering the hose and gives
* the board the opportunity to check things. Returning a value of zero
* indicates that things are bad & PCI initialization should be aborted.
*
* Different boards may wish to customize the pci controller structure
* (add regions, override default access routines, etc) or perform
* certain pre-initialization actions.
*
************************************************************************/
#if defined(CONFIG_PCI)
int pci_pre_init(struct pci_controller *hose)
{
unsigned long strap;
/*--------------------------------------------------------------------------+
* The ebony board is always configured as the host & requires the
* PCI arbiter to be enabled.
*--------------------------------------------------------------------------*/
strap = mfdcr(CPC0_STRP1);
if ((strap & 0x00100000) == 0) {
printf("PCI: CPC0_STRP1[PAE] not set.\n");
return 0;
}
return 1;
}
#endif /* defined(CONFIG_PCI) */

31
board/amcc/katmai/katmai.c
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@ -260,37 +260,6 @@ u32 ddr_clktr(u32 default_val) {
return (SDRAM_CLKTR_CLKP_90_DEG_ADV);
}
/*************************************************************************
* pci_pre_init
*
* This routine is called just prior to registering the hose and gives
* the board the opportunity to check things. Returning a value of zero
* indicates that things are bad & PCI initialization should be aborted.
*
* Different boards may wish to customize the pci controller structure
* (add regions, override default access routines, etc) or perform
* certain pre-initialization actions.
*
************************************************************************/
#if defined(CONFIG_PCI)
int pci_pre_init(struct pci_controller * hose )
{
unsigned long strap;
/*-------------------------------------------------------------------+
* The katmai board is always configured as the host & requires the
* PCI arbiter to be enabled.
*-------------------------------------------------------------------*/
mfsdr(SDR0_SDSTP1, strap);
if( (strap & SDR0_SDSTP1_PAE_MASK) == 0 ) {
printf("PCI: SDR0_STRP1[%08lX] - PCI Arbiter disabled.\n",strap);
return 0;
}
return 1;
}
#endif /* defined(CONFIG_PCI) */
#if defined(CONFIG_PCI)
int board_pcie_card_present(int port)
{

19
board/amcc/kilauea/kilauea.c
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@ -285,25 +285,6 @@ int checkboard (void)
return (0);
}
/*************************************************************************
* pci_pre_init
*
* This routine is called just prior to registering the hose and gives
* the board the opportunity to check things. Returning a value of zero
* indicates that things are bad & PCI initialization should be aborted.
*
* Different boards may wish to customize the pci controller structure
* (add regions, override default access routines, etc) or perform
* certain pre-initialization actions.
*
************************************************************************/
#if defined(CONFIG_PCI)
int pci_pre_init(struct pci_controller * hose )
{
return 0;
}
#endif /* defined(CONFIG_PCI) */
#if defined(CONFIG_POST)
/*
* Returns 1 if keys pressed to start the power-on long-running tests

33
board/amcc/luan/luan.c
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@ -127,39 +127,6 @@ u32 ddr_clktr(u32 default_val) {
}
/*************************************************************************
* pci_pre_init
*
* This routine is called just prior to registering the hose and gives
* the board the opportunity to check things. Returning a value of zero
* indicates that things are bad & PCI initialization should be aborted.
*
* Different boards may wish to customize the pci controller structure
* (add regions, override default access routines, etc) or perform
* certain pre-initialization actions.
*
************************************************************************/
#if defined(CONFIG_PCI)
int pci_pre_init( struct pci_controller *hose )
{
unsigned long strap;
/*--------------------------------------------------------------------------+
* The luan board is always configured as the host & requires the
* PCI arbiter to be enabled.
*--------------------------------------------------------------------------*/
mfsdr(SDR0_SDSTP1, strap);
if( (strap & SDR0_SDSTP1_PAE_MASK) == 0 ) {
printf("PCI: SDR0_STRP1[%08lX] - PCI Arbiter disabled.\n",strap);
return 0;
}
return 1;
}
#endif /* defined(CONFIG_PCI) */
/*************************************************************************
* hw_watchdog_reset
*
* This routine is called to reset (keep alive) the watchdog timer

19
board/amcc/makalu/makalu.c
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@ -237,25 +237,6 @@ int checkboard (void)
return (0);
}
/*************************************************************************
* pci_pre_init
*
* This routine is called just prior to registering the hose and gives
* the board the opportunity to check things. Returning a value of zero
* indicates that things are bad & PCI initialization should be aborted.
*
* Different boards may wish to customize the pci controller structure
* (add regions, override default access routines, etc) or perform
* certain pre-initialization actions.
*
************************************************************************/
#if defined(CONFIG_PCI)
int pci_pre_init(struct pci_controller * hose )
{
return 0;
}
#endif /* defined(CONFIG_PCI) */
#if defined(CONFIG_POST)
/*
* Returns 1 if keys pressed to start the power-on long-running tests

32
board/amcc/ocotea/ocotea.c
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@ -275,38 +275,6 @@ long int fixed_sdram (void)
}
#endif /* !defined(CONFIG_SPD_EEPROM) */
/*************************************************************************
* pci_pre_init
*
* This routine is called just prior to registering the hose and gives
* the board the opportunity to check things. Returning a value of zero
* indicates that things are bad & PCI initialization should be aborted.
*
* Different boards may wish to customize the pci controller structure
* (add regions, override default access routines, etc) or perform
* certain pre-initialization actions.
*
************************************************************************/
#if defined(CONFIG_PCI)
int pci_pre_init(struct pci_controller * hose )
{
unsigned long strap;
/*--------------------------------------------------------------------------+
* The ocotea board is always configured as the host & requires the
* PCI arbiter to be enabled.
*--------------------------------------------------------------------------*/
mfsdr(SDR0_SDSTP1, strap);
if( (strap & SDR0_SDSTP1_PAE_MASK) == 0 ){
printf("PCI: SDR0_STRP1[%08lX] - PCI Arbiter disabled.\n",strap);
return 0;
}
return 1;
}
#endif /* defined(CONFIG_PCI) */
void fpga_init(void)
{
unsigned long group;

59
board/amcc/sequoia/sequoia.c
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@ -364,69 +364,12 @@ int checkboard(void)
/*
* Assign interrupts to PCI devices.
*/
void sequoia_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
void board_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
{
pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, VECNUM_EIRQ2);
}
#endif
/*
* pci_pre_init
*
* This routine is called just prior to registering the hose and gives
* the board the opportunity to check things. Returning a value of zero
* indicates that things are bad & PCI initialization should be aborted.
*
* Different boards may wish to customize the pci controller structure
* (add regions, override default access routines, etc) or perform
* certain pre-initialization actions.
*/
#if defined(CONFIG_PCI)
int pci_pre_init(struct pci_controller *hose)
{
unsigned long addr;
/*
* Set priority for all PLB3 devices to 0.
* Set PLB3 arbiter to fair mode.
*/
mfsdr(SD0_AMP1, addr);
mtsdr(SD0_AMP1, (addr & 0x000000FF) | 0x0000FF00);
addr = mfdcr(PLB3_ACR);
mtdcr(PLB3_ACR, addr | 0x80000000);
/*
* Set priority for all PLB4 devices to 0.
*/
mfsdr(SD0_AMP0, addr);
mtsdr(SD0_AMP0, (addr & 0x000000FF) | 0x0000FF00);
addr = mfdcr(PLB4_ACR) | 0xa0000000; /* Was 0x8---- */
mtdcr(PLB4_ACR, addr);
/*
* Set Nebula PLB4 arbiter to fair mode.
*/
/* Segment0 */
addr = (mfdcr(PLB0_ACR) & ~PLB0_ACR_PPM_MASK) | PLB0_ACR_PPM_FAIR;
addr = (addr & ~PLB0_ACR_HBU_MASK) | PLB0_ACR_HBU_ENABLED;
addr = (addr & ~PLB0_ACR_RDP_MASK) | PLB0_ACR_RDP_4DEEP;
addr = (addr & ~PLB0_ACR_WRP_MASK) | PLB0_ACR_WRP_2DEEP;
mtdcr(PLB0_ACR, addr);
/* Segment1 */
addr = (mfdcr(PLB1_ACR) & ~PLB1_ACR_PPM_MASK) | PLB1_ACR_PPM_FAIR;
addr = (addr & ~PLB1_ACR_HBU_MASK) | PLB1_ACR_HBU_ENABLED;
addr = (addr & ~PLB1_ACR_RDP_MASK) | PLB1_ACR_RDP_4DEEP;
addr = (addr & ~PLB1_ACR_WRP_MASK) | PLB1_ACR_WRP_2DEEP;
mtdcr(PLB1_ACR, addr);
#ifdef CONFIG_PCI_PNP
hose->fixup_irq = sequoia_pci_fixup_irq;
#endif
return 1;
}
#endif /* defined(CONFIG_PCI) */
#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT)
void pci_master_init(struct pci_controller *hose)
{

31
board/amcc/taishan/taishan.c
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@ -209,37 +209,6 @@ int checkboard (void)
return (0);
}
/*************************************************************************
* pci_pre_init
*
* This routine is called just prior to registering the hose and gives
* the board the opportunity to check things. Returning a value of zero
* indicates that things are bad & PCI initialization should be aborted.
*
* Different boards may wish to customize the pci controller structure
* (add regions, override default access routines, etc) or perform
* certain pre-initialization actions.
*
************************************************************************/
#if defined(CONFIG_PCI)
int pci_pre_init(struct pci_controller * hose )
{
unsigned long strap;
/*--------------------------------------------------------------------------+
* The ocotea board is always configured as the host & requires the
* PCI arbiter to be enabled.
*--------------------------------------------------------------------------*/
mfsdr(SDR0_SDSTP1, strap);
if( (strap & SDR0_SDSTP1_PAE_MASK) == 0 ){
printf("PCI: SDR0_STRP1[%08lX] - PCI Arbiter disabled.\n",strap);
return 0;
}
return 1;
}
#endif /* defined(CONFIG_PCI) */
#ifdef CONFIG_POST
/*
* Returns 1 if keys pressed to start the power-on long-running tests

55
board/amcc/yosemite/yosemite.c
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@ -353,61 +353,6 @@ phys_size_t initdram(int board)
}
/*************************************************************************
* pci_pre_init
*
* This routine is called just prior to registering the hose and gives
* the board the opportunity to check things. Returning a value of zero
* indicates that things are bad & PCI initialization should be aborted.
*
* Different boards may wish to customize the pci controller structure
* (add regions, override default access routines, etc) or perform
* certain pre-initialization actions.
*
************************************************************************/
#if defined(CONFIG_PCI)
int pci_pre_init(struct pci_controller *hose)
{
unsigned long addr;
/*-------------------------------------------------------------------------+
| Set priority for all PLB3 devices to 0.
| Set PLB3 arbiter to fair mode.
+-------------------------------------------------------------------------*/
mfsdr(SD0_AMP1, addr);
mtsdr(SD0_AMP1, (addr & 0x000000FF) | 0x0000FF00);
addr = mfdcr(PLB3_ACR);
mtdcr(PLB3_ACR, addr | 0x80000000);
/*-------------------------------------------------------------------------+
| Set priority for all PLB4 devices to 0.
+-------------------------------------------------------------------------*/
mfsdr(SD0_AMP0, addr);
mtsdr(SD0_AMP0, (addr & 0x000000FF) | 0x0000FF00);
addr = mfdcr(PLB4_ACR) | 0xa0000000; /* Was 0x8---- */
mtdcr(PLB4_ACR, addr);
/*-------------------------------------------------------------------------+
| Set Nebula PLB4 arbiter to fair mode.
+-------------------------------------------------------------------------*/
/* Segment0 */
addr = (mfdcr(PLB0_ACR) & ~PLB0_ACR_PPM_MASK) | PLB0_ACR_PPM_FAIR;
addr = (addr & ~PLB0_ACR_HBU_MASK) | PLB0_ACR_HBU_ENABLED;
addr = (addr & ~PLB0_ACR_RDP_MASK) | PLB0_ACR_RDP_4DEEP;
addr = (addr & ~PLB0_ACR_WRP_MASK) | PLB0_ACR_WRP_2DEEP;
mtdcr(PLB0_ACR, addr);
/* Segment1 */
addr = (mfdcr(PLB1_ACR) & ~PLB1_ACR_PPM_MASK) | PLB1_ACR_PPM_FAIR;
addr = (addr & ~PLB1_ACR_HBU_MASK) | PLB1_ACR_HBU_ENABLED;
addr = (addr & ~PLB1_ACR_RDP_MASK) | PLB1_ACR_RDP_4DEEP;
addr = (addr & ~PLB1_ACR_WRP_MASK) | PLB1_ACR_WRP_2DEEP;
mtdcr(PLB1_ACR, addr);
return 1;
}
#endif /* defined(CONFIG_PCI) */
/*************************************************************************
* pci_master_init
*
************************************************************************/

31
board/amcc/yucca/yucca.c
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@ -588,37 +588,6 @@ u32 ddr_clktr(u32 default_val) {
return default_val;
}
/*************************************************************************
* pci_pre_init
*
* This routine is called just prior to registering the hose and gives
* the board the opportunity to check things. Returning a value of zero
* indicates that things are bad & PCI initialization should be aborted.
*
* Different boards may wish to customize the pci controller structure
* (add regions, override default access routines, etc) or perform
* certain pre-initialization actions.
*
************************************************************************/
#if defined(CONFIG_PCI)
int pci_pre_init(struct pci_controller * hose )
{
unsigned long strap;
/*-------------------------------------------------------------------+
* The yucca board is always configured as the host & requires the
* PCI arbiter to be enabled.
*-------------------------------------------------------------------*/
mfsdr(SDR0_SDSTP1, strap);
if( (strap & SDR0_SDSTP1_PAE_MASK) == 0 ) {
printf("PCI: SDR0_STRP1[%08lX] - PCI Arbiter disabled.\n",strap);
return 0;
}
return 1;
}
#endif /* defined(CONFIG_PCI) */
#if defined(CONFIG_PCI)
int board_pcie_card_present(int port)
{

54
board/esd/du440/du440.c
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@ -360,60 +360,6 @@ int checkboard(void)
return (0);
}
/*
* pci_pre_init
*
* This routine is called just prior to registering the hose and gives
* the board the opportunity to check things. Returning a value of zero
* indicates that things are bad & PCI initialization should be aborted.
*
* Different boards may wish to customize the pci controller structure
* (add regions, override default access routines, etc) or perform
* certain pre-initialization actions.
*/
#if defined(CONFIG_PCI)
int pci_pre_init(struct pci_controller *hose)
{
unsigned long addr;
/*
* Set priority for all PLB3 devices to 0.
* Set PLB3 arbiter to fair mode.
*/
mfsdr(SD0_AMP1, addr);
mtsdr(SD0_AMP1, (addr & 0x000000FF) | 0x0000FF00);
addr = mfdcr(PLB3_ACR);
mtdcr(PLB3_ACR, addr | 0x80000000);
/*
* Set priority for all PLB4 devices to 0.
*/
mfsdr(SD0_AMP0, addr);
mtsdr(SD0_AMP0, (addr & 0x000000FF) | 0x0000FF00);
addr = mfdcr(PLB4_ACR) | 0xa0000000; /* Was 0x8---- */
mtdcr(PLB4_ACR, addr);
/*
* Set Nebula PLB4 arbiter to fair mode.
*/
/* Segment0 */
addr = (mfdcr(PLB0_ACR) & ~PLB0_ACR_PPM_MASK) | PLB0_ACR_PPM_FAIR;
addr = (addr & ~PLB0_ACR_HBU_MASK) | PLB0_ACR_HBU_ENABLED;
addr = (addr & ~PLB0_ACR_RDP_MASK) | PLB0_ACR_RDP_4DEEP;
addr = (addr & ~PLB0_ACR_WRP_MASK) | PLB0_ACR_WRP_2DEEP;
mtdcr(PLB0_ACR, addr);
/* Segment1 */
addr = (mfdcr(PLB1_ACR) & ~PLB1_ACR_PPM_MASK) | PLB1_ACR_PPM_FAIR;
addr = (addr & ~PLB1_ACR_HBU_MASK) | PLB1_ACR_HBU_ENABLED;
addr = (addr & ~PLB1_ACR_RDP_MASK) | PLB1_ACR_RDP_4DEEP;
addr = (addr & ~PLB1_ACR_WRP_MASK) | PLB1_ACR_WRP_2DEEP;
mtdcr(PLB1_ACR, addr);
return 1;
}
#endif /* defined(CONFIG_PCI) */
#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT)
void pci_master_init(struct pci_controller *hose)
{

60
board/esd/pmc440/pmc440.c
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@ -478,7 +478,7 @@ int checkboard(void)
/*
* Assign interrupts to PCI devices. Some OSs rely on this.
*/
void pmc440_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
void board_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
{
unsigned char int_line[] = {IRQ_PCIC, IRQ_PCID, IRQ_PCIA, IRQ_PCIB};
@ -488,64 +488,6 @@ void pmc440_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
#endif
/*
* pci_pre_init
*
* This routine is called just prior to registering the hose and gives
* the board the opportunity to check things. Returning a value of zero
* indicates that things are bad & PCI initialization should be aborted.
*
* Different boards may wish to customize the pci controller structure
* (add regions, override default access routines, etc) or perform
* certain pre-initialization actions.
*/
#if defined(CONFIG_PCI)
int pci_pre_init(struct pci_controller *hose)
{
unsigned long addr;
/*
* Set priority for all PLB3 devices to 0.
* Set PLB3 arbiter to fair mode.
*/
mfsdr(SD0_AMP1, addr);
mtsdr(SD0_AMP1, (addr & 0x000000FF) | 0x0000FF00);
addr = mfdcr(PLB3_ACR);
mtdcr(PLB3_ACR, addr | 0x80000000);
/*
* Set priority for all PLB4 devices to 0.
*/
mfsdr(SD0_AMP0, addr);
mtsdr(SD0_AMP0, (addr & 0x000000FF) | 0x0000FF00);
addr = mfdcr(PLB4_ACR) | 0xa0000000; /* Was 0x8---- */
mtdcr(PLB4_ACR, addr);
/*
* Set Nebula PLB4 arbiter to fair mode.
*/
/* Segment0 */
addr = (mfdcr(PLB0_ACR) & ~PLB0_ACR_PPM_MASK) | PLB0_ACR_PPM_FAIR;
addr = (addr & ~PLB0_ACR_HBU_MASK) | PLB0_ACR_HBU_ENABLED;
addr = (addr & ~PLB0_ACR_RDP_MASK) | PLB0_ACR_RDP_4DEEP;
addr = (addr & ~PLB0_ACR_WRP_MASK) | PLB0_ACR_WRP_2DEEP;
mtdcr(PLB0_ACR, addr);
/* Segment1 */
addr = (mfdcr(PLB1_ACR) & ~PLB1_ACR_PPM_MASK) | PLB1_ACR_PPM_FAIR;
addr = (addr & ~PLB1_ACR_HBU_MASK) | PLB1_ACR_HBU_ENABLED;
addr = (addr & ~PLB1_ACR_RDP_MASK) | PLB1_ACR_RDP_4DEEP;
addr = (addr & ~PLB1_ACR_WRP_MASK) | PLB1_ACR_WRP_2DEEP;
mtdcr(PLB1_ACR, addr);
#ifdef CONFIG_PCI_PNP
hose->fixup_irq = pmc440_pci_fixup_irq;
#endif
return 1;
}
#endif /* defined(CONFIG_PCI) */
/*
* pci_target_init
*
* The bootstrap configuration provides default settings for the pci

49
board/gdsys/gdppc440etx/gdppc440etx.c
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@ -29,6 +29,7 @@
#include <ppc4xx.h>
#include <asm/processor.h>
#include <asm/io.h>
#include <asm/4xx_pci.h>
DECLARE_GLOBAL_DATA_PTR;
@ -158,55 +159,13 @@ int checkboard(void)
}
/*
* pci_pre_init
*
* This routine is called just prior to registering the hose and gives
* the board the opportunity to check things. Returning a value of zero
* indicates that things are bad & PCI initialization should be aborted.
*
* Different boards may wish to customize the pci controller structure
* (add regions, override default access routines, etc) or perform
* certain pre-initialization actions.
*
* Override weak pci_pre_init()
*/
#if defined(CONFIG_PCI)
int pci_pre_init(struct pci_controller *hose)
{
unsigned long addr;
/*
* Set priority for all PLB3 devices to 0.
* Set PLB3 arbiter to fair mode.
*/
mfsdr(SD0_AMP1, addr);
mtsdr(SD0_AMP1, (addr & 0x000000FF) | 0x0000FF00);
addr = mfdcr(PLB3_ACR);
mtdcr(PLB3_ACR, addr | 0x80000000);
/*
* Set priority for all PLB4 devices to 0.
*/
mfsdr(SD0_AMP0, addr);
mtsdr(SD0_AMP0, (addr & 0x000000FF) | 0x0000FF00);
addr = mfdcr(PLB4_ACR) | 0xa0000000; /* Was 0x8---- */
mtdcr(PLB4_ACR, addr);
/*
* Set Nebula PLB4 arbiter to fair mode.
*/
/* Segment0 */
addr = (mfdcr(PLB0_ACR) & ~PLB0_ACR_PPM_MASK) | PLB0_ACR_PPM_FAIR;
addr = (addr & ~PLB0_ACR_HBU_MASK) | PLB0_ACR_HBU_ENABLED;
addr = (addr & ~PLB0_ACR_RDP_MASK) | PLB0_ACR_RDP_4DEEP;
addr = (addr & ~PLB0_ACR_WRP_MASK) | PLB0_ACR_WRP_2DEEP;
mtdcr(PLB0_ACR, addr);
/* Segment1 */
addr = (mfdcr(PLB1_ACR) & ~PLB1_ACR_PPM_MASK) | PLB1_ACR_PPM_FAIR;
addr = (addr & ~PLB1_ACR_HBU_MASK) | PLB1_ACR_HBU_ENABLED;
addr = (addr & ~PLB1_ACR_RDP_MASK) | PLB1_ACR_RDP_4DEEP;
addr = (addr & ~PLB1_ACR_WRP_MASK) | PLB1_ACR_WRP_2DEEP;
mtdcr(PLB1_ACR, addr);
/* First call common code */
__pci_pre_init(hose);
/* enable 66 MHz ext. Clock */
out32(GPIO1_TCR, in32(GPIO1_TCR) | 0x00008000);

60
board/korat/korat.c
Unescape View File

@ -595,71 +595,13 @@ int checkboard(void)
/*
* Assign interrupts to PCI devices.
*/
void korat_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
void board_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
{
pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, VECNUM_EIRQ2);
}
#endif
/*
* pci_pre_init
*
* This routine is called just prior to registering the hose and gives
* the board the opportunity to check things. Returning a value of zero
* indicates that things are bad & PCI initialization should be aborted.
*
* Different boards may wish to customize the pci controller structure
* (add regions, override default access routines, etc) or perform
* certain pre-initialization actions.
*/
#if defined(CONFIG_PCI)
int pci_pre_init(struct pci_controller *hose)
{
unsigned long addr;
/*
* Set priority for all PLB3 devices to 0.
* Set PLB3 arbiter to fair mode.
*/
mfsdr(SD0_AMP1, addr);
mtsdr(SD0_AMP1, (addr & 0x000000FF) | 0x0000FF00);
addr = mfdcr(PLB3_ACR);
mtdcr(PLB3_ACR, addr | 0x80000000);
/*
* Set priority for all PLB4 devices to 0.
*/
mfsdr(SD0_AMP0, addr);
mtsdr(SD0_AMP0, (addr & 0x000000FF) | 0x0000FF00);
addr = mfdcr(PLB4_ACR) | 0xa0000000; /* Was 0x8---- */
mtdcr(PLB4_ACR, addr);
/*
* Set Nebula PLB4 arbiter to fair mode.
*/
/* Segment0 */
addr = (mfdcr(PLB0_ACR) & ~PLB0_ACR_PPM_MASK) | PLB0_ACR_PPM_FAIR;
addr = (addr & ~PLB0_ACR_HBU_MASK) | PLB0_ACR_HBU_ENABLED;
addr = (addr & ~PLB0_ACR_RDP_MASK) | PLB0_ACR_RDP_4DEEP;
addr = (addr & ~PLB0_ACR_WRP_MASK) | PLB0_ACR_WRP_2DEEP;
mtdcr(PLB0_ACR, addr);
/* Segment1 */
addr = (mfdcr(PLB1_ACR) & ~PLB1_ACR_PPM_MASK) | PLB1_ACR_PPM_FAIR;
addr = (addr & ~PLB1_ACR_HBU_MASK) | PLB1_ACR_HBU_ENABLED;
addr = (addr & ~PLB1_ACR_RDP_MASK) | PLB1_ACR_RDP_4DEEP;
addr = (addr & ~PLB1_ACR_WRP_MASK) | PLB1_ACR_WRP_2DEEP;
mtdcr(PLB1_ACR, addr);
#if defined(CONFIG_PCI_PNP)
hose->fixup_irq = korat_pci_fixup_irq;
#endif
return 1;
}
#endif /* defined(CONFIG_PCI) */
/*
* pci_target_init
*
* The bootstrap configuration provides default settings for the pci

55
board/lwmon5/lwmon5.c
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@ -276,61 +276,6 @@ int checkboard(void)
}
/*************************************************************************
* pci_pre_init
*
* This routine is called just prior to registering the hose and gives
* the board the opportunity to check things. Returning a value of zero
* indicates that things are bad & PCI initialization should be aborted.
*
* Different boards may wish to customize the pci controller structure
* (add regions, override default access routines, etc) or perform
* certain pre-initialization actions.
*
************************************************************************/
#if defined(CONFIG_PCI)
int pci_pre_init(struct pci_controller *hose)
{
unsigned long addr;
/*-------------------------------------------------------------------------+
| Set priority for all PLB3 devices to 0.
| Set PLB3 arbiter to fair mode.
+-------------------------------------------------------------------------*/
mfsdr(SD0_AMP1, addr);
mtsdr(SD0_AMP1, (addr & 0x000000FF) | 0x0000FF00);
addr = mfdcr(PLB3_ACR);
mtdcr(PLB3_ACR, addr | 0x80000000);
/*-------------------------------------------------------------------------+
| Set priority for all PLB4 devices to 0.
+-------------------------------------------------------------------------*/
mfsdr(SD0_AMP0, addr);
mtsdr(SD0_AMP0, (addr & 0x000000FF) | 0x0000FF00);
addr = mfdcr(PLB4_ACR) | 0xa0000000; /* Was 0x8---- */
mtdcr(PLB4_ACR, addr);
/*-------------------------------------------------------------------------+
| Set Nebula PLB4 arbiter to fair mode.
+-------------------------------------------------------------------------*/
/* Segment0 */
addr = (mfdcr(PLB0_ACR) & ~PLB0_ACR_PPM_MASK) | PLB0_ACR_PPM_FAIR;
addr = (addr & ~PLB0_ACR_HBU_MASK) | PLB0_ACR_HBU_ENABLED;
addr = (addr & ~PLB0_ACR_RDP_MASK) | PLB0_ACR_RDP_4DEEP;
addr = (addr & ~PLB0_ACR_WRP_MASK) | PLB0_ACR_WRP_2DEEP;
mtdcr(PLB0_ACR, addr);
/* Segment1 */
addr = (mfdcr(PLB1_ACR) & ~PLB1_ACR_PPM_MASK) | PLB1_ACR_PPM_FAIR;
addr = (addr & ~PLB1_ACR_HBU_MASK) | PLB1_ACR_HBU_ENABLED;
addr = (addr & ~PLB1_ACR_RDP_MASK) | PLB1_ACR_RDP_4DEEP;
addr = (addr & ~PLB1_ACR_WRP_MASK) | PLB1_ACR_WRP_2DEEP;
mtdcr(PLB1_ACR, addr);
return 1;
}
#endif /* defined(CONFIG_PCI) */
/*************************************************************************
* pci_master_init
*
************************************************************************/

55
board/pcs440ep/pcs440ep.c
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@ -551,61 +551,6 @@ phys_size_t initdram (int board_type)
}
/*************************************************************************
* pci_pre_init
*
* This routine is called just prior to registering the hose and gives
* the board the opportunity to check things. Returning a value of zero
* indicates that things are bad & PCI initialization should be aborted.
*
* Different boards may wish to customize the pci controller structure
* (add regions, override default access routines, etc) or perform
* certain pre-initialization actions.
*
************************************************************************/
#if defined(CONFIG_PCI)
int pci_pre_init(struct pci_controller *hose)
{
unsigned long addr;
/*-------------------------------------------------------------------------+
| Set priority for all PLB3 devices to 0.
| Set PLB3 arbiter to fair mode.
+-------------------------------------------------------------------------*/
mfsdr(SD0_AMP1, addr);
mtsdr(SD0_AMP1, (addr & 0x000000FF) | 0x0000FF00);
addr = mfdcr(PLB3_ACR);
mtdcr(PLB3_ACR, addr | 0x80000000);
/*-------------------------------------------------------------------------+
| Set priority for all PLB4 devices to 0.
+-------------------------------------------------------------------------*/
mfsdr(SD0_AMP0, addr);
mtsdr(SD0_AMP0, (addr & 0x000000FF) | 0x0000FF00);
addr = mfdcr(PLB4_ACR) | 0xa0000000; /* Was 0x8---- */
mtdcr(PLB4_ACR, addr);
/*-------------------------------------------------------------------------+
| Set Nebula PLB4 arbiter to fair mode.
+-------------------------------------------------------------------------*/
/* Segment0 */
addr = (mfdcr(PLB0_ACR) & ~PLB0_ACR_PPM_MASK) | PLB0_ACR_PPM_FAIR;
addr = (addr & ~PLB0_ACR_HBU_MASK) | PLB0_ACR_HBU_ENABLED;
addr = (addr & ~PLB0_ACR_RDP_MASK) | PLB0_ACR_RDP_4DEEP;
addr = (addr & ~PLB0_ACR_WRP_MASK) | PLB0_ACR_WRP_2DEEP;
mtdcr(PLB0_ACR, addr);
/* Segment1 */
addr = (mfdcr(PLB1_ACR) & ~PLB1_ACR_PPM_MASK) | PLB1_ACR_PPM_FAIR;
addr = (addr & ~PLB1_ACR_HBU_MASK) | PLB1_ACR_HBU_ENABLED;
addr = (addr & ~PLB1_ACR_RDP_MASK) | PLB1_ACR_RDP_4DEEP;
addr = (addr & ~PLB1_ACR_WRP_MASK) | PLB1_ACR_WRP_2DEEP;
mtdcr(PLB1_ACR, addr);
return 1;
}
#endif /* defined(CONFIG_PCI) */
/*************************************************************************
* pci_master_init
*
************************************************************************/

30
board/prodrive/alpr/alpr.c
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@ -29,6 +29,7 @@
#include <ppc4xx_enet.h>
#include <miiphy.h>
#include <asm/processor.h>
#include <asm/4xx_pci.h>
DECLARE_GLOBAL_DATA_PTR;
@ -144,39 +145,20 @@ int checkboard (void)
return (0);
}
/*************************************************************************
* pci_pre_init
*
* This routine is called just prior to registering the hose and gives
* the board the opportunity to check things. Returning a value of zero
* indicates that things are bad & PCI initialization should be aborted.
*
* Different boards may wish to customize the pci controller structure
* (add regions, override default access routines, etc) or perform
* certain pre-initialization actions.
*
************************************************************************/
#if defined(CONFIG_PCI)
/*
* Override weak pci_pre_init()
*/
int pci_pre_init(struct pci_controller *hose)
{
unsigned long strap;
/*--------------------------------------------------------------------------+
* The ocotea board is always configured as the host & requires the
* PCI arbiter to be enabled.
*--------------------------------------------------------------------------*/
mfsdr(SDR0_SDSTP1, strap);
if( (strap & SDR0_SDSTP1_PAE_MASK) == 0 ){
printf("PCI: SDR0_STRP1[%08lX] - PCI Arbiter disabled.\n",strap);
if (__pci_pre_init(hose) == 0)
return 0;
}
/* FPGA Init */
alpr_fpga_init();
return 1;
}
#endif /* defined(CONFIG_PCI) */
/*************************************************************************
* Override weak is_pci_host()
@ -193,8 +175,6 @@ int pci_pre_init(struct pci_controller * hose )
*
*
************************************************************************/
#if defined(CONFIG_PCI)
static void wait_for_pci_ready(void)
{
/*

31
board/prodrive/p3p440/p3p440.c
Unescape View File

@ -165,37 +165,6 @@ int misc_init_r (void)
}
/*************************************************************************
* pci_pre_init
*
* This routine is called just prior to registering the hose and gives
* the board the opportunity to check things. Returning a value of zero
* indicates that things are bad & PCI initialization should be aborted.
*
* Different boards may wish to customize the pci controller structure
* (add regions, override default access routines, etc) or perform
* certain pre-initialization actions.
*
************************************************************************/
#if defined(CONFIG_PCI)
int pci_pre_init(struct pci_controller *hose)
{
unsigned long strap;
/*--------------------------------------------------------------------------+
* The P3P440 board is always configured as the host & requires the
* PCI arbiter to be disabled because it's an PMC module.
*--------------------------------------------------------------------------*/
strap = mfdcr(CPC0_STRP1);
if (strap & 0x00100000) {
printf("PCI: CPC0_STRP1[PAE] set.\n");
return 0;
}
return 1;
}
#endif /* defined(CONFIG_PCI) */
/*************************************************************************
* Override weak is_pci_host()
*
* This routine is called to determine if a pci scan should be

32
board/sandburst/common/sb_common.c
Unescape View File

@ -300,38 +300,6 @@ long int fixed_sdram (void)
}
#endif /* !defined(CONFIG_SPD_EEPROM) */
/*************************************************************************
* pci_pre_init
*
* This routine is called just prior to registering the hose and gives
* the board the opportunity to check things. Returning a value of zero
* indicates that things are bad & PCI initialization should be aborted.
*
* Different boards may wish to customize the pci controller structure
* (add regions, override default access routines, etc) or perform
* certain pre-initialization actions.
*
************************************************************************/
#if defined(CONFIG_PCI)
int pci_pre_init(struct pci_controller * hose )
{
unsigned long strap;
/*--------------------------------------------------------------------------+
* The metrobox is always configured as the host & requires the
* PCI arbiter to be enabled.
*--------------------------------------------------------------------------*/
mfsdr(SDR0_SDSTP1, strap);
if( (strap & SDR0_SDSTP1_PAE_MASK) == 0 ){
printf("PCI: SDR0_STRP1[%08lX] - PCI Arbiter disabled.\n",strap);
return 0;
}
return 1;
}
#endif /* defined(CONFIG_PCI) */
/*************************************************************************
* board_get_enetaddr
*

3
board/xes/xpedite1000/xpedite1000.c
Unescape View File

@ -136,6 +136,8 @@ phys_size_t initdram(int board_type)
}
/*
* Override weak pci_pre_init()
*
* This routine is called just prior to registering the hose and gives
* the board the opportunity to check things. Returning a value of zero
* indicates that things are bad & PCI initialization should be aborted.
@ -144,7 +146,6 @@ phys_size_t initdram(int board_type)
* (add regions, override default access routines, etc) or perform
* certain pre-initialization actions.
*/
#if defined(CONFIG_PCI)
int pci_pre_init(struct pci_controller * hose)
{

111
cpu/ppc4xx/4xx_pci.c
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@ -73,9 +73,7 @@
#include <common.h>
#include <command.h>
#if !defined(CONFIG_440)
#include <asm/4xx_pci.h>
#endif
#include <asm/processor.h>
#include <asm/io.h>
#include <pci.h>
@ -84,6 +82,14 @@
DECLARE_GLOBAL_DATA_PTR;
#if defined(CONFIG_405GP) || defined(CONFIG_405EP)
#if defined(CONFIG_PMC405)
ushort pmc405_pci_subsys_deviceid(void);
#endif
/*#define DEBUG*/
/*
* Board-specific pci initialization
* Platform code can reimplement pci_pre_init() if needed
@ -106,15 +112,8 @@ int __pci_pre_init(struct pci_controller *hose)
return 1;
}
int pci_pre_init(struct pci_controller *hose) __attribute__((weak, alias("__pci_pre_init")));
#if defined(CONFIG_405GP) || defined(CONFIG_405EP)
#if defined(CONFIG_PMC405)
ushort pmc405_pci_subsys_deviceid(void);
#endif
/*#define DEBUG*/
int pci_pre_init(struct pci_controller *hose)
__attribute__((weak, alias("__pci_pre_init")));
int __is_pci_host(struct pci_controller *hose)
{
@ -500,6 +499,10 @@ int __is_pci_host(struct pci_controller *hose)
int is_pci_host(struct pci_controller *hose)
__attribute__((weak, alias("__is_pci_host")));
#if defined(CONFIG_440EP) || defined(CONFIG_440EPX) || \
defined(CONFIG_440GR) || defined(CONFIG_440GRX)
#if defined(CONFIG_SYS_PCI_TARGET_INIT)
/*
* pci_target_init
*
@ -507,9 +510,6 @@ int is_pci_host(struct pci_controller *hose)
* inbound map (PIM). But the bootstrap config choices are limited and
* may not be sufficient for a given board.
*/
#if defined(CONFIG_SYS_PCI_TARGET_INIT)
#if defined(CONFIG_440EP) || defined(CONFIG_440EPX) || \
defined(CONFIG_440GR) || defined(CONFIG_440GRX)
void __pci_target_init(struct pci_controller *hose)
{
/*
@ -570,7 +570,68 @@ void __pci_target_init(struct pci_controller *hose)
pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
}
#endif /* CONFIG_SYS_PCI_TARGET_INIT */
/*
* pci_pre_init
*
* This routine is called just prior to registering the hose and gives
* the board the opportunity to check things. Returning a value of zero
* indicates that things are bad & PCI initialization should be aborted.
*
* Different boards may wish to customize the pci controller structure
* (add regions, override default access routines, etc) or perform
* certain pre-initialization actions.
*
*/
int __pci_pre_init(struct pci_controller *hose)
{
u32 reg;
/*
* Set priority for all PLB3 devices to 0.
* Set PLB3 arbiter to fair mode.
*/
mfsdr(SD0_AMP1, reg);
mtsdr(SD0_AMP1, (reg & 0x000000FF) | 0x0000FF00);
reg = mfdcr(PLB3_ACR);
mtdcr(PLB3_ACR, reg | 0x80000000);
/*
* Set priority for all PLB4 devices to 0.
*/
mfsdr(SD0_AMP0, reg);
mtsdr(SD0_AMP0, (reg & 0x000000FF) | 0x0000FF00);
reg = mfdcr(PLB4_ACR) | 0xa0000000;
mtdcr(PLB4_ACR, reg);
/*
* Set Nebula PLB4 arbiter to fair mode.
*/
/* Segment0 */
reg = (mfdcr(PLB0_ACR) & ~PLB0_ACR_PPM_MASK) | PLB0_ACR_PPM_FAIR;
reg = (reg & ~PLB0_ACR_HBU_MASK) | PLB0_ACR_HBU_ENABLED;
reg = (reg & ~PLB0_ACR_RDP_MASK) | PLB0_ACR_RDP_4DEEP;
reg = (reg & ~PLB0_ACR_WRP_MASK) | PLB0_ACR_WRP_2DEEP;
mtdcr(PLB0_ACR, reg);
/* Segment1 */
reg = (mfdcr(PLB1_ACR) & ~PLB1_ACR_PPM_MASK) | PLB1_ACR_PPM_FAIR;
reg = (reg & ~PLB1_ACR_HBU_MASK) | PLB1_ACR_HBU_ENABLED;
reg = (reg & ~PLB1_ACR_RDP_MASK) | PLB1_ACR_RDP_4DEEP;
reg = (reg & ~PLB1_ACR_WRP_MASK) | PLB1_ACR_WRP_2DEEP;
mtdcr(PLB1_ACR, reg);
#if defined(CONFIG_SYS_PCI_BOARD_FIXUP_IRQ)
hose->fixup_irq = board_pci_fixup_irq;
#endif
return 1;
}
#else /* defined(CONFIG_440EP) ... */
#if defined(CONFIG_SYS_PCI_TARGET_INIT)
void __pci_target_init(struct pci_controller * hose)
{
/*
@ -599,11 +660,31 @@ void __pci_target_init(struct pci_controller * hose)
out_le16((void *)PCIL0_CMD, in_le16((void *)PCIL0_CMD) |
PCI_COMMAND_MEMORY);
}
#endif /* CONFIG_SYS_PCI_TARGET_INIT */
int __pci_pre_init(struct pci_controller *hose)
{
/*
* This board is always configured as the host & requires the
* PCI arbiter to be enabled.
*/
if (!pci_arbiter_enabled()) {
printf("PCI: PCI Arbiter disabled!\n");
return 0;
}
return 1;
}
#endif /* defined(CONFIG_440EP) ... */
#if defined(CONFIG_SYS_PCI_TARGET_INIT)
void pci_target_init(struct pci_controller * hose)
__attribute__((weak, alias("__pci_target_init")));
#endif /* CONFIG_SYS_PCI_TARGET_INIT */
#endif /* defined(CONFIG_SYS_PCI_TARGET_INIT) */
int pci_pre_init(struct pci_controller *hose)
__attribute__((weak, alias("__pci_pre_init")));
int pci_440_init (struct pci_controller *hose)
{

2
cpu/ppc4xx/cpu.c
Unescape View File

@ -81,7 +81,7 @@ static int pci_async_enabled(void)
#if defined(CONFIG_PCI) && !defined(CONFIG_IOP480) && \
!defined(CONFIG_405) && !defined(CONFIG_405EX)
static int pci_arbiter_enabled(void)
int pci_arbiter_enabled(void)
{
#if defined(CONFIG_405GP)
return (mfdcr(CPC0_PSR) & PSR_PCI_ARBIT_EN);

5
include/asm-ppc/4xx_pci.h
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@ -1,6 +1,8 @@
#ifndef _405GP_PCI_H
#define _405GP_PCI_H
#include <pci.h>
/*----------------------------------------------------------------------------+
| 405GP PCI core memory map defines.
+----------------------------------------------------------------------------*/
@ -49,6 +51,9 @@
#define PCIDEVID_405GP 0x0
void board_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev);
int pci_arbiter_enabled(void);
int __pci_pre_init(struct pci_controller *hose);
void __pci_target_init(struct pci_controller *hose);
#endif

1
include/configs/PMC440.h
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@ -435,6 +435,7 @@
/* Board-specific PCI */
#define CONFIG_SYS_PCI_TARGET_INIT
#define CONFIG_SYS_PCI_MASTER_INIT
#define CONFIG_SYS_PCI_BOARD_FIXUP_IRQ
/* PCI identification */
#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */

1
include/configs/korat.h
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@ -360,6 +360,7 @@
/* Board-specific PCI */
#define CONFIG_SYS_PCI_TARGET_INIT
#define CONFIG_SYS_PCI_MASTER_INIT
#define CONFIG_SYS_PCI_BOARD_FIXUP_IRQ
#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
#define CONFIG_SYS_PCI_SUBSYS_ID 0xcafe /* Whatever */

1
include/configs/sequoia.h
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@ -364,6 +364,7 @@
/* Board-specific PCI */
#define CONFIG_SYS_PCI_TARGET_INIT
#define CONFIG_SYS_PCI_MASTER_INIT
#define CONFIG_SYS_PCI_BOARD_FIXUP_IRQ
#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
#define CONFIG_SYS_PCI_SUBSYS_ID 0xcafe /* Whatever */

3
include/ppc440.h
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@ -1276,7 +1276,8 @@
#define CPC0_STRP1_PAE_MASK (0x80000000 >> 11)
#define CPC0_STRP1_PISE_MASK (0x80000000 >> 13)
#endif /* defined(CONFIG_440GP) */
#if defined(CONFIG_440GX) || defined(CONFIG_440SP)
#if defined(CONFIG_440GX) || defined(CONFIG_440SP) || \
defined(CONFIG_460EX) || defined(CONFIG_460GT)
#define SDR0_SDSTP1_PAE_MASK (0x80000000 >> 13)
#define SDR0_SDSTP1_PISE_MASK (0x80000000 >> 15)
#endif /* defined(CONFIG_440GX) || defined(CONFIG_440SP) */

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