Tom Rini
8 years ago
commit
ae1b939930
@ -1,20 +0,0 @@ |
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/*
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* Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <mmc.h> |
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#include <pci_ids.h> |
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static struct pci_device_id mmc_supported[] = { |
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TCF_SDIO_0 }, |
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TCF_SDIO_1 }, |
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{}, |
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}; |
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int cpu_mmc_init(bd_t *bis) |
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{ |
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return pci_mmc_init("Topcliff SDHCI", mmc_supported); |
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} |
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@ -0,0 +1,78 @@ |
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/* |
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* Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com>
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* |
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* From coreboot src/arch/x86/wakeup.S |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <asm/acpi_s3.h> |
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#include <asm/processor.h> |
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#include <asm/processor-flags.h> |
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#define RELOCATED(x) ((x) - __wakeup + WAKEUP_BASE) |
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#define CODE_SEG (X86_GDT_ENTRY_16BIT_CS * X86_GDT_ENTRY_SIZE) |
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#define DATA_SEG (X86_GDT_ENTRY_16BIT_DS * X86_GDT_ENTRY_SIZE) |
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.code32 |
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.globl __wakeup
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__wakeup: |
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/* First prepare the jmp to the resume vector */ |
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mov 0x4(%esp), %eax /* vector */ |
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/* last 4 bits of linear addr are taken as offset */ |
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andw $0x0f, %ax |
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movw %ax, (__wakeup_offset) |
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mov 0x4(%esp), %eax |
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/* the rest is taken as segment */ |
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shr $4, %eax |
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movw %ax, (__wakeup_segment) |
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/* Activate the right segment descriptor real mode */ |
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ljmp $CODE_SEG, $RELOCATED(1f) |
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1: |
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/* 16 bit code from here on... */ |
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.code16 |
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/* |
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* Load the segment registers w/ properly configured segment |
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* descriptors. They will retain these configurations (limits, |
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* writability, etc.) once protected mode is turned off. |
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*/ |
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mov $DATA_SEG, %ax |
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mov %ax, %ds |
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mov %ax, %es |
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mov %ax, %fs |
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mov %ax, %gs |
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mov %ax, %ss |
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/* Turn off protection */ |
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movl %cr0, %eax |
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andl $~X86_CR0_PE, %eax |
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movl %eax, %cr0 |
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/* Now really going into real mode */ |
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ljmp $0, $RELOCATED(1f) |
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1: |
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movw $0x0, %ax |
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movw %ax, %ds |
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movw %ax, %es |
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movw %ax, %ss |
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movw %ax, %fs |
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movw %ax, %gs |
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/* |
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* This is a FAR JMP to the OS waking vector. |
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* The C code changes the address to be correct. |
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*/ |
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.byte 0xea
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__wakeup_offset = RELOCATED(.) |
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.word 0x0000
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__wakeup_segment = RELOCATED(.) |
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.word 0x0000
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.globl __wakeup_size
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__wakeup_size: |
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.long . - __wakeup |
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@ -0,0 +1,131 @@ |
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/*
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* Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#ifndef __ASM_ACPI_S3_H__ |
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#define __ASM_ACPI_S3_H__ |
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#define WAKEUP_BASE 0x600 |
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/* PM1_STATUS register */ |
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#define WAK_STS (1 << 15) |
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#define PCIEXPWAK_STS (1 << 14) |
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#define RTC_STS (1 << 10) |
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#define SLPBTN_STS (1 << 9) |
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#define PWRBTN_STS (1 << 8) |
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#define GBL_STS (1 << 5) |
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#define BM_STS (1 << 4) |
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#define TMR_STS (1 << 0) |
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/* PM1_CNT register */ |
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#define SLP_EN (1 << 13) |
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#define SLP_TYP_SHIFT 10 |
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#define SLP_TYP (7 << SLP_TYP_SHIFT) |
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#define SLP_TYP_S0 0 |
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#define SLP_TYP_S1 1 |
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#define SLP_TYP_S3 5 |
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#define SLP_TYP_S4 6 |
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#define SLP_TYP_S5 7 |
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/* Memory size reserved for S3 resume */ |
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#define S3_RESERVE_SIZE 0x1000 |
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#ifndef __ASSEMBLY__ |
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extern char __wakeup[]; |
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extern int __wakeup_size; |
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enum acpi_sleep_state { |
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ACPI_S0, |
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ACPI_S1, |
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ACPI_S2, |
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ACPI_S3, |
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ACPI_S4, |
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ACPI_S5, |
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}; |
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/**
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* acpi_ss_string() - get ACPI-defined sleep state string |
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* |
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* @pm1_cnt: ACPI-defined sleep state |
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* @return: a pointer to the sleep state string. |
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*/ |
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static inline char *acpi_ss_string(enum acpi_sleep_state state) |
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{ |
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char *ss_string[] = { "S0", "S1", "S2", "S3", "S4", "S5"}; |
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return ss_string[state]; |
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} |
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/**
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* acpi_sleep_from_pm1() - get ACPI-defined sleep state from PM1_CNT register |
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* |
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* @pm1_cnt: PM1_CNT register value |
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* @return: ACPI-defined sleep state if given valid PM1_CNT register value, |
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* -EINVAL otherwise. |
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*/ |
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static inline enum acpi_sleep_state acpi_sleep_from_pm1(u32 pm1_cnt) |
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{ |
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switch ((pm1_cnt & SLP_TYP) >> SLP_TYP_SHIFT) { |
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case SLP_TYP_S0: |
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return ACPI_S0; |
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case SLP_TYP_S1: |
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return ACPI_S1; |
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case SLP_TYP_S3: |
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return ACPI_S3; |
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case SLP_TYP_S4: |
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return ACPI_S4; |
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case SLP_TYP_S5: |
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return ACPI_S5; |
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} |
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return -EINVAL; |
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} |
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/**
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* chipset_prev_sleep_state() - Get chipset previous sleep state |
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* |
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* This returns chipset previous sleep state from ACPI registers. |
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* Platform codes must supply this routine in order to support ACPI S3. |
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* |
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* @return ACPI_S0/S1/S2/S3/S4/S5. |
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*/ |
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enum acpi_sleep_state chipset_prev_sleep_state(void); |
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/**
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* chipset_clear_sleep_state() - Clear chipset sleep state |
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* |
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* This clears chipset sleep state in ACPI registers. |
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* Platform codes must supply this routine in order to support ACPI S3. |
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*/ |
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void chipset_clear_sleep_state(void); |
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struct acpi_fadt; |
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/**
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* acpi_resume() - Do ACPI S3 resume |
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* |
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* This calls U-Boot wake up assembly stub and jumps to OS's wake up vector. |
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* |
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* @fadt: FADT table pointer in the ACPI table |
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* @return: Never returns |
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*/ |
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void acpi_resume(struct acpi_fadt *fadt); |
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/**
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* acpi_s3_reserve() - Reserve memory for ACPI S3 resume |
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* |
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* This copies memory where real mode interrupt handler stubs reside to the |
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* reserved place on the stack. |
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* |
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* This routine should be called by reserve_arch() before U-Boot is relocated |
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* when ACPI S3 resume is enabled. |
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* |
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* @return: 0 always |
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*/ |
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int acpi_s3_reserve(void); |
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#endif /* __ASSEMBLY__ */ |
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#endif /* __ASM_ACPI_S3_H__ */ |
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@ -0,0 +1,31 @@ |
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/*
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* Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#ifndef __CMOS_LAYOUT_H |
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#define __CMOS_LAYOUT_H |
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/*
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* The RTC internal registers and RAM is organized as two banks of 128 bytes |
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* each, called the standard and extended banks. The first 14 bytes of the |
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* standard bank contain the RTC time and date information along with four |
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* registers, A - D, that are used for configuration of the RTC. The extended |
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* bank contains a full 128 bytes of battery backed SRAM. |
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* |
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* For simplicity in U-Boot we only support CMOS in the standard bank, and |
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* its base address starts from offset 0x10, which leaves us 112 bytes space. |
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*/ |
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#define CMOS_BASE 0x10 |
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/*
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* The file records all offsets off CMOS_BASE that is currently used by |
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* U-Boot for various reasons. It is put in such a unified place in order |
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* to be consistent across platforms. |
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*/ |
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/* stack address for S3 boot in a FSP configuration, 4 bytes */ |
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#define CMOS_FSP_STACK_ADDR CMOS_BASE |
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#endif /* __CMOS_LAYOUT_H */ |
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@ -0,0 +1,43 @@ |
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/*
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* Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#ifndef __EARLY_CMOS_H |
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#define __EARLY_CMOS_H |
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/* CMOS actually resides in the RTC SRAM */ |
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#define CMOS_IO_PORT 0x70 |
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/**
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* cmos_read8() - Get 8-bit data stored at the given address |
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* |
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* This reads from CMOS for the 8-bit data stored at the given address. |
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* |
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* @addr: RTC SRAM address |
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* @return: 8-bit data stored at the given address |
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*/ |
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u8 cmos_read8(u8 addr); |
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/**
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* cmos_read16() - Get 16-bit data stored at the given address |
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* |
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* This reads from CMOS for the 16-bit data stored at the given address. |
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* |
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* @addr: RTC SRAM address |
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* @return: 16-bit data stored at the given address |
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*/ |
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u16 cmos_read16(u8 addr); |
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/**
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* cmos_read32() - Get 32-bit data stored at the given address |
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* |
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* This reads from CMOS for the 32-bit data stored at the given address. |
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* |
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* @addr: RTC SRAM address |
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* @return: 32-bit data stored at the given address |
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*/ |
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u32 cmos_read32(u8 addr); |
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#endif /* __EARLY_CMOS_H */ |
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@ -0,0 +1,82 @@ |
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/*
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* Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <asm/acpi_s3.h> |
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#include <asm/acpi_table.h> |
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#include <asm/post.h> |
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DECLARE_GLOBAL_DATA_PTR; |
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static void asmlinkage (*acpi_do_wakeup)(void *vector) = (void *)WAKEUP_BASE; |
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static void acpi_jump_to_wakeup(void *vector) |
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{ |
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/* Copy wakeup trampoline in place */ |
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memcpy((void *)WAKEUP_BASE, __wakeup, __wakeup_size); |
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printf("Jumping to OS waking vector %p\n", vector); |
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acpi_do_wakeup(vector); |
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} |
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void acpi_resume(struct acpi_fadt *fadt) |
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{ |
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void *wake_vec; |
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/* Turn on ACPI mode for S3 */ |
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enter_acpi_mode(fadt->pm1a_cnt_blk); |
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wake_vec = acpi_find_wakeup_vector(fadt); |
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/*
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* Restore the memory content starting from address 0x1000 which is |
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* used for the real mode interrupt handler stubs. |
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*/ |
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memcpy((void *)0x1000, (const void *)gd->arch.backup_mem, |
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S3_RESERVE_SIZE); |
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post_code(POST_OS_RESUME); |
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acpi_jump_to_wakeup(wake_vec); |
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} |
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int acpi_s3_reserve(void) |
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{ |
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/* adjust stack pointer for ACPI S3 resume backup memory */ |
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gd->start_addr_sp -= S3_RESERVE_SIZE; |
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gd->arch.backup_mem = gd->start_addr_sp; |
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gd->start_addr_sp &= ~0xf; |
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/*
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* U-Boot sets up the real mode interrupt handler stubs starting from |
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* address 0x1000. In most cases, the first 640K (0x00000 - 0x9ffff) |
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* system memory is reported as system RAM in E820 table to the OS. |
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* (see install_e820_map() implementation for each platform). So OS |
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* can use these memories whatever it wants. |
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* |
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* If U-Boot is in an S3 resume path, care must be taken not to corrupt |
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* these memorie otherwise OS data gets lost. Testing shows that, on |
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* Microsoft Windows 10 on Intel Baytrail its wake up vector happens to |
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* be installed at the same address 0x1000. While on Linux its wake up |
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* vector does not overlap this memory range, but after resume kernel |
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* checks low memory range per config option CONFIG_X86_RESERVE_LOW |
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* which is 64K by default to see whether a memory corruption occurs |
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* during the suspend/resume (it's harmless, but warnings are shown |
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* in the kernel dmesg logs). |
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* |
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* We cannot simply mark the these memory as reserved in E820 table |
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* because such configuration makes GRUB complain: unable to allocate |
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* real mode page. Hence we choose to back up these memories to the |
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* place where we reserved on our stack for our S3 resume work. |
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* Before jumping to OS wake up vector, we need restore the original |
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* content there (see acpi_resume() above). |
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*/ |
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if (gd->arch.prev_sleep_state == ACPI_S3) |
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memcpy((void *)gd->arch.backup_mem, (const void *)0x1000, |
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S3_RESERVE_SIZE); |
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return 0; |
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} |
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@ -0,0 +1,51 @@ |
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/*
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* Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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/*
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* This library provides CMOS (inside RTC SRAM) access routines at a very |
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* early stage when driver model is not available yet. Only read access is |
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* provided. The 16-bit/32-bit read are compatible with driver model RTC |
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* uclass write ops, that data is stored in little-endian mode. |
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*/ |
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#include <common.h> |
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#include <asm/early_cmos.h> |
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#include <asm/io.h> |
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u8 cmos_read8(u8 addr) |
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{ |
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outb(addr, CMOS_IO_PORT); |
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return inb(CMOS_IO_PORT + 1); |
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} |
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u16 cmos_read16(u8 addr) |
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{ |
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u16 value = 0; |
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u16 data; |
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int i; |
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for (i = 0; i < sizeof(value); i++) { |
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data = cmos_read8(addr + i); |
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value |= data << (i << 3); |
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} |
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|
||||||
|
return value; |
||||||
|
} |
||||||
|
|
||||||
|
u32 cmos_read32(u8 addr) |
||||||
|
{ |
||||||
|
u32 value = 0; |
||||||
|
u32 data; |
||||||
|
int i; |
||||||
|
|
||||||
|
for (i = 0; i < sizeof(value); i++) { |
||||||
|
data = cmos_read8(addr + i); |
||||||
|
value |= data << (i << 3); |
||||||
|
} |
||||||
|
|
||||||
|
return value; |
||||||
|
} |
||||||
Loading…
Reference in new issue