It's convenient to hold configurations for DDR3 PHY and EMIF in separate common place. This patch moves K2HK DDR3 PHY and EMIF configuration data with different rates and memory size to a common ddr3_cfg.c file. Acked-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Hao Zhang <hzhang@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>master
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/*
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* Keystone2: DDR3 configuration |
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* |
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* (C) Copyright 2012-2014 |
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* Texas Instruments Incorporated, <www.ti.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <i2c.h> |
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#include <asm/arch/ddr3.h> |
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#include <asm/arch/hardware.h> |
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DECLARE_GLOBAL_DATA_PTR; |
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/* DDR3 PHY configuration data with 1600M rate, 8GB size */ |
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struct ddr3_phy_config ddr3phy_1600_8g = { |
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.pllcr = 0x0001C000ul, |
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.pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK), |
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.pgcr1_val = ((1 << 2) | (1 << 7) | (1 << 23)), |
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.ptr0 = 0x42C21590ul, |
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.ptr1 = 0xD05612C0ul, |
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.ptr2 = 0, /* not set in gel */ |
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.ptr3 = 0x0D861A80ul, |
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.ptr4 = 0x0C827100ul, |
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.dcr_mask = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK), |
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.dcr_val = ((1 << 10)), |
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.dtpr0 = 0xA19DBB66ul, |
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.dtpr1 = 0x32868300ul, |
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.dtpr2 = 0x50035200ul, |
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.mr0 = 0x00001C70ul, |
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.mr1 = 0x00000006ul, |
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.mr2 = 0x00000018ul, |
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.dtcr = 0x730035C7ul, |
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.pgcr2 = 0x00F07A12ul, |
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.zq0cr1 = 0x0000005Dul, |
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.zq1cr1 = 0x0000005Bul, |
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.zq2cr1 = 0x0000005Bul, |
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.pir_v1 = 0x00000033ul, |
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.pir_v2 = 0x0000FF81ul, |
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}; |
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/* DDR3 EMIF configuration data with 1600M rate, 8GB size */ |
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struct ddr3_emif_config ddr3_1600_8g = { |
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.sdcfg = 0x6200CE6Aul, |
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.sdtim1 = 0x16709C55ul, |
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.sdtim2 = 0x00001D4Aul, |
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.sdtim3 = 0x435DFF54ul, |
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.sdtim4 = 0x553F0CFFul, |
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.zqcfg = 0xF0073200ul, |
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.sdrfc = 0x00001869ul, |
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}; |
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#ifdef CONFIG_K2HK_EVM |
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/* DDR3 PHY configuration data with 1333M rate, and 2GB size */ |
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struct ddr3_phy_config ddr3phy_1333_2g = { |
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.pllcr = 0x0005C000ul, |
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.pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK), |
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.pgcr1_val = ((1 << 2) | (1 << 7) | (1 << 23)), |
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.ptr0 = 0x42C21590ul, |
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.ptr1 = 0xD05612C0ul, |
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.ptr2 = 0, /* not set in gel */ |
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.ptr3 = 0x0B4515C2ul, |
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.ptr4 = 0x0A6E08B4ul, |
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.dcr_mask = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK), |
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.dcr_val = ((1 << 10)), |
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.dtpr0 = 0x8558AA55ul, |
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.dtpr1 = 0x32857280ul, |
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.dtpr2 = 0x5002C200ul, |
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.mr0 = 0x00001A60ul, |
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.mr1 = 0x00000006ul, |
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.mr2 = 0x00000010ul, |
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.dtcr = 0x710035C7ul, |
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.pgcr2 = 0x00F065B8ul, |
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.zq0cr1 = 0x0000005Dul, |
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.zq1cr1 = 0x0000005Bul, |
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.zq2cr1 = 0x0000005Bul, |
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.pir_v1 = 0x00000033ul, |
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.pir_v2 = 0x0000FF81ul, |
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}; |
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/* DDR3 EMIF configuration data with 1333M rate, and 2GB size */ |
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struct ddr3_emif_config ddr3_1333_2g = { |
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.sdcfg = 0x62008C62ul, |
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.sdtim1 = 0x125C8044ul, |
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.sdtim2 = 0x00001D29ul, |
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.sdtim3 = 0x32CDFF43ul, |
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.sdtim4 = 0x543F0ADFul, |
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.zqcfg = 0x70073200ul, |
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.sdrfc = 0x00001457ul, |
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}; |
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#endif |
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int ddr3_get_dimm_params(char *dimm_name) |
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{ |
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int ret; |
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int old_bus; |
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u8 spd_params[256]; |
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i2c_init(CONFIG_SYS_DAVINCI_I2C_SPEED, CONFIG_SYS_DAVINCI_I2C_SLAVE); |
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old_bus = i2c_get_bus_num(); |
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i2c_set_bus_num(1); |
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ret = i2c_read(0x53, 0, 1, spd_params, 256); |
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i2c_set_bus_num(old_bus); |
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dimm_name[0] = '\0'; |
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if (ret) { |
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puts("Cannot read DIMM params\n"); |
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return 1; |
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} |
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/*
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* We need to convert spd data to dimm parameters |
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* and to DDR3 EMIF and PHY regirsters values. |
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* For now we just return DIMM type string value. |
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* Caller may use this value to choose appropriate |
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* a pre-set DDR3 configuration |
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*/ |
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strncpy(dimm_name, (char *)&spd_params[0x80], 18); |
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dimm_name[18] = '\0'; |
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return 0; |
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} |
@ -0,0 +1,21 @@ |
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/*
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* Keystone2: DDR3 configuration |
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* |
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* (C) Copyright 2012-2014 |
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* Texas Instruments Incorporated, <www.ti.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#ifndef __DDR3_CFG_H |
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#define __DDR3_CFG_H |
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extern struct ddr3_phy_config ddr3phy_1600_8g; |
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extern struct ddr3_emif_config ddr3_1600_8g; |
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extern struct ddr3_phy_config ddr3phy_1333_2g; |
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extern struct ddr3_emif_config ddr3_1333_2g; |
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int ddr3_get_dimm_params(char *dimm_name); |
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#endif /* __DDR3_CFG_H */ |
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