Signed-off-by: Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> CC: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Acked-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>master
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#
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# Copyright (C) 2007
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# Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
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#
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# Copyright (C) 2007
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# Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
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#
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# Copyright (C) 2007
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# Kenati Technologies, Inc.
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#
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# board/ms7720se/Makefile
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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include $(TOPDIR)/config.mk |
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LIB = lib$(BOARD).a
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OBJS := ms7720se.o
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SOBJS := lowlevel_init.o
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$(LIB): $(OBJS) $(SOBJS) |
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$(AR) crv $@ $(OBJS) $(SOBJS)
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clean: |
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rm -f $(SOBJS) $(OBJS)
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distclean: clean |
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rm -f $(LIB) core *.bak .depend
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#########################################################################
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.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) |
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$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
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-include .depend |
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#########################################################################
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@ -0,0 +1,34 @@ |
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#
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# Copyright (C) 2007
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# Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
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#
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# Copyright (C) 2007
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# Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
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#
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# Copyright (C) 2007
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# Kenati Technologies, Inc.
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#
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# board/ms7722se/config.mk
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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# TEXT_BASE refers to image _after_ relocation.
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#
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# NOTE: Must match value used in u-boot.lds (in this directory).
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#
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TEXT_BASE = 0x8FFC0000
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@ -0,0 +1,268 @@ |
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/* |
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* (C) Copyright 2007 |
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* Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
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* |
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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.global lowlevel_init
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.text |
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.align 2
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lowlevel_init: |
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mov.l WTCSR_A,r1 |
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mov.l WTCSR_D,r0 |
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mov.w r0,@r1
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mov.l WTCNT_A,r1 |
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mov.l WTCNT_D,r0 |
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mov.w r0,@r1
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mov.l FRQCR_A,r1 |
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mov.l FRQCR_D,r0 |
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mov.w r0,@r1
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mov.l UCLKCR_A,r1 |
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mov.l UCLKCR_D,r0 |
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mov.w r0,@r1
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mov.l CMNCR_A, r1 |
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mov.l CMNCR_D, r0 |
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mov.l r0, @r1
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mov.l CS0BCR_A, r1 |
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mov.l CS0BCR_D, r0 |
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mov.l r0, @r1
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mov.l CS2BCR_A, r1 |
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mov.l CS2BCR_D, r0 |
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mov.l r0, @r1
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mov.l CS3BCR_A, r1 |
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mov.l CS3BCR_D, r0 |
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mov.l r0, @r1
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mov.l CS4BCR_A, r1 |
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mov.l CS4BCR_D, r0 |
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mov.l r0, @r1
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mov.l CS5ABCR_A, r1 |
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mov.l CS5ABCR_D, r0 |
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mov.l r0, @r1
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mov.l CS5BBCR_A, r1 |
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mov.l CS5BBCR_D, r0 |
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mov.l r0, @r1
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mov.l CS6ABCR_A, r1 |
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mov.l CS6ABCR_D, r0 |
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mov.l r0, @r1
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mov.l CS6BBCR_A, r1 |
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mov.l CS6BBCR_D, r0 |
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mov.l r0, @r1
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mov.l CS0WCR_A, r1 |
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mov.l CS0WCR_D, r0 |
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mov.l r0, @r1
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mov.l CS2WCR_A, r1 |
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mov.l CS2WCR_D, r0 |
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mov.l r0, @r1
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mov.l CS3WCR_A, r1 |
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mov.l CS3WCR_D, r0 |
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mov.l r0, @r1
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mov.l CS4WCR_A, r1 |
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mov.l CS4WCR_D, r0 |
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mov.l r0, @r1
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mov.l CS5AWCR_A, r1 |
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mov.l CS5AWCR_D, r0 |
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mov.l r0, @r1
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mov.l CS5BWCR_A, r1 |
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mov.l CS5BWCR_D, r0 |
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mov.l r0, @r1
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mov.l CS6AWCR_A, r1 |
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mov.l CS6AWCR_D, r0 |
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mov.l r0, @r1
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mov.l CS6BWCR_A, r1 |
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mov.l CS6BWCR_D, r0 |
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mov.l r0, @r1
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mov.l SDCR_A, r1 |
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mov.l SDCR_D1, r0 |
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mov.l r0, @r1
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mov.l RTCSR_A, r1 |
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mov.l RTCSR_D, r0 |
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mov.l r0, @r1
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mov.l RTCNT_A, r1 |
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mov.l RTCNT_D, r0 |
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mov.l r0, @r1
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mov.l RTCOR_A, r1 |
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mov.l RTCOR_D, r0 |
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mov.l r0, @r1
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mov.l SDCR_A, r1 |
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mov.l SDCR_D2, r0 |
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mov.l r0, @r1
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mov.l SDMR3_A, r1 |
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mov.l SDMR3_D, r0 |
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mov.w r0, @r1
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mov.l PCCR_A, r1 |
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mov.l PCCR_D, r0 |
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mov.w r0, @r1
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mov.l PDCR_A, r1 |
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mov.l PDCR_D, r0 |
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mov.w r0, @r1
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mov.l PECR_A, r1 |
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mov.l PECR_D, r0 |
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mov.w r0, @r1
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mov.l PGCR_A, r1 |
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mov.l PGCR_D, r0 |
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mov.w r0, @r1
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mov.l PHCR_A, r1 |
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mov.l PHCR_D, r0 |
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mov.w r0, @r1
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mov.l PPCR_A, r1 |
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mov.l PPCR_D, r0 |
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mov.w r0, @r1
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mov.l PTCR_A, r1 |
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mov.l PTCR_D, r0 |
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mov.w r0, @r1
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mov.l PVCR_A, r1 |
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mov.l PVCR_D, r0 |
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mov.w r0, @r1
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mov.l PSELA_A, r1 |
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mov.l PSELA_D, r0 |
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mov.w r0, @r1
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mov.l CCR_A, r1 |
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mov.l CCR_D, r0 |
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mov.l r0, @r1
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mov.l LED_A, r1 |
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mov.l LED_D, r0 |
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mov.b r0, @r1
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rts |
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nop |
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.align 4
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FRQCR_A: .long 0xA415FF80 /* FRQCR Address */ |
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WTCNT_A: .long 0xA415FF84 |
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WTCSR_A: .long 0xA415FF86 |
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UCLKCR_A: .long 0xA40A0008 |
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FRQCR_D: .long 0x1103 /* I:B:P=8:4:2 */ |
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WTCNT_D: .long 0x5A00 |
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WTCSR_D: .long 0xA506 |
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UCLKCR_D: .long 0xA5C0 |
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#define BSC_BASE 0xA4FD0000 |
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CMNCR_A: .long BSC_BASE |
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CS0BCR_A: .long BSC_BASE + 0x04 |
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CS2BCR_A: .long BSC_BASE + 0x08 |
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CS3BCR_A: .long BSC_BASE + 0x0C |
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CS4BCR_A: .long BSC_BASE + 0x10 |
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CS5ABCR_A: .long BSC_BASE + 0x14 |
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CS5BBCR_A: .long BSC_BASE + 0x18 |
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CS6ABCR_A: .long BSC_BASE + 0x1C |
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CS6BBCR_A: .long BSC_BASE + 0x20 |
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CS0WCR_A: .long BSC_BASE + 0x24 |
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CS2WCR_A: .long BSC_BASE + 0x28 |
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CS3WCR_A: .long BSC_BASE + 0x2C |
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CS4WCR_A: .long BSC_BASE + 0x30 |
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CS5AWCR_A: .long BSC_BASE + 0x34 |
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CS5BWCR_A: .long BSC_BASE + 0x38 |
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CS6AWCR_A: .long BSC_BASE + 0x3C |
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CS6BWCR_A: .long BSC_BASE + 0x40 |
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SDCR_A: .long BSC_BASE + 0x44 |
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RTCSR_A: .long BSC_BASE + 0x48 |
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RTCNT_A: .long BSC_BASE + 0x4C |
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RTCOR_A: .long BSC_BASE + 0x50 |
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SDMR3_A: .long BSC_BASE + 0x58C0 |
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CMNCR_D: .long 0x00000010 |
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CS0BCR_D: .long 0x36DB0400 |
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CS2BCR_D: .long 0x36DB0400 |
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CS3BCR_D: .long 0x36DB4600 |
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CS4BCR_D: .long 0x36DB0400 |
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CS5ABCR_D: .long 0x36DB0400 |
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CS5BBCR_D: .long 0x36DB0200 |
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CS6ABCR_D: .long 0x36DB0400 |
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CS6BBCR_D: .long 0x36DB0400 |
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CS0WCR_D: .long 0x00000B01 |
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CS2WCR_D: .long 0x00000500 |
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CS3WCR_D: .long 0x00006D1B |
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CS4WCR_D: .long 0x00000500 |
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CS5AWCR_D: .long 0x00000500 |
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CS5BWCR_D: .long 0x00000500 |
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CS6AWCR_D: .long 0x00000500 |
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CS6BWCR_D: .long 0x00000500 |
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SDCR_D1: .long 0x00000011 |
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RTCSR_D: .long 0xA55A0010 |
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RTCNT_D: .long 0xA55A001F |
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RTCOR_D: .long 0xA55A001F |
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SDMR3_D: .long 0x0000 |
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SDCR_D2: .long 0x00000811 |
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#define PFC_BASE 0xA4050100 |
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PCCR_A: .long PFC_BASE + 0x04 |
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PDCR_A: .long PFC_BASE + 0x06 |
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PECR_A: .long PFC_BASE + 0x08 |
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PGCR_A: .long PFC_BASE + 0x0C |
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PHCR_A: .long PFC_BASE + 0x0E |
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PPCR_A: .long PFC_BASE + 0x18 |
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PTCR_A: .long PFC_BASE + 0x1E |
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PVCR_A: .long PFC_BASE + 0x22 |
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PSELA_A: .long PFC_BASE + 0x24 |
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PCCR_D: .long 0x0000 |
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PDCR_D: .long 0x0000 |
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PECR_D: .long 0x0000 |
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PGCR_D: .long 0x0000 |
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PHCR_D: .long 0x0000 |
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PPCR_D: .long 0x00AA |
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PTCR_D: .long 0x0280 |
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PVCR_D: .long 0x0000 |
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PSELA_D: .long 0x0000 |
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CCR_A: .long 0xFFFFFFEC |
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!CCR_D: .long 0x0000000D |
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CCR_D: .long 0x0000000B |
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LED_A: .long 0xB6800000 |
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LED_D: .long 0xFF |
@ -0,0 +1,60 @@ |
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/*
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* Copyright (C) 2007 |
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* Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> |
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* |
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* Copyright (C) 2007 |
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* Nobuhiro Iwamatsu <iwamatsu@nigauri.org> |
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* |
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* Copyright (C) 2007 |
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* Kenati Technologies, Inc. |
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* |
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* board/ms7720se/ms7720se.c |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#include <common.h> |
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#include <asm/io.h> |
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#include <asm/processor.h> |
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#define LED_BASE 0xB0800000 |
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int checkboard(void) |
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{ |
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puts("BOARD: Hitachi UL MS7720SE\n"); |
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return 0; |
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} |
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|
int board_init(void) |
||||||
|
{ |
||||||
|
|
||||||
|
return 0; |
||||||
|
} |
||||||
|
|
||||||
|
int dram_init(void) |
||||||
|
{ |
||||||
|
DECLARE_GLOBAL_DATA_PTR; |
||||||
|
|
||||||
|
gd->bd->bi_memstart = CFG_SDRAM_BASE; |
||||||
|
gd->bd->bi_memsize = CFG_SDRAM_SIZE; |
||||||
|
printf("DRAM: %dMB\n", CFG_SDRAM_SIZE / (1024 * 1024)); |
||||||
|
return 0; |
||||||
|
} |
||||||
|
|
||||||
|
void led_set_state(unsigned short value) |
||||||
|
{ |
||||||
|
outw(value & 0xFF, LED_BASE); |
||||||
|
} |
@ -0,0 +1,108 @@ |
|||||||
|
/* |
||||||
|
* Copyrigth (c) 2007 |
||||||
|
* Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> |
||||||
|
* |
||||||
|
* Copyrigth (c) 2007 |
||||||
|
* Nobuhiro Iwamatsu <iwamatsu@nigauri.org> |
||||||
|
* |
||||||
|
* See file CREDITS for list of people who contributed to this |
||||||
|
* project. |
||||||
|
* |
||||||
|
* This program is free software; you can redistribute it and/or |
||||||
|
* modify it under the terms of the GNU General Public License as |
||||||
|
* published by the Free Software Foundation; either version 2 of |
||||||
|
* the License, or (at your option) any later version. |
||||||
|
* |
||||||
|
* This program is distributed in the hope that it will be useful, |
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||||
|
* GNU General Public License for more details. |
||||||
|
* |
||||||
|
* You should have received a copy of the GNU General Public License |
||||||
|
* along with this program; if not, write to the Free Software |
||||||
|
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||||
|
* MA 02111-1307 USA |
||||||
|
*/ |
||||||
|
|
||||||
|
OUTPUT_FORMAT("elf32-sh-linux", "elf32-sh-linux", "elf32-sh-linux") |
||||||
|
OUTPUT_ARCH(sh) |
||||||
|
ENTRY(_start) |
||||||
|
|
||||||
|
SECTIONS |
||||||
|
{ |
||||||
|
/* |
||||||
|
Base address of internal SDRAM is 0x0C000000. |
||||||
|
Although size of SDRAM can be either 16 or 32 MBytes, |
||||||
|
we assume 16 MBytes (ie ignore upper half if the full |
||||||
|
32 MBytes is present). |
||||||
|
|
||||||
|
NOTE: This address must match with the definition of |
||||||
|
TEXT_BASE in config.mk (in this directory). |
||||||
|
|
||||||
|
*/ |
||||||
|
. = 0x8C000000 + (64*1024*1024) - (256*1024); |
||||||
|
|
||||||
|
PROVIDE (reloc_dst = .); |
||||||
|
|
||||||
|
PROVIDE (_ftext = .); |
||||||
|
PROVIDE (_fcode = .); |
||||||
|
PROVIDE (_start = .); |
||||||
|
|
||||||
|
.text : |
||||||
|
{ |
||||||
|
cpu/sh3/start.o (.text) |
||||||
|
. = ALIGN(8192); |
||||||
|
common/environment.o (.ppcenv) |
||||||
|
. = ALIGN(8192); |
||||||
|
common/environment.o (.ppcenvr) |
||||||
|
. = ALIGN(8192); |
||||||
|
*(.text) |
||||||
|
. = ALIGN(4); |
||||||
|
} =0xFF |
||||||
|
PROVIDE (_ecode = .); |
||||||
|
.rodata : |
||||||
|
{ |
||||||
|
*(.rodata) |
||||||
|
. = ALIGN(4); |
||||||
|
} |
||||||
|
PROVIDE (_etext = .); |
||||||
|
|
||||||
|
|
||||||
|
PROVIDE (_fdata = .); |
||||||
|
.data : |
||||||
|
{ |
||||||
|
*(.data) |
||||||
|
. = ALIGN(4); |
||||||
|
} |
||||||
|
PROVIDE (_edata = .); |
||||||
|
|
||||||
|
PROVIDE (_fgot = .); |
||||||
|
.got : |
||||||
|
{ |
||||||
|
*(.got) |
||||||
|
. = ALIGN(4); |
||||||
|
} |
||||||
|
PROVIDE (_egot = .); |
||||||
|
|
||||||
|
PROVIDE (__u_boot_cmd_start = .); |
||||||
|
.u_boot_cmd : |
||||||
|
{ |
||||||
|
*(.u_boot_cmd) |
||||||
|
. = ALIGN(4); |
||||||
|
} |
||||||
|
PROVIDE (__u_boot_cmd_end = .); |
||||||
|
|
||||||
|
PROVIDE (reloc_dst_end = .); |
||||||
|
/* _reloc_dst_end = .; */ |
||||||
|
|
||||||
|
PROVIDE (bss_start = .); |
||||||
|
PROVIDE (__bss_start = .); |
||||||
|
.bss : |
||||||
|
{ |
||||||
|
*(.bss) |
||||||
|
. = ALIGN(4); |
||||||
|
} |
||||||
|
PROVIDE (bss_end = .); |
||||||
|
|
||||||
|
PROVIDE (_end = .); |
||||||
|
} |
@ -0,0 +1,134 @@ |
|||||||
|
/*
|
||||||
|
* Configuation settings for the Hitachi Solution Engine 7720 |
||||||
|
* |
||||||
|
* Copyright (C) 2007 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> |
||||||
|
* |
||||||
|
* See file CREDITS for list of people who contributed to this |
||||||
|
* project. |
||||||
|
* |
||||||
|
* This program is free software; you can redistribute it and/or |
||||||
|
* modify it under the terms of the GNU General Public License as |
||||||
|
* published by the Free Software Foundation; either version 2 of |
||||||
|
* the License, or (at your option) any later version. |
||||||
|
* |
||||||
|
* This program is distributed in the hope that it will be useful, |
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||||
|
* GNU General Public License for more details. |
||||||
|
* |
||||||
|
* You should have received a copy of the GNU General Public License |
||||||
|
* along with this program; if not, write to the Free Software |
||||||
|
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||||
|
* MA 02111-1307 USA |
||||||
|
*/ |
||||||
|
|
||||||
|
#ifndef __MS7720SE_H |
||||||
|
#define __MS7720SE_H |
||||||
|
|
||||||
|
#undef DEBUG |
||||||
|
#define CONFIG_SH 1 |
||||||
|
#define CONFIG_SH3 1 |
||||||
|
#define CONFIG_CPU_SH7720 1 |
||||||
|
#define CONFIG_MS7720SE 1 |
||||||
|
|
||||||
|
#define CONFIG_CMD_FLASH |
||||||
|
#define CONFIG_CMD_ENV |
||||||
|
#define CONFIG_CMD_SDRAM |
||||||
|
#define CONFIG_CMD_MEMORY |
||||||
|
#define CONFIG_CMD_CACHE |
||||||
|
#define CONFIG_CMD_PCMCIA |
||||||
|
#define CONFIG_CMD_IDE |
||||||
|
#define CONFIG_CMD_EXT2 |
||||||
|
|
||||||
|
#define CFG_CMD_PCMCIA 0x01 |
||||||
|
#define CFG_CMD_IDE 0x02 |
||||||
|
|
||||||
|
#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | \ |
||||||
|
CFG_CMD_IDE|CFG_CMD_PCMCIA) & \
|
||||||
|
~(CFG_CMD_FPGA)) |
||||||
|
|
||||||
|
#define CONFIG_BAUDRATE 115200 |
||||||
|
#define CONFIG_BOOTARGS "console=ttySC0,115200" |
||||||
|
#define CONFIG_BOOTFILE /boot/zImage |
||||||
|
#define CONFIG_LOADADDR 0x8E000000 |
||||||
|
|
||||||
|
#define CONFIG_VERSION_VARIABLE |
||||||
|
#undef CONFIG_SHOW_BOOT_PROGRESS |
||||||
|
|
||||||
|
/* MEMORY */ |
||||||
|
#define MS7720SE_SDRAM_BASE 0x8C000000 |
||||||
|
#define MS7720SE_FLASH_BASE_1 0xA0000000 |
||||||
|
#define MS7720SE_FLASH_BANK_SIZE (8 * 1024 * 1024) |
||||||
|
|
||||||
|
#define CFG_LONGHELP /* undef to save memory */ |
||||||
|
#define CFG_PROMPT "=> " /* Monitor Command Prompt */ |
||||||
|
#define CFG_CBSIZE 256 /* Buffer size for input from the Console */ |
||||||
|
#define CFG_PBSIZE 256 /* Buffer size for Console output */ |
||||||
|
#define CFG_MAXARGS 16 /* max args accepted for monitor commands */ |
||||||
|
/* Buffer size for Boot Arguments passed to kernel */ |
||||||
|
#define CFG_BARGSIZE 512 |
||||||
|
/* List of legal baudrate settings for this board */ |
||||||
|
#define CFG_BAUDRATE_TABLE { 115200 } |
||||||
|
|
||||||
|
/* SCIF */ |
||||||
|
#define CFG_SCIF_CONSOLE 1 |
||||||
|
#define CONFIG_CONS_SCIF0 1 |
||||||
|
|
||||||
|
#define CFG_MEMTEST_START MS7720SE_SDRAM_BASE |
||||||
|
#define CFG_MEMTEST_END (CFG_MEMTEST_START + (60 * 1024 * 1024)) |
||||||
|
|
||||||
|
#define CFG_SDRAM_BASE MS7720SE_SDRAM_BASE |
||||||
|
#define CFG_SDRAM_SIZE (64 * 1024 * 1024) |
||||||
|
|
||||||
|
#define CFG_LOAD_ADDR (CFG_SDRAM_BASE + 32 * 1024 * 1024) |
||||||
|
#define CFG_MONITOR_BASE MS7720SE_FLASH_BASE_1 |
||||||
|
#define CFG_MONITOR_LEN (128 * 1024) |
||||||
|
#define CFG_MALLOC_LEN (256 * 1024) |
||||||
|
#define CFG_GBL_DATA_SIZE 256 |
||||||
|
#define CFG_BOOTMAPSZ (8 * 1024 * 1024) |
||||||
|
|
||||||
|
|
||||||
|
/* FLASH */ |
||||||
|
#define CFG_FLASH_CFI |
||||||
|
#define CFG_FLASH_CFI_DRIVER |
||||||
|
#undef CFG_FLASH_QUIET_TEST |
||||||
|
#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ |
||||||
|
|
||||||
|
#define CFG_FLASH_BASE MS7720SE_FLASH_BASE_1 |
||||||
|
|
||||||
|
#define CFG_MAX_FLASH_SECT 150 |
||||||
|
#define CFG_MAX_FLASH_BANKS 1 |
||||||
|
#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } |
||||||
|
|
||||||
|
#define CFG_ENV_IS_IN_FLASH |
||||||
|
#define CFG_ENV_SECT_SIZE (64 * 1024) |
||||||
|
#define CFG_ENV_SIZE CFG_ENV_SECT_SIZE |
||||||
|
#define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN) |
||||||
|
#define CFG_FLASH_ERASE_TOUT 120000 |
||||||
|
#define CFG_FLASH_WRITE_TOUT 500 |
||||||
|
|
||||||
|
/* Board Clock */ |
||||||
|
#define CONFIG_SYS_CLK_FREQ 33333333 |
||||||
|
#define TMU_CLK_DIVIDER 4 /* 4 (default), 16, 64, 256 or 1024 */ |
||||||
|
#define CFG_HZ (CONFIG_SYS_CLK_FREQ / TMU_CLK_DIVIDER) |
||||||
|
|
||||||
|
/* PCMCIA */ |
||||||
|
#define CONFIG_IDE_PCMCIA 1 |
||||||
|
#define CONFIG_MARUBUN_PCCARD 1 |
||||||
|
#define CONFIG_PCMCIA_SLOT_A 1 |
||||||
|
#define CFG_IDE_MAXDEVICE 1 |
||||||
|
#define CFG_MARUBUN_MRSHPC 0xb83fffe0 |
||||||
|
#define CFG_MARUBUN_MW1 0xb8400000 |
||||||
|
#define CFG_MARUBUN_MW2 0xb8500000 |
||||||
|
#define CFG_MARUBUN_IO 0xb8600000 |
||||||
|
|
||||||
|
#define CFG_PIO_MODE 1 |
||||||
|
#define CFG_IDE_MAXBUS 1 |
||||||
|
#define CONFIG_DOS_PARTITION 1 |
||||||
|
#define CFG_ATA_BASE_ADDR CFG_MARUBUN_IO /* base address */ |
||||||
|
#define CFG_ATA_IDE0_OFFSET 0x01F0 /* ide0 offste */ |
||||||
|
#define CFG_ATA_DATA_OFFSET 0 /* data reg offset */ |
||||||
|
#define CFG_ATA_REG_OFFSET 0 /* reg offset */ |
||||||
|
#define CFG_ATA_ALT_OFFSET 0x200 /* alternate register offset */ |
||||||
|
|
||||||
|
#endif /* __MS7720SE_H */ |
Loading…
Reference in new issue