Add Faraday's ftgmac100 (gigabit ethernet) MAC controller's driver. Signed-off-by: Macpaul Lin <macpaul@andestech.com>master
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/*
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* Faraday FTGMAC100 Ethernet |
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* |
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* (C) Copyright 2009 Faraday Technology |
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* Po-Yu Chuang <ratbert@faraday-tech.com> |
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* |
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* (C) Copyright 2010 Andes Technology |
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* Macpaul Lin <macpaul@andestech.com> |
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* |
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* This program is free software; you can redistribute it and/or modify |
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* it under the terms of the GNU General Public License as published by |
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* the Free Software Foundation; either version 2 of the License, or |
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* (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. |
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*/ |
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#include <config.h> |
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#include <common.h> |
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#include <malloc.h> |
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#include <net.h> |
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#include <asm/io.h> |
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#include <linux/mii.h> |
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#include "ftgmac100.h" |
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#define ETH_ZLEN 60 |
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#define mdelay(n) ({unsigned long msec = (n); while (msec--) udelay(1000); }) |
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/* RBSR - hw default init value is also 0x640 */ |
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#define RBSR_DEFAULT_VALUE 0x640 |
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/* PKTBUFSTX/PKTBUFSRX must both be power of 2 */ |
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#define PKTBUFSTX 4 /* must be power of 2 */ |
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struct ftgmac100_data { |
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struct ftgmac100_txdes txdes[PKTBUFSTX]; |
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struct ftgmac100_rxdes rxdes[PKTBUFSRX]; |
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int tx_index; |
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int rx_index; |
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int phy_addr; |
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}; |
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/*
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* struct mii_bus functions |
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*/ |
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static int ftgmac100_mdiobus_read(struct eth_device *dev, int phy_addr, |
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int regnum) |
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{ |
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struct ftgmac100 *ftgmac100 = (struct ftgmac100 *)dev->iobase; |
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int phycr; |
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int i; |
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phycr = readl(&ftgmac100->phycr); |
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/* preserve MDC cycle threshold */ |
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phycr &= FTGMAC100_PHYCR_MDC_CYCTHR_MASK; |
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phycr |= FTGMAC100_PHYCR_PHYAD(phy_addr) |
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| FTGMAC100_PHYCR_REGAD(regnum) |
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| FTGMAC100_PHYCR_MIIRD; |
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writel(phycr, &ftgmac100->phycr); |
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for (i = 0; i < 10; i++) { |
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phycr = readl(&ftgmac100->phycr); |
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if ((phycr & FTGMAC100_PHYCR_MIIRD) == 0) { |
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int data; |
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data = readl(&ftgmac100->phydata); |
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return FTGMAC100_PHYDATA_MIIRDATA(data); |
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} |
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mdelay(10); |
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} |
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debug("mdio read timed out\n"); |
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return -1; |
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} |
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static int ftgmac100_mdiobus_write(struct eth_device *dev, int phy_addr, |
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int regnum, u16 value) |
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{ |
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struct ftgmac100 *ftgmac100 = (struct ftgmac100 *)dev->iobase; |
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int phycr; |
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int data; |
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int i; |
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phycr = readl(&ftgmac100->phycr); |
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/* preserve MDC cycle threshold */ |
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phycr &= FTGMAC100_PHYCR_MDC_CYCTHR_MASK; |
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phycr |= FTGMAC100_PHYCR_PHYAD(phy_addr) |
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| FTGMAC100_PHYCR_REGAD(regnum) |
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| FTGMAC100_PHYCR_MIIWR; |
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data = FTGMAC100_PHYDATA_MIIWDATA(value); |
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writel(data, &ftgmac100->phydata); |
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writel(phycr, &ftgmac100->phycr); |
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for (i = 0; i < 10; i++) { |
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phycr = readl(&ftgmac100->phycr); |
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if ((phycr & FTGMAC100_PHYCR_MIIWR) == 0) { |
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debug("(phycr & FTGMAC100_PHYCR_MIIWR) == 0: " \
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"phy_addr: %x\n", phy_addr); |
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return 0; |
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} |
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mdelay(1); |
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} |
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debug("mdio write timed out\n"); |
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return -1; |
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} |
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int ftgmac100_phy_read(struct eth_device *dev, int addr, int reg, u16 *value) |
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{ |
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*value = ftgmac100_mdiobus_read(dev , addr, reg); |
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if (*value == -1) |
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return -1; |
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return 0; |
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} |
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int ftgmac100_phy_write(struct eth_device *dev, int addr, int reg, u16 value) |
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{ |
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if (ftgmac100_mdiobus_write(dev, addr, reg, value) == -1) |
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return -1; |
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return 0; |
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} |
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static int ftgmac100_phy_reset(struct eth_device *dev) |
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{ |
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struct ftgmac100_data *priv = dev->priv; |
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int i; |
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u16 status, adv; |
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adv = ADVERTISE_CSMA | ADVERTISE_ALL; |
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ftgmac100_phy_write(dev, priv->phy_addr, MII_ADVERTISE, adv); |
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printf("%s: Starting autonegotiation...\n", dev->name); |
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ftgmac100_phy_write(dev, priv->phy_addr, |
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MII_BMCR, (BMCR_ANENABLE | BMCR_ANRESTART)); |
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for (i = 0; i < 100000 / 100; i++) { |
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ftgmac100_phy_read(dev, priv->phy_addr, MII_BMSR, &status); |
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if (status & BMSR_ANEGCOMPLETE) |
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break; |
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mdelay(1); |
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} |
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if (status & BMSR_ANEGCOMPLETE) { |
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printf("%s: Autonegotiation complete\n", dev->name); |
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} else { |
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printf("%s: Autonegotiation timed out (status=0x%04x)\n", |
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dev->name, status); |
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return 0; |
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} |
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return 1; |
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} |
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static int ftgmac100_phy_init(struct eth_device *dev) |
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{ |
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struct ftgmac100_data *priv = dev->priv; |
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int phy_addr; |
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u16 phy_id, status, adv, lpa, stat_ge; |
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int media, speed, duplex; |
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int i; |
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/* Check if the PHY is up to snuff... */ |
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for (phy_addr = 0; phy_addr < CONFIG_PHY_MAX_ADDR; phy_addr++) { |
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ftgmac100_phy_read(dev, phy_addr, MII_PHYSID1, &phy_id); |
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/*
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* When it is unable to found PHY, |
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* the interface usually return 0xffff or 0x0000 |
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*/ |
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if (phy_id != 0xffff && phy_id != 0x0) { |
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printf("%s: found PHY at 0x%02x\n", |
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dev->name, phy_addr); |
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priv->phy_addr = phy_addr; |
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break; |
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} |
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} |
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if (phy_id == 0xffff || phy_id == 0x0) { |
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printf("%s: no PHY present\n", dev->name); |
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return 0; |
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} |
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ftgmac100_phy_read(dev, priv->phy_addr, MII_BMSR, &status); |
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if (!(status & BMSR_LSTATUS)) { |
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/* Try to re-negotiate if we don't have link already. */ |
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ftgmac100_phy_reset(dev); |
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for (i = 0; i < 100000 / 100; i++) { |
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ftgmac100_phy_read(dev, priv->phy_addr, |
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MII_BMSR, &status); |
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if (status & BMSR_LSTATUS) |
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break; |
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udelay(100); |
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} |
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} |
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if (!(status & BMSR_LSTATUS)) { |
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printf("%s: link down\n", dev->name); |
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return 0; |
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} |
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#ifdef CONFIG_FTGMAC100_EGIGA |
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/* 1000 Base-T Status Register */ |
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ftgmac100_phy_read(dev, priv->phy_addr, |
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MII_STAT1000, &stat_ge); |
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speed = (stat_ge & (LPA_1000FULL | LPA_1000HALF) |
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? 1 : 0); |
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duplex = ((stat_ge & LPA_1000FULL) |
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? 1 : 0); |
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if (speed) { /* Speed is 1000 */ |
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printf("%s: link up, 1000bps %s-duplex\n", |
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dev->name, duplex ? "full" : "half"); |
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return 0; |
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} |
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#endif |
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ftgmac100_phy_read(dev, priv->phy_addr, MII_ADVERTISE, &adv); |
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ftgmac100_phy_read(dev, priv->phy_addr, MII_LPA, &lpa); |
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media = mii_nway_result(lpa & adv); |
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speed = (media & (ADVERTISE_100FULL | ADVERTISE_100HALF) ? 1 : 0); |
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duplex = (media & ADVERTISE_FULL) ? 1 : 0; |
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printf("%s: link up, %sMbps %s-duplex\n", |
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dev->name, speed ? "100" : "10", duplex ? "full" : "half"); |
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return 1; |
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} |
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static int ftgmac100_update_link_speed(struct eth_device *dev) |
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{ |
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struct ftgmac100 *ftgmac100 = (struct ftgmac100 *)dev->iobase; |
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struct ftgmac100_data *priv = dev->priv; |
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unsigned short stat_fe; |
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unsigned short stat_ge; |
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unsigned int maccr; |
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#ifdef CONFIG_FTGMAC100_EGIGA |
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/* 1000 Base-T Status Register */ |
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ftgmac100_phy_read(dev, priv->phy_addr, MII_STAT1000, &stat_ge); |
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#endif |
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ftgmac100_phy_read(dev, priv->phy_addr, MII_BMSR, &stat_fe); |
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if (!(stat_fe & BMSR_LSTATUS)) /* link status up? */ |
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return 0; |
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/* read MAC control register and clear related bits */ |
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maccr = readl(&ftgmac100->maccr) & |
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~(FTGMAC100_MACCR_GIGA_MODE | |
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FTGMAC100_MACCR_FAST_MODE | |
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FTGMAC100_MACCR_FULLDUP); |
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#ifdef CONFIG_FTGMAC100_EGIGA |
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if (stat_ge & LPA_1000FULL) { |
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/* set gmac for 1000BaseTX and Full Duplex */ |
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maccr |= FTGMAC100_MACCR_GIGA_MODE | FTGMAC100_MACCR_FULLDUP; |
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} |
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if (stat_ge & LPA_1000HALF) { |
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/* set gmac for 1000BaseTX and Half Duplex */ |
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maccr |= FTGMAC100_MACCR_GIGA_MODE; |
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} |
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#endif |
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if (stat_fe & BMSR_100FULL) { |
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/* set MII for 100BaseTX and Full Duplex */ |
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maccr |= FTGMAC100_MACCR_FAST_MODE | FTGMAC100_MACCR_FULLDUP; |
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} |
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if (stat_fe & BMSR_10FULL) { |
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/* set MII for 10BaseT and Full Duplex */ |
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maccr |= FTGMAC100_MACCR_FULLDUP; |
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} |
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if (stat_fe & BMSR_100HALF) { |
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/* set MII for 100BaseTX and Half Duplex */ |
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maccr |= FTGMAC100_MACCR_FAST_MODE; |
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} |
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if (stat_fe & BMSR_10HALF) { |
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/* set MII for 10BaseT and Half Duplex */ |
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/* we have already clear these bits, do nothing */ |
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; |
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} |
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/* update MII config into maccr */ |
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writel(maccr, &ftgmac100->maccr); |
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return 1; |
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} |
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/*
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* Reset MAC |
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*/ |
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static void ftgmac100_reset(struct eth_device *dev) |
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{ |
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struct ftgmac100 *ftgmac100 = (struct ftgmac100 *)dev->iobase; |
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debug("%s()\n", __func__); |
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writel(FTGMAC100_MACCR_SW_RST, &ftgmac100->maccr); |
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while (readl(&ftgmac100->maccr) & FTGMAC100_MACCR_SW_RST) |
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; |
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} |
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/*
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* Set MAC address |
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*/ |
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static void ftgmac100_set_mac(struct eth_device *dev, |
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const unsigned char *mac) |
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{ |
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struct ftgmac100 *ftgmac100 = (struct ftgmac100 *)dev->iobase; |
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unsigned int maddr = mac[0] << 8 | mac[1]; |
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unsigned int laddr = mac[2] << 24 | mac[3] << 16 | mac[4] << 8 | mac[5]; |
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debug("%s(%x %x)\n", __func__, maddr, laddr); |
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writel(maddr, &ftgmac100->mac_madr); |
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writel(laddr, &ftgmac100->mac_ladr); |
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} |
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static void ftgmac100_set_mac_from_env(struct eth_device *dev) |
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{ |
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eth_getenv_enetaddr("ethaddr", dev->enetaddr); |
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ftgmac100_set_mac(dev, dev->enetaddr); |
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} |
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/*
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* disable transmitter, receiver |
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*/ |
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static void ftgmac100_halt(struct eth_device *dev) |
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{ |
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struct ftgmac100 *ftgmac100 = (struct ftgmac100 *)dev->iobase; |
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debug("%s()\n", __func__); |
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writel(0, &ftgmac100->maccr); |
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} |
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static int ftgmac100_init(struct eth_device *dev, bd_t *bd) |
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{ |
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struct ftgmac100 *ftgmac100 = (struct ftgmac100 *)dev->iobase; |
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struct ftgmac100_data *priv = dev->priv; |
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struct ftgmac100_txdes *txdes = priv->txdes; |
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struct ftgmac100_rxdes *rxdes = priv->rxdes; |
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unsigned int maccr; |
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int i; |
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debug("%s()\n", __func__); |
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ftgmac100_reset(dev); |
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/* set the ethernet address */ |
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ftgmac100_set_mac_from_env(dev); |
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/* disable all interrupts */ |
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writel(0, &ftgmac100->ier); |
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/* initialize descriptors */ |
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priv->tx_index = 0; |
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priv->rx_index = 0; |
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txdes[PKTBUFSTX - 1].txdes0 = FTGMAC100_TXDES0_EDOTR; |
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rxdes[PKTBUFSRX - 1].rxdes0 = FTGMAC100_RXDES0_EDORR; |
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for (i = 0; i < PKTBUFSTX; i++) { |
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/* TXBUF_BADR */ |
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txdes[i].txdes3 = 0; |
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txdes[i].txdes1 = 0; |
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} |
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for (i = 0; i < PKTBUFSRX; i++) { |
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/* RXBUF_BADR */ |
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rxdes[i].rxdes3 = (unsigned int)NetRxPackets[i]; |
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rxdes[i].rxdes0 &= ~FTGMAC100_RXDES0_RXPKT_RDY; |
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} |
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/* transmit ring */ |
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writel((unsigned int)txdes, &ftgmac100->txr_badr); |
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/* receive ring */ |
||||||
|
writel((unsigned int)rxdes, &ftgmac100->rxr_badr); |
||||||
|
|
||||||
|
/* poll receive descriptor automatically */ |
||||||
|
writel(FTGMAC100_APTC_RXPOLL_CNT(1), &ftgmac100->aptc); |
||||||
|
|
||||||
|
/* config receive buffer size register */ |
||||||
|
writel(FTGMAC100_RBSR_SIZE(RBSR_DEFAULT_VALUE), &ftgmac100->rbsr); |
||||||
|
|
||||||
|
/* enable transmitter, receiver */ |
||||||
|
maccr = FTGMAC100_MACCR_TXMAC_EN | |
||||||
|
FTGMAC100_MACCR_RXMAC_EN | |
||||||
|
FTGMAC100_MACCR_TXDMA_EN | |
||||||
|
FTGMAC100_MACCR_RXDMA_EN | |
||||||
|
FTGMAC100_MACCR_CRC_APD | |
||||||
|
FTGMAC100_MACCR_FULLDUP | |
||||||
|
FTGMAC100_MACCR_RX_RUNT | |
||||||
|
FTGMAC100_MACCR_RX_BROADPKT; |
||||||
|
|
||||||
|
writel(maccr, &ftgmac100->maccr); |
||||||
|
|
||||||
|
if (!ftgmac100_phy_init(dev)) { |
||||||
|
if (!ftgmac100_update_link_speed(dev)) |
||||||
|
return -1; |
||||||
|
} |
||||||
|
|
||||||
|
return 0; |
||||||
|
} |
||||||
|
|
||||||
|
/*
|
||||||
|
* Get a data block via Ethernet |
||||||
|
*/ |
||||||
|
static int ftgmac100_recv(struct eth_device *dev) |
||||||
|
{ |
||||||
|
struct ftgmac100_data *priv = dev->priv; |
||||||
|
struct ftgmac100_rxdes *curr_des; |
||||||
|
unsigned short rxlen; |
||||||
|
|
||||||
|
curr_des = &priv->rxdes[priv->rx_index]; |
||||||
|
|
||||||
|
if (!(curr_des->rxdes0 & FTGMAC100_RXDES0_RXPKT_RDY)) |
||||||
|
return -1; |
||||||
|
|
||||||
|
if (curr_des->rxdes0 & (FTGMAC100_RXDES0_RX_ERR | |
||||||
|
FTGMAC100_RXDES0_CRC_ERR | |
||||||
|
FTGMAC100_RXDES0_FTL | |
||||||
|
FTGMAC100_RXDES0_RUNT | |
||||||
|
FTGMAC100_RXDES0_RX_ODD_NB)) { |
||||||
|
return -1; |
||||||
|
} |
||||||
|
|
||||||
|
rxlen = FTGMAC100_RXDES0_VDBC(curr_des->rxdes0); |
||||||
|
|
||||||
|
debug("%s(): RX buffer %d, %x received\n", |
||||||
|
__func__, priv->rx_index, rxlen); |
||||||
|
|
||||||
|
/* pass the packet up to the protocol layers. */ |
||||||
|
NetReceive((void *)curr_des->rxdes3, rxlen); |
||||||
|
|
||||||
|
/* release buffer to DMA */ |
||||||
|
curr_des->rxdes0 &= ~FTGMAC100_RXDES0_RXPKT_RDY; |
||||||
|
|
||||||
|
priv->rx_index = (priv->rx_index + 1) % PKTBUFSRX; |
||||||
|
|
||||||
|
return 0; |
||||||
|
} |
||||||
|
|
||||||
|
/*
|
||||||
|
* Send a data block via Ethernet |
||||||
|
*/ |
||||||
|
static int |
||||||
|
ftgmac100_send(struct eth_device *dev, void *packet, int length) |
||||||
|
{ |
||||||
|
struct ftgmac100 *ftgmac100 = (struct ftgmac100 *)dev->iobase; |
||||||
|
struct ftgmac100_data *priv = dev->priv; |
||||||
|
struct ftgmac100_txdes *curr_des = &priv->txdes[priv->tx_index]; |
||||||
|
int start; |
||||||
|
|
||||||
|
if (curr_des->txdes0 & FTGMAC100_TXDES0_TXDMA_OWN) { |
||||||
|
debug("%s(): no TX descriptor available\n", __func__); |
||||||
|
return -1; |
||||||
|
} |
||||||
|
|
||||||
|
debug("%s(%x, %x)\n", __func__, (int)packet, length); |
||||||
|
|
||||||
|
length = (length < ETH_ZLEN) ? ETH_ZLEN : length; |
||||||
|
|
||||||
|
/* initiate a transmit sequence */ |
||||||
|
curr_des->txdes3 = (unsigned int)packet; /* TXBUF_BADR */ |
||||||
|
|
||||||
|
/* only one descriptor on TXBUF */ |
||||||
|
curr_des->txdes0 &= FTGMAC100_TXDES0_EDOTR; |
||||||
|
curr_des->txdes0 |= FTGMAC100_TXDES0_FTS | |
||||||
|
FTGMAC100_TXDES0_LTS | |
||||||
|
FTGMAC100_TXDES0_TXBUF_SIZE(length) | |
||||||
|
FTGMAC100_TXDES0_TXDMA_OWN ; |
||||||
|
|
||||||
|
/* start transmit */ |
||||||
|
writel(1, &ftgmac100->txpd); |
||||||
|
|
||||||
|
/* wait for transfer to succeed */ |
||||||
|
start = get_timer(0); |
||||||
|
while (curr_des->txdes0 & FTGMAC100_TXDES0_TXDMA_OWN) { |
||||||
|
if (get_timer(0) >= 5) { |
||||||
|
debug("%s(): timed out\n", __func__); |
||||||
|
return -1; |
||||||
|
} |
||||||
|
} |
||||||
|
|
||||||
|
debug("%s(): packet sent\n", __func__); |
||||||
|
|
||||||
|
priv->tx_index = (priv->tx_index + 1) % PKTBUFSTX; |
||||||
|
|
||||||
|
return 0; |
||||||
|
} |
||||||
|
|
||||||
|
int ftgmac100_initialize(bd_t *bd) |
||||||
|
{ |
||||||
|
struct eth_device *dev; |
||||||
|
struct ftgmac100_data *priv; |
||||||
|
|
||||||
|
dev = malloc(sizeof *dev); |
||||||
|
if (!dev) { |
||||||
|
printf("%s(): failed to allocate dev\n", __func__); |
||||||
|
goto out; |
||||||
|
} |
||||||
|
|
||||||
|
/* Transmit and receive descriptors should align to 16 bytes */ |
||||||
|
priv = memalign(16, sizeof(struct ftgmac100_data)); |
||||||
|
if (!priv) { |
||||||
|
printf("%s(): failed to allocate priv\n", __func__); |
||||||
|
goto free_dev; |
||||||
|
} |
||||||
|
|
||||||
|
memset(dev, 0, sizeof(*dev)); |
||||||
|
memset(priv, 0, sizeof(*priv)); |
||||||
|
|
||||||
|
sprintf(dev->name, "FTGMAC100"); |
||||||
|
dev->iobase = CONFIG_FTGMAC100_BASE; |
||||||
|
dev->init = ftgmac100_init; |
||||||
|
dev->halt = ftgmac100_halt; |
||||||
|
dev->send = ftgmac100_send; |
||||||
|
dev->recv = ftgmac100_recv; |
||||||
|
dev->priv = priv; |
||||||
|
|
||||||
|
eth_register(dev); |
||||||
|
|
||||||
|
return 1; |
||||||
|
|
||||||
|
free_dev: |
||||||
|
free(dev); |
||||||
|
out: |
||||||
|
return 0; |
||||||
|
} |
@ -0,0 +1,255 @@ |
|||||||
|
/*
|
||||||
|
* Faraday FTGMAC100 Ethernet |
||||||
|
* |
||||||
|
* (C) Copyright 2010 Faraday Technology |
||||||
|
* Po-Yu Chuang <ratbert@faraday-tech.com> |
||||||
|
* |
||||||
|
* (C) Copyright 2010 Andes Technology |
||||||
|
* Macpaul Lin <macpaul@andestech.com> |
||||||
|
* |
||||||
|
* This program is free software; you can redistribute it and/or modify |
||||||
|
* it under the terms of the GNU General Public License as published by |
||||||
|
* the Free Software Foundation; either version 2 of the License, or |
||||||
|
* (at your option) any later version. |
||||||
|
* |
||||||
|
* This program is distributed in the hope that it will be useful, |
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||||
|
* GNU General Public License for more details. |
||||||
|
* |
||||||
|
* You should have received a copy of the GNU General Public License |
||||||
|
* along with this program; if not, write to the Free Software |
||||||
|
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. |
||||||
|
*/ |
||||||
|
|
||||||
|
#ifndef __FTGMAC100_H |
||||||
|
#define __FTGMAC100_H |
||||||
|
|
||||||
|
/* The registers offset table of ftgmac100 */ |
||||||
|
struct ftgmac100 { |
||||||
|
unsigned int isr; /* 0x00 */ |
||||||
|
unsigned int ier; /* 0x04 */ |
||||||
|
unsigned int mac_madr; /* 0x08 */ |
||||||
|
unsigned int mac_ladr; /* 0x0c */ |
||||||
|
unsigned int maht0; /* 0x10 */ |
||||||
|
unsigned int maht1; /* 0x14 */ |
||||||
|
unsigned int txpd; /* 0x18 */ |
||||||
|
unsigned int rxpd; /* 0x1c */ |
||||||
|
unsigned int txr_badr; /* 0x20 */ |
||||||
|
unsigned int rxr_badr; /* 0x24 */ |
||||||
|
unsigned int hptxpd; /* 0x28 */ |
||||||
|
unsigned int hptxpd_badr; /* 0x2c */ |
||||||
|
unsigned int itc; /* 0x30 */ |
||||||
|
unsigned int aptc; /* 0x34 */ |
||||||
|
unsigned int dblac; /* 0x38 */ |
||||||
|
unsigned int dmafifos; /* 0x3c */ |
||||||
|
unsigned int revr; /* 0x40 */ |
||||||
|
unsigned int fear; /* 0x44 */ |
||||||
|
unsigned int tpafcr; /* 0x48 */ |
||||||
|
unsigned int rbsr; /* 0x4c */ |
||||||
|
unsigned int maccr; /* 0x50 */ |
||||||
|
unsigned int macsr; /* 0x54 */ |
||||||
|
unsigned int tm; /* 0x58 */ |
||||||
|
unsigned int resv1; /* 0x5c */ /* not defined in spec */ |
||||||
|
unsigned int phycr; /* 0x60 */ |
||||||
|
unsigned int phydata; /* 0x64 */ |
||||||
|
unsigned int fcr; /* 0x68 */ |
||||||
|
unsigned int bpr; /* 0x6c */ |
||||||
|
unsigned int wolcr; /* 0x70 */ |
||||||
|
unsigned int wolsr; /* 0x74 */ |
||||||
|
unsigned int wfcrc; /* 0x78 */ |
||||||
|
unsigned int resv2; /* 0x7c */ /* not defined in spec */ |
||||||
|
unsigned int wfbm1; /* 0x80 */ |
||||||
|
unsigned int wfbm2; /* 0x84 */ |
||||||
|
unsigned int wfbm3; /* 0x88 */ |
||||||
|
unsigned int wfbm4; /* 0x8c */ |
||||||
|
unsigned int nptxr_ptr; /* 0x90 */ |
||||||
|
unsigned int hptxr_ptr; /* 0x94 */ |
||||||
|
unsigned int rxr_ptr; /* 0x98 */ |
||||||
|
unsigned int resv3; /* 0x9c */ /* not defined in spec */ |
||||||
|
unsigned int tx; /* 0xa0 */ |
||||||
|
unsigned int tx_mcol_scol; /* 0xa4 */ |
||||||
|
unsigned int tx_ecol_fail; /* 0xa8 */ |
||||||
|
unsigned int tx_lcol_und; /* 0xac */ |
||||||
|
unsigned int rx; /* 0xb0 */ |
||||||
|
unsigned int rx_bc; /* 0xb4 */ |
||||||
|
unsigned int rx_mc; /* 0xb8 */ |
||||||
|
unsigned int rx_pf_aep; /* 0xbc */ |
||||||
|
unsigned int rx_runt; /* 0xc0 */ |
||||||
|
unsigned int rx_crcer_ftl; /* 0xc4 */ |
||||||
|
unsigned int rx_col_lost; /* 0xc8 */ |
||||||
|
}; |
||||||
|
|
||||||
|
/*
|
||||||
|
* Interrupt status register & interrupt enable register |
||||||
|
*/ |
||||||
|
#define FTGMAC100_INT_RPKT_BUF (1 << 0) |
||||||
|
#define FTGMAC100_INT_RPKT_FIFO (1 << 1) |
||||||
|
#define FTGMAC100_INT_NO_RXBUF (1 << 2) |
||||||
|
#define FTGMAC100_INT_RPKT_LOST (1 << 3) |
||||||
|
#define FTGMAC100_INT_XPKT_ETH (1 << 4) |
||||||
|
#define FTGMAC100_INT_XPKT_FIFO (1 << 5) |
||||||
|
#define FTGMAC100_INT_NO_NPTXBUF (1 << 6) |
||||||
|
#define FTGMAC100_INT_XPKT_LOST (1 << 7) |
||||||
|
#define FTGMAC100_INT_AHB_ERR (1 << 8) |
||||||
|
#define FTGMAC100_INT_PHYSTS_CHG (1 << 9) |
||||||
|
#define FTGMAC100_INT_NO_HPTXBUF (1 << 10) |
||||||
|
|
||||||
|
/*
|
||||||
|
* Interrupt timer control register |
||||||
|
*/ |
||||||
|
#define FTGMAC100_ITC_RXINT_CNT(x) (((x) & 0xf) << 0) |
||||||
|
#define FTGMAC100_ITC_RXINT_THR(x) (((x) & 0x7) << 4) |
||||||
|
#define FTGMAC100_ITC_RXINT_TIME_SEL (1 << 7) |
||||||
|
#define FTGMAC100_ITC_TXINT_CNT(x) (((x) & 0xf) << 8) |
||||||
|
#define FTGMAC100_ITC_TXINT_THR(x) (((x) & 0x7) << 12) |
||||||
|
#define FTGMAC100_ITC_TXINT_TIME_SEL (1 << 15) |
||||||
|
|
||||||
|
/*
|
||||||
|
* Automatic polling timer control register |
||||||
|
*/ |
||||||
|
#define FTGMAC100_APTC_RXPOLL_CNT(x) (((x) & 0xf) << 0) |
||||||
|
#define FTGMAC100_APTC_RXPOLL_TIME_SEL (1 << 4) |
||||||
|
#define FTGMAC100_APTC_TXPOLL_CNT(x) (((x) & 0xf) << 8) |
||||||
|
#define FTGMAC100_APTC_TXPOLL_TIME_SEL (1 << 12) |
||||||
|
|
||||||
|
/*
|
||||||
|
* DMA burst length and arbitration control register |
||||||
|
*/ |
||||||
|
#define FTGMAC100_DBLAC_RXFIFO_LTHR(x) (((x) & 0x7) << 0) |
||||||
|
#define FTGMAC100_DBLAC_RXFIFO_HTHR(x) (((x) & 0x7) << 3) |
||||||
|
#define FTGMAC100_DBLAC_RX_THR_EN (1 << 6) |
||||||
|
#define FTGMAC100_DBLAC_RXBURST_SIZE(x) (((x) & 0x3) << 8) |
||||||
|
#define FTGMAC100_DBLAC_TXBURST_SIZE(x) (((x) & 0x3) << 10) |
||||||
|
#define FTGMAC100_DBLAC_RXDES_SIZE(x) (((x) & 0xf) << 12) |
||||||
|
#define FTGMAC100_DBLAC_TXDES_SIZE(x) (((x) & 0xf) << 16) |
||||||
|
#define FTGMAC100_DBLAC_IFG_CNT(x) (((x) & 0x7) << 20) |
||||||
|
#define FTGMAC100_DBLAC_IFG_INC (1 << 23) |
||||||
|
|
||||||
|
/*
|
||||||
|
* DMA FIFO status register |
||||||
|
*/ |
||||||
|
#define FTGMAC100_DMAFIFOS_RXDMA1_SM(dmafifos) ((dmafifos) & 0xf) |
||||||
|
#define FTGMAC100_DMAFIFOS_RXDMA2_SM(dmafifos) (((dmafifos) >> 4) & 0xf) |
||||||
|
#define FTGMAC100_DMAFIFOS_RXDMA3_SM(dmafifos) (((dmafifos) >> 8) & 0x7) |
||||||
|
#define FTGMAC100_DMAFIFOS_TXDMA1_SM(dmafifos) (((dmafifos) >> 12) & 0xf) |
||||||
|
#define FTGMAC100_DMAFIFOS_TXDMA2_SM(dmafifos) (((dmafifos) >> 16) & 0x3) |
||||||
|
#define FTGMAC100_DMAFIFOS_TXDMA3_SM(dmafifos) (((dmafifos) >> 18) & 0xf) |
||||||
|
#define FTGMAC100_DMAFIFOS_RXFIFO_EMPTY (1 << 26) |
||||||
|
#define FTGMAC100_DMAFIFOS_TXFIFO_EMPTY (1 << 27) |
||||||
|
#define FTGMAC100_DMAFIFOS_RXDMA_GRANT (1 << 28) |
||||||
|
#define FTGMAC100_DMAFIFOS_TXDMA_GRANT (1 << 29) |
||||||
|
#define FTGMAC100_DMAFIFOS_RXDMA_REQ (1 << 30) |
||||||
|
#define FTGMAC100_DMAFIFOS_TXDMA_REQ (1 << 31) |
||||||
|
|
||||||
|
/*
|
||||||
|
* Receive buffer size register |
||||||
|
*/ |
||||||
|
#define FTGMAC100_RBSR_SIZE(x) ((x) & 0x3fff) |
||||||
|
|
||||||
|
/*
|
||||||
|
* MAC control register |
||||||
|
*/ |
||||||
|
#define FTGMAC100_MACCR_TXDMA_EN (1 << 0) |
||||||
|
#define FTGMAC100_MACCR_RXDMA_EN (1 << 1) |
||||||
|
#define FTGMAC100_MACCR_TXMAC_EN (1 << 2) |
||||||
|
#define FTGMAC100_MACCR_RXMAC_EN (1 << 3) |
||||||
|
#define FTGMAC100_MACCR_RM_VLAN (1 << 4) |
||||||
|
#define FTGMAC100_MACCR_HPTXR_EN (1 << 5) |
||||||
|
#define FTGMAC100_MACCR_LOOP_EN (1 << 6) |
||||||
|
#define FTGMAC100_MACCR_ENRX_IN_HALFTX (1 << 7) |
||||||
|
#define FTGMAC100_MACCR_FULLDUP (1 << 8) |
||||||
|
#define FTGMAC100_MACCR_GIGA_MODE (1 << 9) |
||||||
|
#define FTGMAC100_MACCR_CRC_APD (1 << 10) |
||||||
|
#define FTGMAC100_MACCR_RX_RUNT (1 << 12) |
||||||
|
#define FTGMAC100_MACCR_JUMBO_LF (1 << 13) |
||||||
|
#define FTGMAC100_MACCR_RX_ALL (1 << 14) |
||||||
|
#define FTGMAC100_MACCR_HT_MULTI_EN (1 << 15) |
||||||
|
#define FTGMAC100_MACCR_RX_MULTIPKT (1 << 16) |
||||||
|
#define FTGMAC100_MACCR_RX_BROADPKT (1 << 17) |
||||||
|
#define FTGMAC100_MACCR_DISCARD_CRCERR (1 << 18) |
||||||
|
#define FTGMAC100_MACCR_FAST_MODE (1 << 19) |
||||||
|
#define FTGMAC100_MACCR_SW_RST (1 << 31) |
||||||
|
|
||||||
|
/*
|
||||||
|
* PHY control register |
||||||
|
*/ |
||||||
|
#define FTGMAC100_PHYCR_MDC_CYCTHR_MASK 0x3f |
||||||
|
#define FTGMAC100_PHYCR_MDC_CYCTHR(x) ((x) & 0x3f) |
||||||
|
#define FTGMAC100_PHYCR_PHYAD(x) (((x) & 0x1f) << 16) |
||||||
|
#define FTGMAC100_PHYCR_REGAD(x) (((x) & 0x1f) << 21) |
||||||
|
#define FTGMAC100_PHYCR_MIIRD (1 << 26) |
||||||
|
#define FTGMAC100_PHYCR_MIIWR (1 << 27) |
||||||
|
|
||||||
|
/*
|
||||||
|
* PHY data register |
||||||
|
*/ |
||||||
|
#define FTGMAC100_PHYDATA_MIIWDATA(x) ((x) & 0xffff) |
||||||
|
#define FTGMAC100_PHYDATA_MIIRDATA(phydata) (((phydata) >> 16) & 0xffff) |
||||||
|
|
||||||
|
/*
|
||||||
|
* Transmit descriptor, aligned to 16 bytes |
||||||
|
*/ |
||||||
|
struct ftgmac100_txdes { |
||||||
|
unsigned int txdes0; |
||||||
|
unsigned int txdes1; |
||||||
|
unsigned int txdes2; /* not used by HW */ |
||||||
|
unsigned int txdes3; /* TXBUF_BADR */ |
||||||
|
} __attribute__ ((aligned(16))); |
||||||
|
|
||||||
|
#define FTGMAC100_TXDES0_TXBUF_SIZE(x) ((x) & 0x3fff) |
||||||
|
#define FTGMAC100_TXDES0_EDOTR (1 << 15) |
||||||
|
#define FTGMAC100_TXDES0_CRC_ERR (1 << 19) |
||||||
|
#define FTGMAC100_TXDES0_LTS (1 << 28) |
||||||
|
#define FTGMAC100_TXDES0_FTS (1 << 29) |
||||||
|
#define FTGMAC100_TXDES0_TXDMA_OWN (1 << 31) |
||||||
|
|
||||||
|
#define FTGMAC100_TXDES1_VLANTAG_CI(x) ((x) & 0xffff) |
||||||
|
#define FTGMAC100_TXDES1_INS_VLANTAG (1 << 16) |
||||||
|
#define FTGMAC100_TXDES1_TCP_CHKSUM (1 << 17) |
||||||
|
#define FTGMAC100_TXDES1_UDP_CHKSUM (1 << 18) |
||||||
|
#define FTGMAC100_TXDES1_IP_CHKSUM (1 << 19) |
||||||
|
#define FTGMAC100_TXDES1_LLC (1 << 22) |
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#define FTGMAC100_TXDES1_TX2FIC (1 << 30) |
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#define FTGMAC100_TXDES1_TXIC (1 << 31) |
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/*
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* Receive descriptor, aligned to 16 bytes |
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*/ |
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struct ftgmac100_rxdes { |
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unsigned int rxdes0; |
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unsigned int rxdes1; |
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unsigned int rxdes2; /* not used by HW */ |
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unsigned int rxdes3; /* RXBUF_BADR */ |
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} __attribute__ ((aligned(16))); |
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#define FTGMAC100_RXDES0_VDBC(x) ((x) & 0x3fff) |
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#define FTGMAC100_RXDES0_EDORR (1 << 15) |
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#define FTGMAC100_RXDES0_MULTICAST (1 << 16) |
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#define FTGMAC100_RXDES0_BROADCAST (1 << 17) |
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#define FTGMAC100_RXDES0_RX_ERR (1 << 18) |
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#define FTGMAC100_RXDES0_CRC_ERR (1 << 19) |
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#define FTGMAC100_RXDES0_FTL (1 << 20) |
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#define FTGMAC100_RXDES0_RUNT (1 << 21) |
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#define FTGMAC100_RXDES0_RX_ODD_NB (1 << 22) |
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#define FTGMAC100_RXDES0_FIFO_FULL (1 << 23) |
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#define FTGMAC100_RXDES0_PAUSE_OPCODE (1 << 24) |
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#define FTGMAC100_RXDES0_PAUSE_FRAME (1 << 25) |
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#define FTGMAC100_RXDES0_LRS (1 << 28) |
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#define FTGMAC100_RXDES0_FRS (1 << 29) |
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#define FTGMAC100_RXDES0_RXPKT_RDY (1 << 31) |
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#define FTGMAC100_RXDES1_VLANTAG_CI 0xffff |
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#define FTGMAC100_RXDES1_PROT_MASK (0x3 << 20) |
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#define FTGMAC100_RXDES1_PROT_NONIP (0x0 << 20) |
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#define FTGMAC100_RXDES1_PROT_IP (0x1 << 20) |
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#define FTGMAC100_RXDES1_PROT_TCPIP (0x2 << 20) |
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#define FTGMAC100_RXDES1_PROT_UDPIP (0x3 << 20) |
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#define FTGMAC100_RXDES1_LLC (1 << 22) |
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#define FTGMAC100_RXDES1_DF (1 << 23) |
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#define FTGMAC100_RXDES1_VLANTAG_AVAIL (1 << 24) |
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#define FTGMAC100_RXDES1_TCP_CHKSUM_ERR (1 << 25) |
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#define FTGMAC100_RXDES1_UDP_CHKSUM_ERR (1 << 26) |
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#define FTGMAC100_RXDES1_IP_CHKSUM_ERR (1 << 27) |
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#endif /* __FTGMAC100_H */ |
Loading…
Reference in new issue