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@ -7,6 +7,9 @@ |
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* SPDX-License-Identifier: (GPL-2.0+ OR MIT) |
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*/ |
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#include <dt-bindings/gpio/gpio.h> |
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#include <dt-bindings/gpio/uniphier-gpio.h> |
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/memreserve/ 0x80000000 0x02000000; |
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/ { |
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@ -49,7 +52,7 @@ |
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}; |
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}; |
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cluster0_opp: opp_table { |
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cluster0_opp: opp-table { |
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compatible = "operating-points-v2"; |
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opp-shared; |
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@ -96,6 +99,11 @@ |
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}; |
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}; |
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emmc_pwrseq: emmc-pwrseq { |
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compatible = "mmc-pwrseq-emmc"; |
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reset-gpios = <&gpio UNIPHIER_GPIO_PORT(3, 2) GPIO_ACTIVE_LOW>; |
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}; |
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timer { |
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compatible = "arm,armv8-timer"; |
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interrupts = <1 13 4>, |
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@ -119,6 +127,7 @@ |
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pinctrl-0 = <&pinctrl_uart0>; |
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clocks = <&peri_clk 0>; |
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clock-frequency = <58820000>; |
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resets = <&peri_rst 0>; |
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}; |
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serial1: serial@54006900 { |
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@ -130,6 +139,7 @@ |
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pinctrl-0 = <&pinctrl_uart1>; |
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clocks = <&peri_clk 1>; |
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clock-frequency = <58820000>; |
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resets = <&peri_rst 1>; |
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}; |
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serial2: serial@54006a00 { |
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@ -141,6 +151,7 @@ |
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pinctrl-0 = <&pinctrl_uart2>; |
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clocks = <&peri_clk 2>; |
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clock-frequency = <58820000>; |
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resets = <&peri_rst 2>; |
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}; |
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serial3: serial@54006b00 { |
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@ -152,6 +163,7 @@ |
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pinctrl-0 = <&pinctrl_uart3>; |
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clocks = <&peri_clk 3>; |
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clock-frequency = <58820000>; |
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resets = <&peri_rst 3>; |
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}; |
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gpio: gpio@55000000 { |
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@ -200,6 +212,7 @@ |
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pinctrl-names = "default"; |
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pinctrl-0 = <&pinctrl_i2c0>; |
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clocks = <&peri_clk 4>; |
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resets = <&peri_rst 4>; |
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clock-frequency = <100000>; |
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}; |
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@ -213,6 +226,7 @@ |
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pinctrl-names = "default"; |
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pinctrl-0 = <&pinctrl_i2c1>; |
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clocks = <&peri_clk 5>; |
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resets = <&peri_rst 5>; |
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clock-frequency = <100000>; |
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}; |
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@ -223,6 +237,7 @@ |
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#size-cells = <0>; |
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interrupts = <0 43 4>; |
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clocks = <&peri_clk 6>; |
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resets = <&peri_rst 6>; |
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clock-frequency = <400000>; |
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}; |
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@ -236,6 +251,7 @@ |
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pinctrl-names = "default"; |
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pinctrl-0 = <&pinctrl_i2c3>; |
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clocks = <&peri_clk 7>; |
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resets = <&peri_rst 7>; |
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clock-frequency = <100000>; |
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}; |
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@ -249,6 +265,7 @@ |
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pinctrl-names = "default"; |
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pinctrl-0 = <&pinctrl_i2c4>; |
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clocks = <&peri_clk 8>; |
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resets = <&peri_rst 8>; |
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clock-frequency = <100000>; |
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}; |
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@ -259,6 +276,7 @@ |
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#size-cells = <0>; |
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interrupts = <0 25 4>; |
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clocks = <&peri_clk 9>; |
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resets = <&peri_rst 9>; |
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clock-frequency = <400000>; |
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}; |
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@ -311,9 +329,11 @@ |
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pinctrl-names = "default"; |
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pinctrl-0 = <&pinctrl_emmc_1v8>; |
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clocks = <&sys_clk 4>; |
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resets = <&sys_rst 4>; |
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bus-width = <8>; |
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mmc-ddr-1_8v; |
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mmc-hs200-1_8v; |
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mmc-pwrseq = <&emmc_pwrseq>; |
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cdns,phy-input-delay-legacy = <4>; |
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cdns,phy-input-delay-mmc-highspeed = <2>; |
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cdns,phy-input-delay-mmc-ddr = <3>; |
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@ -328,7 +348,8 @@ |
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interrupts = <0 243 4>; |
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pinctrl-names = "default"; |
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pinctrl-0 = <&pinctrl_usb0>; |
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clocks = <&mio_clk 7>, <&mio_clk 8>, <&mio_clk 12>; |
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clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 8>, |
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<&mio_clk 12>; |
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resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>, |
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<&mio_rst 12>; |
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}; |
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@ -340,7 +361,8 @@ |
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interrupts = <0 244 4>; |
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pinctrl-names = "default"; |
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pinctrl-0 = <&pinctrl_usb1>; |
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clocks = <&mio_clk 7>, <&mio_clk 9>, <&mio_clk 13>; |
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clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 9>, |
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<&mio_clk 13>; |
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resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>, |
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<&mio_rst 13>; |
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}; |
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@ -352,7 +374,8 @@ |
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interrupts = <0 245 4>; |
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pinctrl-names = "default"; |
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pinctrl-0 = <&pinctrl_usb2>; |
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clocks = <&mio_clk 7>, <&mio_clk 10>, <&mio_clk 14>; |
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clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 10>, |
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<&mio_clk 14>; |
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resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>, |
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<&mio_rst 14>; |
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}; |
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@ -384,6 +407,24 @@ |
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}; |
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}; |
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soc-glue@5f900000 { |
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compatible = "socionext,uniphier-ld11-soc-glue-debug", |
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"simple-mfd"; |
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#address-cells = <1>; |
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#size-cells = <1>; |
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ranges = <0 0x5f900000 0x2000>; |
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efuse@100 { |
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compatible = "socionext,uniphier-efuse"; |
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reg = <0x100 0x28>; |
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}; |
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efuse@200 { |
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compatible = "socionext,uniphier-efuse"; |
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reg = <0x200 0x68>; |
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}; |
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}; |
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aidet: aidet@5fc20000 { |
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compatible = "socionext,uniphier-ld11-aidet"; |
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reg = <0x5fc20000 0x200>; |
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@ -429,6 +470,7 @@ |
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pinctrl-names = "default"; |
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pinctrl-0 = <&pinctrl_nand>; |
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clocks = <&sys_clk 2>; |
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resets = <&sys_rst 2>; |
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}; |
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}; |
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}; |
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