IHS I2C master support was merely a hack in the osd driver. Now it is a proper u-boot I2C framework driver, supporting the v2.00 master features. Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc>master
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/*
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* (C) Copyright 2013 |
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* Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <i2c.h> |
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#include <gdsys_fpga.h> |
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DECLARE_GLOBAL_DATA_PTR; |
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enum { |
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I2CINT_ERROR_EV = 1 << 13, |
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I2CINT_TRANSMIT_EV = 1 << 14, |
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I2CINT_RECEIVE_EV = 1 << 15, |
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}; |
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enum { |
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I2CMB_WRITE = 1 << 10, |
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I2CMB_2BYTE = 1 << 11, |
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I2CMB_HOLD_BUS = 1 << 13, |
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I2CMB_NATIVE = 2 << 14, |
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}; |
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static int wait_for_int(bool read) |
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{ |
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u16 val; |
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unsigned int ctr = 0; |
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FPGA_GET_REG(I2C_ADAP_HWNR, i2c.interrupt_status, &val); |
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while (!(val & (I2CINT_ERROR_EV |
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| (read ? I2CINT_RECEIVE_EV : I2CINT_TRANSMIT_EV)))) { |
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udelay(10); |
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if (ctr++ > 5000) { |
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printf("I2C timeout\n"); |
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return 1; |
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} |
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FPGA_GET_REG(I2C_ADAP_HWNR, i2c.interrupt_status, &val); |
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} |
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return (val & I2CINT_ERROR_EV) ? 1 : 0; |
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} |
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static int ihs_i2c_transfer(uchar chip, uchar *buffer, int len, bool read, |
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bool is_last) |
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{ |
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u16 val; |
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FPGA_SET_REG(I2C_ADAP_HWNR, i2c.interrupt_status, I2CINT_ERROR_EV |
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| I2CINT_RECEIVE_EV | I2CINT_TRANSMIT_EV); |
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FPGA_GET_REG(I2C_ADAP_HWNR, i2c.interrupt_status, &val); |
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if (!read && len) { |
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val = buffer[0]; |
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if (len > 1) |
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val |= buffer[1] << 8; |
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FPGA_SET_REG(I2C_ADAP_HWNR, i2c.write_mailbox_ext, val); |
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} |
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FPGA_SET_REG(I2C_ADAP_HWNR, i2c.write_mailbox, |
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I2CMB_NATIVE |
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| (read ? 0 : I2CMB_WRITE) |
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| (chip << 1) |
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| ((len > 1) ? I2CMB_2BYTE : 0) |
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| (is_last ? 0 : I2CMB_HOLD_BUS)); |
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if (wait_for_int(read)) |
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return 1; |
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if (read) { |
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FPGA_GET_REG(I2C_ADAP_HWNR, i2c.read_mailbox_ext, &val); |
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buffer[0] = val & 0xff; |
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if (len > 1) |
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buffer[1] = val >> 8; |
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} |
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return 0; |
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} |
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static int ihs_i2c_address(uchar chip, uint addr, int alen, bool hold_bus) |
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{ |
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int shift = (alen-1) * 8; |
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while (alen) { |
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int transfer = MIN(alen, 2); |
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uchar buf[2]; |
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bool is_last = alen <= transfer; |
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buf[0] = addr >> shift; |
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if (alen > 1) |
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buf[1] = addr >> (shift - 8); |
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if (ihs_i2c_transfer(chip, buf, transfer, false, |
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hold_bus ? false : is_last)) |
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return 1; |
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shift -= 16; |
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alen -= transfer; |
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} |
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return 0; |
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} |
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static int ihs_i2c_access(struct i2c_adapter *adap, uchar chip, uint addr, |
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int alen, uchar *buffer, int len, bool read) |
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{ |
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if (len <= 0) |
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return 1; |
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if (ihs_i2c_address(chip, addr, alen, !read)) |
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return 1; |
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while (len) { |
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int transfer = MIN(len, 2); |
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if (ihs_i2c_transfer(chip, buffer, transfer, read, |
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len <= transfer)) |
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return 1; |
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buffer += transfer; |
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addr += transfer; |
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len -= transfer; |
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} |
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return 0; |
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} |
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static void ihs_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr) |
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{ |
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#ifdef CONFIG_SYS_I2C_INIT_BOARD |
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/*
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* Call board specific i2c bus reset routine before accessing the |
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* environment, which might be in a chip on that bus. For details |
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* about this problem see doc/I2C_Edge_Conditions. |
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*/ |
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i2c_init_board(); |
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#endif |
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} |
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static int ihs_i2c_probe(struct i2c_adapter *adap, uchar chip) |
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{ |
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uchar buffer[2]; |
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if (ihs_i2c_transfer(chip, buffer, 0, true, true)) |
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return 1; |
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return 0; |
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} |
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static int ihs_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr, |
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int alen, uchar *buffer, int len) |
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{ |
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return ihs_i2c_access(adap, chip, addr, alen, buffer, len, true); |
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} |
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static int ihs_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr, |
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int alen, uchar *buffer, int len) |
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{ |
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return ihs_i2c_access(adap, chip, addr, alen, buffer, len, false); |
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} |
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static unsigned int ihs_i2c_set_bus_speed(struct i2c_adapter *adap, |
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unsigned int speed) |
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{ |
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if (speed != adap->speed) |
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return 1; |
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return speed; |
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} |
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/*
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* Register IHS i2c adapters |
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*/ |
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#ifdef CONFIG_SYS_I2C_IHS_CH0 |
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U_BOOT_I2C_ADAP_COMPLETE(ihs0, ihs_i2c_init, ihs_i2c_probe, |
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ihs_i2c_read, ihs_i2c_write, |
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ihs_i2c_set_bus_speed, |
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CONFIG_SYS_I2C_IHS_SPEED_0, |
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CONFIG_SYS_I2C_IHS_SLAVE_0, 0) |
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#endif |
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#ifdef CONFIG_SYS_I2C_IHS_CH1 |
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U_BOOT_I2C_ADAP_COMPLETE(ihs1, ihs_i2c_init, ihs_i2c_probe, |
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ihs_i2c_read, ihs_i2c_write, |
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ihs_i2c_set_bus_speed, |
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CONFIG_SYS_I2C_IHS_SPEED_1, |
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CONFIG_SYS_I2C_IHS_SLAVE_1, 1) |
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#endif |
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#ifdef CONFIG_SYS_I2C_IHS_CH2 |
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U_BOOT_I2C_ADAP_COMPLETE(ihs2, ihs_i2c_init, ihs_i2c_probe, |
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ihs_i2c_read, ihs_i2c_write, |
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ihs_i2c_set_bus_speed, |
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CONFIG_SYS_I2C_IHS_SPEED_2, |
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CONFIG_SYS_I2C_IHS_SLAVE_2, 2) |
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#endif |
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#ifdef CONFIG_SYS_I2C_IHS_CH3 |
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U_BOOT_I2C_ADAP_COMPLETE(ihs3, ihs_i2c_init, ihs_i2c_probe, |
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ihs_i2c_read, ihs_i2c_write, |
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ihs_i2c_set_bus_speed, |
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CONFIG_SYS_I2C_IHS_SPEED_3, |
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CONFIG_SYS_I2C_IHS_SLAVE_3, 3) |
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#endif |
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