Add clock driver support for Rockchip rv1108 soc Signed-off-by: Andy Yan <andy.yan@rock-chips.com> Reviewed-by: Simon Glass <sjg@chromium.org>master
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/*
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* (C) Copyright 2016 Rockchip Electronics Co., Ltd |
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* Author: Andy Yan <andy.yan@rock-chips.com> |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#ifndef _ASM_ARCH_CRU_RV1108_H |
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#define _ASM_ARCH_CRU_RV1108_H |
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#include <common.h> |
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#define OSC_HZ (24 * 1000 * 1000) |
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#define APLL_HZ (600 * 1000000) |
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#define GPLL_HZ (594 * 1000000) |
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struct rv1108_clk_priv { |
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struct rv1108_cru *cru; |
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ulong rate; |
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}; |
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struct rv1108_cru { |
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struct rv1108_pll { |
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unsigned int con0; |
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unsigned int con1; |
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unsigned int con2; |
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unsigned int con3; |
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unsigned int con4; |
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unsigned int con5; |
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unsigned int reserved[2]; |
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} pll[3]; |
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unsigned int clksel_con[46]; |
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unsigned int reserved1[2]; |
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unsigned int clkgate_con[20]; |
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unsigned int reserved2[4]; |
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unsigned int softrst_con[13]; |
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unsigned int reserved3[3]; |
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unsigned int glb_srst_fst_val; |
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unsigned int glb_srst_snd_val; |
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unsigned int glb_cnt_th; |
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unsigned int misc_con; |
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unsigned int glb_rst_con; |
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unsigned int glb_rst_st; |
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unsigned int sdmmc_con[2]; |
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unsigned int sdio_con[2]; |
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unsigned int emmc_con[2]; |
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}; |
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check_member(rv1108_cru, emmc_con[1], 0x01ec); |
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struct pll_div { |
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u32 refdiv; |
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u32 fbdiv; |
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u32 postdiv1; |
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u32 postdiv2; |
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u32 frac; |
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}; |
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enum { |
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/* PLL CON0 */ |
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FBDIV_MASK = 0xfff, |
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FBDIV_SHIFT = 0, |
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/* PLL CON1 */ |
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POSTDIV2_SHIFT = 12, |
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POSTDIV2_MASK = 7 << POSTDIV2_SHIFT, |
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POSTDIV1_SHIFT = 8, |
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POSTDIV1_MASK = 7 << POSTDIV1_SHIFT, |
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REFDIV_MASK = 0x3f, |
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REFDIV_SHIFT = 0, |
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/* PLL CON2 */ |
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LOCK_STA_SHIFT = 31, |
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LOCK_STA_MASK = 1 << LOCK_STA_SHIFT, |
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FRACDIV_MASK = 0xffffff, |
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FRACDIV_SHIFT = 0, |
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/* PLL CON3 */ |
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WORK_MODE_SHIFT = 8, |
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WORK_MODE_MASK = 1 << WORK_MODE_SHIFT, |
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WORK_MODE_SLOW = 0, |
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WORK_MODE_NORMAL = 1, |
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DSMPD_SHIFT = 3, |
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DSMPD_MASK = 1 << DSMPD_SHIFT, |
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/* CLKSEL0_CON */ |
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CORE_PLL_SEL_SHIFT = 8, |
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CORE_PLL_SEL_MASK = 3 << CORE_PLL_SEL_SHIFT, |
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CORE_PLL_SEL_APLL = 0, |
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CORE_PLL_SEL_GPLL = 1, |
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CORE_PLL_SEL_DPLL = 2, |
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CORE_CLK_DIV_SHIFT = 0, |
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CORE_CLK_DIV_MASK = 0x1f << CORE_CLK_DIV_SHIFT, |
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/* CLKSEL24_CON */ |
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MAC_PLL_SEL_SHIFT = 12, |
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MAC_PLL_SEL_MASK = 1 << MAC_PLL_SEL_SHIFT, |
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MAC_PLL_SEL_APLL = 0, |
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MAC_PLL_SEL_GPLL = 1, |
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RMII_EXTCLK_SEL_SHIFT = 8, |
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RMII_EXTCLK_SEL_MASK = 1 << RMII_EXTCLK_SEL_SHIFT, |
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MAC_CLK_DIV_MASK = 0x1f, |
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MAC_CLK_DIV_SHIFT = 0, |
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/* CLKSEL27_CON */ |
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SFC_PLL_SEL_SHIFT = 7, |
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SFC_PLL_SEL_MASK = 1 << SFC_PLL_SEL_SHIFT, |
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SFC_PLL_SEL_DPLL = 0, |
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SFC_PLL_SEL_GPLL = 1, |
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SFC_CLK_DIV_SHIFT = 0, |
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SFC_CLK_DIV_MASK = 0x3f << SFC_CLK_DIV_SHIFT, |
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}; |
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#endif |
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/*
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* (C) Copyright 2016 Rockchip Electronics Co., Ltd |
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* Author: Andy Yan <andy.yan@rock-chips.com> |
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* SPDX-License-Identifier: GPL-2.0 |
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*/ |
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#include <common.h> |
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#include <clk-uclass.h> |
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#include <dm.h> |
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#include <errno.h> |
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#include <syscon.h> |
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#include <asm/io.h> |
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#include <asm/arch/clock.h> |
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#include <asm/arch/cru_rv1108.h> |
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#include <asm/arch/hardware.h> |
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#include <dm/lists.h> |
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#include <dt-bindings/clock/rv1108-cru.h> |
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DECLARE_GLOBAL_DATA_PTR; |
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enum { |
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VCO_MAX_HZ = 2400U * 1000000, |
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VCO_MIN_HZ = 600 * 1000000, |
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OUTPUT_MAX_HZ = 2400U * 1000000, |
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OUTPUT_MIN_HZ = 24 * 1000000, |
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}; |
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#define RATE_TO_DIV(input_rate, output_rate) \ |
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((input_rate) / (output_rate) - 1); |
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#define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) |
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#define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\ |
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.refdiv = _refdiv,\
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.fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ),\
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.postdiv1 = _postdiv1, .postdiv2 = _postdiv2};\
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_Static_assert(((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ) *\
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OSC_HZ / (_refdiv * _postdiv1 * _postdiv2) == hz,\
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#hz "Hz cannot be hit with PLL "\ |
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"divisors on line " __stringify(__LINE__)); |
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/* use interge mode*/ |
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static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 3, 1); |
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static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1); |
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static inline int rv1108_pll_id(enum rk_clk_id clk_id) |
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{ |
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int id = 0; |
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switch (clk_id) { |
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case CLK_ARM: |
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case CLK_DDR: |
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id = clk_id - 1; |
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break; |
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case CLK_GENERAL: |
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id = 2; |
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break; |
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default: |
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printf("invalid pll id:%d\n", clk_id); |
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id = -1; |
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break; |
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} |
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return id; |
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} |
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static uint32_t rkclk_pll_get_rate(struct rv1108_cru *cru, |
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enum rk_clk_id clk_id) |
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{ |
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uint32_t refdiv, fbdiv, postdiv1, postdiv2; |
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uint32_t con0, con1, con3; |
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int pll_id = rv1108_pll_id(clk_id); |
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struct rv1108_pll *pll = &cru->pll[pll_id]; |
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uint32_t freq; |
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con3 = readl(&pll->con3); |
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if (con3 & WORK_MODE_MASK) { |
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con0 = readl(&pll->con0); |
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con1 = readl(&pll->con1); |
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fbdiv = (con0 >> FBDIV_SHIFT) & FBDIV_MASK; |
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postdiv1 = (con1 & POSTDIV1_MASK) >> POSTDIV1_SHIFT; |
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postdiv2 = (con1 & POSTDIV2_MASK) >> POSTDIV2_SHIFT; |
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refdiv = (con1 & REFDIV_MASK) >> REFDIV_SHIFT; |
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freq = (24 * fbdiv / (refdiv * postdiv1 * postdiv2)) * 1000000; |
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} else { |
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freq = OSC_HZ; |
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} |
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return freq; |
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} |
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static int rv1108_mac_set_clk(struct rv1108_cru *cru, ulong rate) |
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{ |
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uint32_t con = readl(&cru->clksel_con[24]); |
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ulong pll_rate; |
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uint8_t div; |
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if ((con >> MAC_PLL_SEL_SHIFT) & MAC_PLL_SEL_GPLL) |
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pll_rate = rkclk_pll_get_rate(cru, CLK_GENERAL); |
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else |
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pll_rate = rkclk_pll_get_rate(cru, CLK_ARM); |
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/*default set 50MHZ for gmac*/ |
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if (!rate) |
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rate = 50000000; |
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div = DIV_ROUND_UP(pll_rate, rate) - 1; |
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if (div <= 0x1f) |
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rk_clrsetreg(&cru->clksel_con[24], MAC_CLK_DIV_MASK, |
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div << MAC_CLK_DIV_SHIFT); |
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else |
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debug("Unsupported div for gmac:%d\n", div); |
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return DIV_TO_RATE(pll_rate, div); |
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} |
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static int rv1108_sfc_set_clk(struct rv1108_cru *cru, uint rate) |
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{ |
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u32 con = readl(&cru->clksel_con[27]); |
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u32 pll_rate; |
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u32 div; |
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if ((con >> SFC_PLL_SEL_SHIFT) && SFC_PLL_SEL_GPLL) |
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pll_rate = rkclk_pll_get_rate(cru, CLK_GENERAL); |
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else |
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pll_rate = rkclk_pll_get_rate(cru, CLK_DDR); |
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div = DIV_ROUND_UP(pll_rate, rate) - 1; |
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if (div <= 0x3f) |
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rk_clrsetreg(&cru->clksel_con[27], SFC_CLK_DIV_MASK, |
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div << SFC_CLK_DIV_SHIFT); |
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else |
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debug("Unsupported sfc clk rate:%d\n", rate); |
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return DIV_TO_RATE(pll_rate, div); |
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} |
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static ulong rv1108_clk_get_rate(struct clk *clk) |
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{ |
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struct rv1108_clk_priv *priv = dev_get_priv(clk->dev); |
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switch (clk->id) { |
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case 0 ... 63: |
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return rkclk_pll_get_rate(priv->cru, clk->id); |
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default: |
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return -ENOENT; |
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} |
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} |
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static ulong rv1108_clk_set_rate(struct clk *clk, ulong rate) |
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{ |
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struct rv1108_clk_priv *priv = dev_get_priv(clk->dev); |
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ulong new_rate; |
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switch (clk->id) { |
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case SCLK_MAC: |
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new_rate = rv1108_mac_set_clk(priv->cru, rate); |
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break; |
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case SCLK_SFC: |
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new_rate = rv1108_sfc_set_clk(priv->cru, rate); |
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break; |
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default: |
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return -ENOENT; |
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} |
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return new_rate; |
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} |
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static const struct clk_ops rv1108_clk_ops = { |
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.get_rate = rv1108_clk_get_rate, |
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.set_rate = rv1108_clk_set_rate, |
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}; |
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static void rkclk_init(struct rv1108_cru *cru) |
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{ |
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unsigned int apll = rkclk_pll_get_rate(cru, CLK_ARM); |
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unsigned int dpll = rkclk_pll_get_rate(cru, CLK_DDR); |
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unsigned int gpll = rkclk_pll_get_rate(cru, CLK_GENERAL); |
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rk_clrsetreg(&cru->clksel_con[0], CORE_CLK_DIV_MASK, |
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0 << MAC_CLK_DIV_SHIFT); |
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printf("APLL: %d DPLL:%d GPLL:%d\n", apll, dpll, gpll); |
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} |
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static int rv1108_clk_probe(struct udevice *dev) |
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{ |
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struct rv1108_clk_priv *priv = dev_get_priv(dev); |
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priv->cru = (struct rv1108_cru *)devfdt_get_addr(dev); |
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rkclk_init(priv->cru); |
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return 0; |
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} |
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static int rv1108_clk_bind(struct udevice *dev) |
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{ |
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int ret; |
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/* The reset driver does not have a device node, so bind it here */ |
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ret = device_bind_driver(gd->dm_root, "rv1108_sysreset", "reset", &dev); |
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if (ret) |
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error("No Rv1108 reset driver: ret=%d\n", ret); |
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return 0; |
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} |
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static const struct udevice_id rv1108_clk_ids[] = { |
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{ .compatible = "rockchip,rv1108-cru" }, |
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{ } |
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}; |
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U_BOOT_DRIVER(clk_rv1108) = { |
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.name = "clk_rv1108", |
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.id = UCLASS_CLK, |
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.of_match = rv1108_clk_ids, |
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.priv_auto_alloc_size = sizeof(struct rv1108_clk_priv), |
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.ops = &rv1108_clk_ops, |
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.bind = rv1108_clk_bind, |
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.probe = rv1108_clk_probe, |
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}; |
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/*
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* Copyright (c) 2017 Rockchip Electronics Co. Ltd. |
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* Author: Shawn Lin <shawn.lin@rock-chips.com> |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RV1108_H |
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#define _DT_BINDINGS_CLK_ROCKCHIP_RV1108_H |
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/* pll id */ |
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#define PLL_APLL 0 |
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#define PLL_DPLL 1 |
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#define PLL_GPLL 2 |
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#define ARMCLK 3 |
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/* sclk gates (special clocks) */ |
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#define SCLK_MAC 64 |
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#define SCLK_SPI0 65 |
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#define SCLK_NANDC 67 |
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#define SCLK_SDMMC 68 |
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#define SCLK_SDIO 69 |
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#define SCLK_EMMC 71 |
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#define SCLK_UART0 72 |
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#define SCLK_UART1 73 |
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#define SCLK_UART2 74 |
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#define SCLK_I2S0 75 |
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#define SCLK_I2S1 76 |
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#define SCLK_I2S2 77 |
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#define SCLK_TIMER0 78 |
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#define SCLK_TIMER1 79 |
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#define SCLK_SFC 80 |
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#define SCLK_SDMMC_DRV 81 |
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#define SCLK_SDIO_DRV 82 |
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#define SCLK_EMMC_DRV 83 |
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#define SCLK_SDMMC_SAMPLE 84 |
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#define SCLK_SDIO_SAMPLE 85 |
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#define SCLK_EMMC_SAMPLE 86 |
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#define SCLK_MAC_RX 87 |
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#define SCLK_MAC_TX 88 |
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#define SCLK_MACREF 89 |
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#define SCLK_MACREF_OUT 90 |
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/* aclk gates */ |
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#define ACLK_DMAC 192 |
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#define ACLK_PRE 193 |
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#define ACLK_CORE 194 |
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#define ACLK_ENMCORE 195 |
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#define ACLK_GMAC 196 |
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/* pclk gates */ |
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#define PCLK_GPIO1 256 |
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#define PCLK_GPIO2 257 |
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#define PCLK_GPIO3 258 |
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#define PCLK_GRF 259 |
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#define PCLK_I2C1 260 |
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#define PCLK_I2C2 261 |
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#define PCLK_I2C3 262 |
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#define PCLK_SPI 263 |
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#define PCLK_SFC 264 |
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#define PCLK_UART0 265 |
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#define PCLK_UART1 266 |
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#define PCLK_UART2 267 |
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#define PCLK_TSADC 268 |
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#define PCLK_PWM 269 |
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#define PCLK_TIMER 270 |
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#define PCLK_PERI 271 |
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#define PCLK_GMAC 272 |
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/* hclk gates */ |
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#define HCLK_I2S0_8CH 320 |
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#define HCLK_I2S1_8CH 321 |
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#define HCLK_I2S2_2CH 322 |
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#define HCLK_NANDC 323 |
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#define HCLK_SDMMC 324 |
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#define HCLK_SDIO 325 |
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#define HCLK_EMMC 326 |
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#define HCLK_PERI 327 |
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#define HCLK_SFC 328 |
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#define CLK_NR_CLKS (HCLK_SFC + 1) |
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/* reset id */ |
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#define SRST_CORE_PO_AD 0 |
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#define SRST_CORE_AD 1 |
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#define SRST_L2_AD 2 |
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#define SRST_CPU_NIU_AD 3 |
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#define SRST_CORE_PO 4 |
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#define SRST_CORE 5 |
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#define SRST_L2 6 |
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#define SRST_CORE_DBG 8 |
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#define PRST_DBG 9 |
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#define RST_DAP 10 |
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#define PRST_DBG_NIU 11 |
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#define ARST_STRC_SYS_AD 15 |
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#define SRST_DDRPHY_CLKDIV 16 |
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#define SRST_DDRPHY 17 |
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#define PRST_DDRPHY 18 |
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#define PRST_HDMIPHY 19 |
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#define PRST_VDACPHY 20 |
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#define PRST_VADCPHY 21 |
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#define PRST_MIPI_CSI_PHY 22 |
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#define PRST_MIPI_DSI_PHY 23 |
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#define PRST_ACODEC 24 |
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#define ARST_BUS_NIU 25 |
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#define PRST_TOP_NIU 26 |
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#define ARST_INTMEM 27 |
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#define HRST_ROM 28 |
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#define ARST_DMAC 29 |
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#define SRST_MSCH_NIU 30 |
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#define PRST_MSCH_NIU 31 |
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#define PRST_DDRUPCTL 32 |
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#define NRST_DDRUPCTL 33 |
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#define PRST_DDRMON 34 |
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#define HRST_I2S0_8CH 35 |
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#define MRST_I2S0_8CH 36 |
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#define HRST_I2S1_2CH 37 |
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#define MRST_IS21_2CH 38 |
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#define HRST_I2S2_2CH 39 |
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#define MRST_I2S2_2CH 40 |
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#define HRST_CRYPTO 41 |
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#define SRST_CRYPTO 42 |
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#define PRST_SPI 43 |
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#define SRST_SPI 44 |
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#define PRST_UART0 45 |
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#define PRST_UART1 46 |
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#define PRST_UART2 47 |
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#define SRST_UART0 48 |
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#define SRST_UART1 49 |
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#define SRST_UART2 50 |
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#define PRST_I2C1 51 |
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#define PRST_I2C2 52 |
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#define PRST_I2C3 53 |
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#define SRST_I2C1 54 |
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#define SRST_I2C2 55 |
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#define SRST_I2C3 56 |
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#define PRST_PWM1 58 |
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#define SRST_PWM1 60 |
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#define PRST_WDT 61 |
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#define PRST_GPIO1 62 |
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#define PRST_GPIO2 63 |
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#define PRST_GPIO3 64 |
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#define PRST_GRF 65 |
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#define PRST_EFUSE 66 |
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#define PRST_EFUSE512 67 |
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#define PRST_TIMER0 68 |
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#define SRST_TIMER0 69 |
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#define SRST_TIMER1 70 |
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#define PRST_TSADC 71 |
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#define SRST_TSADC 72 |
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#define PRST_SARADC 73 |
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#define SRST_SARADC 74 |
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#define HRST_SYSBUS 75 |
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#define PRST_USBGRF 76 |
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#define ARST_PERIPH_NIU 80 |
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#define HRST_PERIPH_NIU 81 |
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#define PRST_PERIPH_NIU 82 |
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#define HRST_PERIPH 83 |
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#define HRST_SDMMC 84 |
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#define HRST_SDIO 85 |
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#define HRST_EMMC 86 |
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#define HRST_NANDC 87 |
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#define NRST_NANDC 88 |
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#define HRST_SFC 89 |
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#define SRST_SFC 90 |
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#define ARST_GMAC 91 |
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#define HRST_OTG 92 |
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#define SRST_OTG 93 |
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#define SRST_OTG_ADP 94 |
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#define HRST_HOST0 95 |
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#define HRST_HOST0_AUX 96 |
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#define HRST_HOST0_ARB 97 |
||||
#define SRST_HOST0_EHCIPHY 98 |
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#define SRST_HOST0_UTMI 99 |
||||
#define SRST_USBPOR 100 |
||||
#define SRST_UTMI0 101 |
||||
#define SRST_UTMI1 102 |
||||
|
||||
#define ARST_VIO0_NIU 102 |
||||
#define ARST_VIO1_NIU 103 |
||||
#define HRST_VIO_NIU 104 |
||||
#define PRST_VIO_NIU 105 |
||||
#define ARST_VOP 106 |
||||
#define HRST_VOP 107 |
||||
#define DRST_VOP 108 |
||||
#define ARST_IEP 109 |
||||
#define HRST_IEP 110 |
||||
#define ARST_RGA 111 |
||||
#define HRST_RGA 112 |
||||
#define SRST_RGA 113 |
||||
#define PRST_CVBS 114 |
||||
#define PRST_HDMI 115 |
||||
#define SRST_HDMI 116 |
||||
#define PRST_MIPI_DSI 117 |
||||
|
||||
#define ARST_ISP_NIU 118 |
||||
#define HRST_ISP_NIU 119 |
||||
#define HRST_ISP 120 |
||||
#define SRST_ISP 121 |
||||
#define ARST_VIP0 122 |
||||
#define HRST_VIP0 123 |
||||
#define PRST_VIP0 124 |
||||
#define ARST_VIP1 125 |
||||
#define HRST_VIP1 126 |
||||
#define PRST_VIP1 127 |
||||
#define ARST_VIP2 128 |
||||
#define HRST_VIP2 129 |
||||
#define PRST_VIP2 120 |
||||
#define ARST_VIP3 121 |
||||
#define HRST_VIP3 122 |
||||
#define PRST_VIP4 123 |
||||
|
||||
#define PRST_CIF1TO4 124 |
||||
#define SRST_CVBS_CLK 125 |
||||
#define HRST_CVBS 126 |
||||
|
||||
#define ARST_VPU_NIU 140 |
||||
#define HRST_VPU_NIU 141 |
||||
#define ARST_VPU 142 |
||||
#define HRST_VPU 143 |
||||
#define ARST_RKVDEC_NIU 144 |
||||
#define HRST_RKVDEC_NIU 145 |
||||
#define ARST_RKVDEC 146 |
||||
#define HRST_RKVDEC 147 |
||||
#define SRST_RKVDEC_CABAC 148 |
||||
#define SRST_RKVDEC_CORE 149 |
||||
#define ARST_RKVENC_NIU 150 |
||||
#define HRST_RKVENC_NIU 151 |
||||
#define ARST_RKVENC 152 |
||||
#define HRST_RKVENC 153 |
||||
#define SRST_RKVENC_CORE 154 |
||||
|
||||
#define SRST_DSP_CORE 156 |
||||
#define SRST_DSP_SYS 157 |
||||
#define SRST_DSP_GLOBAL 158 |
||||
#define SRST_DSP_OECM 159 |
||||
#define PRST_DSP_IOP_NIU 160 |
||||
#define ARST_DSP_EPP_NIU 161 |
||||
#define ARST_DSP_EDP_NIU 162 |
||||
#define PRST_DSP_DBG_NIU 163 |
||||
#define PRST_DSP_CFG_NIU 164 |
||||
#define PRST_DSP_GRF 165 |
||||
#define PRST_DSP_MAILBOX 166 |
||||
#define PRST_DSP_INTC 167 |
||||
#define PRST_DSP_PFM_MON 169 |
||||
#define SRST_DSP_PFM_MON 170 |
||||
#define ARST_DSP_EDAP_NIU 171 |
||||
|
||||
#define SRST_PMU 172 |
||||
#define SRST_PMU_I2C0 173 |
||||
#define PRST_PMU_I2C0 174 |
||||
#define PRST_PMU_GPIO0 175 |
||||
#define PRST_PMU_INTMEM 176 |
||||
#define PRST_PMU_PWM0 177 |
||||
#define SRST_PMU_PWM0 178 |
||||
#define PRST_PMU_GRF 179 |
||||
#define SRST_PMU_NIU 180 |
||||
#define SRST_PMU_PVTM 181 |
||||
#define ARST_DSP_EDP_PERF 184 |
||||
#define ARST_DSP_EPP_PERF 185 |
||||
|
||||
#endif /* _DT_BINDINGS_CLK_ROCKCHIP_RV1108_H */ |
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Reference in new issue