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imx: nand: update GPMI NAND driver to support MX7

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Update GPMI NAND driver and BCH head file to support i.MX7

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
master
Peng Fan 10 years ago committed by Stefano Babic
parent 1fc4f80495
commit bedaa842ae
2 changed files with 4 additions and 4 deletions
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  1. 4
      arch/arm/include/asm/imx-common/regs-bch.h
  2. 4
      drivers/mtd/nand/mxs_nand.c

4
arch/arm/include/asm/imx-common/regs-bch.h
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@ -123,7 +123,7 @@ struct mxs_bch_regs {
#define BCH_FLASHLAYOUT0_NBLOCKS_OFFSET 24 #define BCH_FLASHLAYOUT0_NBLOCKS_OFFSET 24
#define BCH_FLASHLAYOUT0_META_SIZE_MASK (0xff << 16) #define BCH_FLASHLAYOUT0_META_SIZE_MASK (0xff << 16)
#define BCH_FLASHLAYOUT0_META_SIZE_OFFSET 16 #define BCH_FLASHLAYOUT0_META_SIZE_OFFSET 16
#if defined(CONFIG_MX6) #if (defined(CONFIG_MX6) || defined(CONFIG_MX7))
#define BCH_FLASHLAYOUT0_ECC0_MASK (0x1f << 11) #define BCH_FLASHLAYOUT0_ECC0_MASK (0x1f << 11)
#define BCH_FLASHLAYOUT0_ECC0_OFFSET 11 #define BCH_FLASHLAYOUT0_ECC0_OFFSET 11
#else #else
@ -154,7 +154,7 @@ struct mxs_bch_regs {
#define BCH_FLASHLAYOUT1_PAGE_SIZE_MASK (0xffff << 16) #define BCH_FLASHLAYOUT1_PAGE_SIZE_MASK (0xffff << 16)
#define BCH_FLASHLAYOUT1_PAGE_SIZE_OFFSET 16 #define BCH_FLASHLAYOUT1_PAGE_SIZE_OFFSET 16
#if defined(CONFIG_MX6) #if (defined(CONFIG_MX6) || defined(CONFIG_MX7))
#define BCH_FLASHLAYOUT1_ECCN_MASK (0x1f << 11) #define BCH_FLASHLAYOUT1_ECCN_MASK (0x1f << 11)
#define BCH_FLASHLAYOUT1_ECCN_OFFSET 11 #define BCH_FLASHLAYOUT1_ECCN_OFFSET 11
#else #else

4
drivers/mtd/nand/mxs_nand.c
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@ -30,7 +30,7 @@
#define MXS_NAND_DMA_DESCRIPTOR_COUNT 4 #define MXS_NAND_DMA_DESCRIPTOR_COUNT 4
#define MXS_NAND_CHUNK_DATA_CHUNK_SIZE 512 #define MXS_NAND_CHUNK_DATA_CHUNK_SIZE 512
#if defined(CONFIG_MX6) #if (defined(CONFIG_MX6) || defined(CONFIG_MX7))
#define MXS_NAND_CHUNK_DATA_CHUNK_SIZE_SHIFT 2 #define MXS_NAND_CHUNK_DATA_CHUNK_SIZE_SHIFT 2
#else #else
#define MXS_NAND_CHUNK_DATA_CHUNK_SIZE_SHIFT 0 #define MXS_NAND_CHUNK_DATA_CHUNK_SIZE_SHIFT 0
@ -152,7 +152,7 @@ static inline uint32_t mxs_nand_get_ecc_strength(uint32_t page_data_size,
int max_ecc_strength_supported; int max_ecc_strength_supported;
/* Refer to Chapter 17 for i.MX6DQ, Chapter 18 for i.MX6SX */ /* Refer to Chapter 17 for i.MX6DQ, Chapter 18 for i.MX6SX */
if (is_cpu_type(MXC_CPU_MX6SX)) if (is_cpu_type(MXC_CPU_MX6SX) || is_soc_type(MXC_SOC_MX7))
max_ecc_strength_supported = 62; max_ecc_strength_supported = 62;
else else
max_ecc_strength_supported = 40; max_ecc_strength_supported = 40;

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