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@ -1,18 +1,149 @@ |
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-------------------------------------------- |
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---------------------------------------- |
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SOCFPGA Documentation for U-Boot and SPL |
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-------------------------------------------- |
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---------------------------------------- |
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This README is about U-Boot and SPL support for Altera's ARM Cortex-A9MPCore |
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based SOCFPGA. To know more about the hardware itself, please refer to |
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www.altera.com. |
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-------------------------------------------- |
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socfpga_dw_mmc |
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-------------------------------------------- |
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-------------- |
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Here are macro and detailed configuration required to enable DesignWare SDMMC |
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controller support within SOCFPGA |
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#define CONFIG_SYS_MMC_MAX_BLK_COUNT 256 |
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-> Using smaller max blk cnt to avoid flooding the limited stack in OCRAM |
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-------------------------------------------------- |
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Generating the handoff header files for U-Boot SPL |
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-------------------------------------------------- |
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This text is assuming quartus 16.1, but newer versions will probably work just fine too; |
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verified with DE1_SOC_Linux_FB demo project (https://github.com/VCTLabs/DE1_SOC_Linux_FB). |
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Updated/working projects should build using either process below. |
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Note: it *should* work from Quartus 14.0.200 onwards, however, the current vendor demo |
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projects must have the IP cores updated as shown below. |
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Rebuilding your Quartus project |
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------------------------------- |
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Choose one of the follwing methods, either command line or GUI. |
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Using the comaand line |
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~~~~~~~~~~~~~~~~~~~~~~ |
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First run the embedded command shell, using your path to the Quartus install: |
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$ /path/to/intelFPGA/16.1/embedded/embedded_command_shell.sh |
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Then (if necessary) update the IP cores in the project, generate HDL code, and |
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build the project: |
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$ cd path/to/project/dir |
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$ qsys-generate soc_system.qsys --upgrade-ip-cores |
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$ qsys-generate soc_system.qsys --synthesis=[VERILOG|VHDL] |
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$ quartus_sh --flow compile <project name> |
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Convert the resulting .sof file (SRAM object file) to .rbf file (Raw bit file): |
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$ quartus_cpf -c <project_name>.sof soc_system.rbf |
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Generate BSP handoff files |
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~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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You can run the bsp editor GUI below, or run the following command from the |
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project directory: |
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$ /path/to/bsb/tools/bsp-create-settings --type spl --bsp-dir build \ |
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--preloader-settings-dir hps_isw_handoff/soc_system_hps_0/ \ |
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--settings build/settings.bsp |
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You should use the bsp "build" directory above (ie, where the settings.bsp file is) |
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in the following u-boot command to update the board headers. Once these headers |
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are updated for a given project build, u-boot should be configured for the |
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project board (eg, de0-nano-sockit) and then build the normal spl build. |
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Now you can skip the GUI section. |
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Using the Qsys GUI |
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~~~~~~~~~~~~~~~~~~ |
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1. Navigate to your project directory |
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2. Run Quartus II |
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3. Open Project (Ctrl+J), select <project_name>.qpf |
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4. Run QSys [Tools->QSys] |
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4.1 In the Open dialog, select '<project_name>.qsys' |
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4.2 In the Open System dialog, wait until completion and press 'Close' |
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4.3 In the Qsys window, click on 'Generate HDL...' in bottom right corner |
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4.3.1 In the 'Generation' window, click 'Generate' |
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4.3.2 In the 'Generate' dialog, wait until completion and click 'Close' |
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4.4 In the QSys window, click 'Finish' |
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4.4.1 In the 'Quartus II' pop up window, click 'OK' |
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5. Back in Quartus II main window, do the following |
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5.1 Use Processing -> Start -> Start Analysis & Synthesis (Ctrl+K) |
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5.2 Use Processing -> Start Compilation (Ctrl+L) |
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... this may take some time, have patience ... |
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6. Start the embedded command shell as shown in the previous section |
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6.1 Change directory to 'software/spl_bsp' |
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6.2 Prepare BSP by launching the BSP editor from ECS |
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=> bsp-editor |
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6.3 In BSP editor |
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6.3.1 Use File -> Open |
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6.3.2 Select 'settings.bsp' file |
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6.3.3 Click Generate |
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6.3.4 Click Exit |
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Post handoff generation |
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~~~~~~~~~~~~~~~~~~~~~~~ |
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Now that the handoff files are generated, U-Boot can be used to process |
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the handoff files generated by the bsp-editor. For this, please use the |
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following script from the u-boot source tree: |
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$ ./arch/arm/mach-socfpga/qts-filter.sh \ |
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<soc_type> \ |
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<input_qts_dir> \ |
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<input_bsp_dir> \ |
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<output_dir> |
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Process QTS-generated files into U-Boot compatible ones. |
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soc_type - Type of SoC, either 'cyclone5' or 'arria5'. |
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input_qts_dir - Directory with compiled Quartus project |
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and containing the Quartus project file (QPF). |
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input_bsp_dir - Directory with generated bsp containing |
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the settings.bsp file. |
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output_dir - Directory to store the U-Boot compatible |
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headers. |
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This will generate (or update) the following 4 files: |
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iocsr_config.h |
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pinmux_config.h |
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pll_config.h |
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sdram_config.h |
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These files should be copied into "qts" directory in the board directory |
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(see output argument of qts-filter.sh command above). |
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Here is an example for the DE-0 Nano SoC after the above rebuild process: |
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$ ll board/terasic/de0-nano-soc/qts/ |
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total 36 |
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-rw-r--r-- 1 sarnold sarnold 8826 Mar 21 18:11 iocsr_config.h |
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-rw-r--r-- 1 sarnold sarnold 4398 Mar 21 18:11 pinmux_config.h |
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-rw-r--r-- 1 sarnold sarnold 3190 Mar 21 18:11 pll_config.h |
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-rw-r--r-- 1 sarnold sarnold 9022 Mar 21 18:11 sdram_config.h |
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Note: file sizes will differ slightly depending on the selected board. |
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Now your board is ready for full mainline support including U-Boot SPL. |
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The Preloader will not be needed any more. |
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Tom Rini
7 years ago