Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu> Acked-by: Stefan Roese <sr@denx.de>master
parent
92fa7f53f1
commit
cbdc662a2c
@ -1,15 +0,0 @@ |
|||||||
if TARGET_TASREG |
|
||||||
|
|
||||||
config SYS_CPU |
|
||||||
default "mcf52x2" |
|
||||||
|
|
||||||
config SYS_BOARD |
|
||||||
default "tasreg" |
|
||||||
|
|
||||||
config SYS_VENDOR |
|
||||||
default "esd" |
|
||||||
|
|
||||||
config SYS_CONFIG_NAME |
|
||||||
default "TASREG" |
|
||||||
|
|
||||||
endif |
|
@ -1,6 +0,0 @@ |
|||||||
TASREG BOARD |
|
||||||
M: Matthias Fuchs <matthias.fuchs@esd-electronics.com> |
|
||||||
S: Maintained |
|
||||||
F: board/esd/tasreg/ |
|
||||||
F: include/configs/TASREG.h |
|
||||||
F: configs/TASREG_defconfig |
|
@ -1,8 +0,0 @@ |
|||||||
#
|
|
||||||
# (C) Copyright 2000-2006
|
|
||||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
|
||||||
#
|
|
||||||
# SPDX-License-Identifier: GPL-2.0+
|
|
||||||
#
|
|
||||||
|
|
||||||
obj-y = tasreg.o flash.o
|
|
@ -1,9 +0,0 @@ |
|||||||
#
|
|
||||||
# (C) Copyright 2000-2003
|
|
||||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
|
||||||
# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com>
|
|
||||||
#
|
|
||||||
# SPDX-License-Identifier: GPL-2.0+
|
|
||||||
#
|
|
||||||
|
|
||||||
CONFIG_SYS_TEXT_BASE = 0xffc00000
|
|
@ -1,59 +0,0 @@ |
|||||||
/*
|
|
||||||
* (C) Copyright 2001 |
|
||||||
* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com |
|
||||||
* |
|
||||||
* SPDX-License-Identifier: GPL-2.0+ |
|
||||||
*/ |
|
||||||
|
|
||||||
#include <common.h> |
|
||||||
/*#include <asm/ppc4xx.h>*/ |
|
||||||
#include <asm/processor.h> |
|
||||||
|
|
||||||
/*
|
|
||||||
* include common flash code (for esd boards) |
|
||||||
*/ |
|
||||||
#include "../common/flash.c" |
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
* Functions |
|
||||||
*/ |
|
||||||
static ulong flash_get_size (vu_long * addr, flash_info_t * info); |
|
||||||
static void flash_get_offsets (ulong base, flash_info_t * info); |
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
*/ |
|
||||||
|
|
||||||
unsigned long flash_init (void) |
|
||||||
{ |
|
||||||
unsigned long size_b0; |
|
||||||
int i; |
|
||||||
|
|
||||||
/* Init: no FLASHes known */ |
|
||||||
for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) { |
|
||||||
flash_info[i].flash_id = FLASH_UNKNOWN; |
|
||||||
} |
|
||||||
|
|
||||||
/* Static FLASH Bank configuration here - FIXME XXX */ |
|
||||||
|
|
||||||
size_b0 = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]); |
|
||||||
|
|
||||||
if (flash_info[0].flash_id == FLASH_UNKNOWN) { |
|
||||||
printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", |
|
||||||
size_b0, size_b0<<20); |
|
||||||
} |
|
||||||
|
|
||||||
/* Setup offsets */ |
|
||||||
flash_get_offsets (-size_b0, &flash_info[0]); |
|
||||||
|
|
||||||
/* test-only: todo: Re-do sizing to get full correct info */ |
|
||||||
|
|
||||||
/* Monitor protection ON by default */ |
|
||||||
(void)flash_protect(FLAG_PROTECT_SET, |
|
||||||
CONFIG_SYS_FLASH_BASE, |
|
||||||
CONFIG_SYS_FLASH_BASE+CONFIG_SYS_MONITOR_LEN-1, |
|
||||||
&flash_info[0]); |
|
||||||
|
|
||||||
flash_info[0].size = size_b0; |
|
||||||
|
|
||||||
return (size_b0); |
|
||||||
} |
|
File diff suppressed because it is too large
Load Diff
@ -1,432 +0,0 @@ |
|||||||
/*
|
|
||||||
* (C) Copyright 2004 |
|
||||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
|
||||||
* |
|
||||||
* SPDX-License-Identifier: GPL-2.0+ |
|
||||||
*/ |
|
||||||
|
|
||||||
#include <common.h> |
|
||||||
#include <command.h> |
|
||||||
#include <malloc.h> |
|
||||||
#include <asm/m5249.h> |
|
||||||
#include <asm/io.h> |
|
||||||
|
|
||||||
|
|
||||||
/* Prototypes */ |
|
||||||
int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len); |
|
||||||
int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len); |
|
||||||
|
|
||||||
|
|
||||||
#if 0 |
|
||||||
#define FPGA_DEBUG |
|
||||||
#endif |
|
||||||
|
|
||||||
/* predefine these here for FPGA programming (before including fpga.c) */ |
|
||||||
#define SET_FPGA(data) mbar2_writeLong(MCFSIM_GPIO1_OUT, data) |
|
||||||
#define FPGA_DONE_STATE (mbar2_readLong(MCFSIM_GPIO1_READ) & CONFIG_SYS_FPGA_DONE) |
|
||||||
#define FPGA_INIT_STATE (mbar2_readLong(MCFSIM_GPIO1_READ) & CONFIG_SYS_FPGA_INIT) |
|
||||||
#define FPGA_PROG_ACTIVE_HIGH /* on this platform is PROG active high! */ |
|
||||||
#define out32(a,b) /* nothing to do (gpio already configured) */ |
|
||||||
|
|
||||||
|
|
||||||
/* fpga configuration data - generated by bin2cc */ |
|
||||||
const unsigned char fpgadata[] = |
|
||||||
{ |
|
||||||
#include "fpgadata.c" |
|
||||||
}; |
|
||||||
|
|
||||||
/*
|
|
||||||
* include common fpga code (for esd boards) |
|
||||||
*/ |
|
||||||
#include "../common/fpga.c" |
|
||||||
|
|
||||||
|
|
||||||
int checkboard (void) { |
|
||||||
ulong val; |
|
||||||
uchar val8; |
|
||||||
|
|
||||||
puts ("Board: "); |
|
||||||
puts("esd TASREG"); |
|
||||||
val8 = ((uchar)~((uchar)mbar2_readLong(MCFSIM_GPIO1_READ) >> 4)) & 0xf; |
|
||||||
printf(" (Switch=%1X)\n", val8); |
|
||||||
|
|
||||||
/*
|
|
||||||
* Set LED on |
|
||||||
*/ |
|
||||||
val = mbar2_readLong(MCFSIM_GPIO1_OUT) & ~CONFIG_SYS_GPIO1_LED; |
|
||||||
mbar2_writeLong(MCFSIM_GPIO1_OUT, val); /* Set LED on */ |
|
||||||
|
|
||||||
return 0; |
|
||||||
}; |
|
||||||
|
|
||||||
|
|
||||||
phys_size_t initdram (int board_type) { |
|
||||||
unsigned long junk = 0xa5a59696; |
|
||||||
|
|
||||||
/*
|
|
||||||
* Note: |
|
||||||
* RC = ([(RefreshTime/#rows) / (1/BusClk)] / 16) - 1 |
|
||||||
*/ |
|
||||||
|
|
||||||
#ifdef CONFIG_SYS_FAST_CLK |
|
||||||
/*
|
|
||||||
* Busclk=70MHz, RefreshTime=64ms, #rows=4096 (4K) |
|
||||||
* SO=1, NAM=0, COC=0, RTIM=01 (6clk refresh), RC=39 |
|
||||||
*/ |
|
||||||
mbar_writeShort(MCFSIM_DCR, 0x8239); |
|
||||||
#elif CONFIG_SYS_PLL_BYPASS |
|
||||||
/*
|
|
||||||
* Busclk=5.6448MHz, RefreshTime=64ms, #rows=8192 (8K) |
|
||||||
* SO=1, NAM=0, COC=0, RTIM=01 (6clk refresh), RC=02 |
|
||||||
*/ |
|
||||||
mbar_writeShort(MCFSIM_DCR, 0x8202); |
|
||||||
#else |
|
||||||
/*
|
|
||||||
* Busclk=36MHz, RefreshTime=64ms, #rows=4096 (4K) |
|
||||||
* SO=1, NAM=0, COC=0, RTIM=01 (6clk refresh), RC=22 (562 bus clock cycles) |
|
||||||
*/ |
|
||||||
mbar_writeShort(MCFSIM_DCR, 0x8222); |
|
||||||
#endif |
|
||||||
|
|
||||||
/*
|
|
||||||
* SDRAM starts at 0x0000_0000, CASL=10, CBM=010, PS=10 (16bit port), |
|
||||||
* PM=1 (continuous page mode) |
|
||||||
*/ |
|
||||||
|
|
||||||
/* RE=0 (keep auto-refresh disabled while setting up registers) */ |
|
||||||
mbar_writeLong(MCFSIM_DACR0, 0x00003324); |
|
||||||
|
|
||||||
/* BAM=007c (bits 22,21 are bank selects; 256kB blocks) */ |
|
||||||
mbar_writeLong(MCFSIM_DMR0, 0x01fc0001); |
|
||||||
|
|
||||||
/** Precharge sequence **/ |
|
||||||
mbar_writeLong(MCFSIM_DACR0, 0x0000332c); /* Set DACR0[IP] (bit 3) */ |
|
||||||
out_be32((void *)0, junk); /* write to a memory location to init. precharge */ |
|
||||||
udelay(0x10); /* Allow several Precharge cycles */ |
|
||||||
|
|
||||||
/** Refresh Sequence **/ |
|
||||||
mbar_writeLong(MCFSIM_DACR0, 0x0000b324); /* Enable the refresh bit, DACR0[RE] (bit 15) */ |
|
||||||
udelay(0x7d0); /* Allow gobs of refresh cycles */ |
|
||||||
|
|
||||||
/** Mode Register initialization **/ |
|
||||||
mbar_writeLong(MCFSIM_DACR0, 0x0000b364); /* Enable DACR0[IMRS] (bit 6); RE remains enabled */ |
|
||||||
out_be32((void *)0x800, junk); /* Access RAM to initialize the mode register */ |
|
||||||
|
|
||||||
return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; |
|
||||||
}; |
|
||||||
|
|
||||||
|
|
||||||
int testdram (void) { |
|
||||||
/* TODO: XXX XXX XXX */ |
|
||||||
printf ("DRAM test not implemented!\n"); |
|
||||||
|
|
||||||
return (0); |
|
||||||
} |
|
||||||
|
|
||||||
|
|
||||||
int misc_init_r (void) |
|
||||||
{ |
|
||||||
unsigned char *dst; |
|
||||||
ulong len = sizeof(fpgadata); |
|
||||||
int status; |
|
||||||
int index; |
|
||||||
int i; |
|
||||||
uchar buf[8]; |
|
||||||
|
|
||||||
dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE); |
|
||||||
if (gunzip (dst, CONFIG_SYS_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) { |
|
||||||
printf ("GUNZIP ERROR - must RESET board to recover\n"); |
|
||||||
do_reset (NULL, 0, 0, NULL); |
|
||||||
} |
|
||||||
|
|
||||||
status = fpga_boot(dst, len); |
|
||||||
if (status != 0) { |
|
||||||
printf("\nFPGA: Booting failed "); |
|
||||||
switch (status) { |
|
||||||
case ERROR_FPGA_PRG_INIT_LOW: |
|
||||||
printf("(Timeout: INIT not low after asserting PROGRAM*)\n "); |
|
||||||
break; |
|
||||||
case ERROR_FPGA_PRG_INIT_HIGH: |
|
||||||
printf("(Timeout: INIT not high after deasserting PROGRAM*)\n "); |
|
||||||
break; |
|
||||||
case ERROR_FPGA_PRG_DONE: |
|
||||||
printf("(Timeout: DONE not high after programming FPGA)\n "); |
|
||||||
break; |
|
||||||
} |
|
||||||
|
|
||||||
/* display infos on fpgaimage */ |
|
||||||
index = 15; |
|
||||||
for (i=0; i<4; i++) { |
|
||||||
len = dst[index]; |
|
||||||
printf("FPGA: %s\n", &(dst[index+1])); |
|
||||||
index += len+3; |
|
||||||
} |
|
||||||
putc ('\n'); |
|
||||||
/* delayed reboot */ |
|
||||||
for (i=20; i>0; i--) { |
|
||||||
printf("Rebooting in %2d seconds \r",i); |
|
||||||
for (index=0;index<1000;index++) |
|
||||||
udelay(1000); |
|
||||||
} |
|
||||||
putc ('\n'); |
|
||||||
do_reset(NULL, 0, 0, NULL); |
|
||||||
} |
|
||||||
|
|
||||||
puts("FPGA: "); |
|
||||||
|
|
||||||
/* display infos on fpgaimage */ |
|
||||||
index = 15; |
|
||||||
for (i=0; i<4; i++) { |
|
||||||
len = dst[index]; |
|
||||||
printf("%s ", &(dst[index+1])); |
|
||||||
index += len+3; |
|
||||||
} |
|
||||||
putc ('\n'); |
|
||||||
|
|
||||||
free(dst); |
|
||||||
|
|
||||||
/*
|
|
||||||
* |
|
||||||
*/ |
|
||||||
buf[0] = 0x00; |
|
||||||
buf[1] = 0x32; |
|
||||||
buf[2] = 0x3f; |
|
||||||
i2c_write(0x38, 0, 0, buf, 3); |
|
||||||
|
|
||||||
return (0); |
|
||||||
} |
|
||||||
|
|
||||||
|
|
||||||
#if 1 /* test-only: board specific test commands */ |
|
||||||
int i2c_probe(uchar addr); |
|
||||||
|
|
||||||
/*
|
|
||||||
*/ |
|
||||||
int do_iploop(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) |
|
||||||
{ |
|
||||||
ulong addr; |
|
||||||
|
|
||||||
if (argc < 2) { |
|
||||||
puts("ERROR!\n"); |
|
||||||
return -1; |
|
||||||
} |
|
||||||
|
|
||||||
addr = simple_strtol (argv[1], NULL, 16); |
|
||||||
|
|
||||||
printf("i2c probe looping on addr 0x%lx (cntrl-c aborts)...\n", addr); |
|
||||||
|
|
||||||
for (;;) { |
|
||||||
i2c_probe(addr); |
|
||||||
|
|
||||||
/* Abort if ctrl-c was pressed */ |
|
||||||
if (ctrlc()) { |
|
||||||
puts("\nAbort\n"); |
|
||||||
return 0; |
|
||||||
} |
|
||||||
|
|
||||||
udelay(1000); |
|
||||||
} |
|
||||||
|
|
||||||
return 0; |
|
||||||
} |
|
||||||
U_BOOT_CMD( |
|
||||||
iploop, 2, 1, do_iploop, |
|
||||||
"i2c probe loop <addr>", |
|
||||||
"" |
|
||||||
); |
|
||||||
|
|
||||||
/*
|
|
||||||
*/ |
|
||||||
int do_codec(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) |
|
||||||
{ |
|
||||||
uchar buf[8]; |
|
||||||
|
|
||||||
out_be16((void *)0xe0000000, 0x4000); |
|
||||||
|
|
||||||
udelay(5000); /* wait for 5ms */ |
|
||||||
|
|
||||||
buf[0] = 0x10; |
|
||||||
buf[1] = 0x07; |
|
||||||
buf[2] = 0x03; |
|
||||||
i2c_write(0x10, 0, 0, buf, 3); |
|
||||||
|
|
||||||
buf[0] = 0x10; |
|
||||||
buf[1] = 0x01; |
|
||||||
buf[2] = 0x80; |
|
||||||
i2c_write(0x10, 0, 0, buf, 3); |
|
||||||
|
|
||||||
buf[0] = 0x10; |
|
||||||
buf[1] = 0x02; |
|
||||||
buf[2] = 0x03; |
|
||||||
i2c_write(0x10, 0, 0, buf, 3); |
|
||||||
|
|
||||||
buf[0] = 0x10; |
|
||||||
buf[1] = 0x03; |
|
||||||
buf[2] = 0x29; |
|
||||||
i2c_write(0x10, 0, 0, buf, 3); |
|
||||||
|
|
||||||
buf[0] = 0x10; |
|
||||||
buf[1] = 0x04; |
|
||||||
buf[2] = 0x00; |
|
||||||
i2c_write(0x10, 0, 0, buf, 3); |
|
||||||
|
|
||||||
buf[0] = 0x10; |
|
||||||
buf[1] = 0x05; |
|
||||||
buf[2] = 0x00; |
|
||||||
i2c_write(0x10, 0, 0, buf, 3); |
|
||||||
|
|
||||||
buf[0] = 0x10; |
|
||||||
buf[1] = 0x07; |
|
||||||
buf[2] = 0x02; |
|
||||||
i2c_write(0x10, 0, 0, buf, 3); |
|
||||||
|
|
||||||
return 0; |
|
||||||
} |
|
||||||
U_BOOT_CMD( |
|
||||||
codec, 1, 1, do_codec, |
|
||||||
"Enable codec", |
|
||||||
"" |
|
||||||
); |
|
||||||
|
|
||||||
/*
|
|
||||||
*/ |
|
||||||
int do_saa(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) |
|
||||||
{ |
|
||||||
ulong addr; |
|
||||||
ulong instr; |
|
||||||
ulong cntrl; |
|
||||||
ulong data; |
|
||||||
uchar buf[8]; |
|
||||||
|
|
||||||
if (argc < 5) { |
|
||||||
puts("ERROR!\n"); |
|
||||||
return -1; |
|
||||||
} |
|
||||||
|
|
||||||
addr = simple_strtol (argv[1], NULL, 16); |
|
||||||
instr = simple_strtol (argv[2], NULL, 16); |
|
||||||
cntrl = simple_strtol (argv[3], NULL, 16); |
|
||||||
data = simple_strtol (argv[4], NULL, 16); |
|
||||||
|
|
||||||
buf[0] = (uchar)instr; |
|
||||||
buf[1] = (uchar)cntrl; |
|
||||||
buf[2] = (uchar)data; |
|
||||||
i2c_write(addr, 0, 0, buf, 3); |
|
||||||
|
|
||||||
return 0; |
|
||||||
} |
|
||||||
U_BOOT_CMD( |
|
||||||
saa, 5, 1, do_saa, |
|
||||||
"Write to SAA1064 <addr> <instr> <cntrl> <data>", |
|
||||||
"" |
|
||||||
); |
|
||||||
|
|
||||||
/*
|
|
||||||
*/ |
|
||||||
int do_iwrite(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) |
|
||||||
{ |
|
||||||
ulong addr; |
|
||||||
ulong data0; |
|
||||||
ulong data1; |
|
||||||
ulong data2; |
|
||||||
ulong data3; |
|
||||||
uchar buf[8]; |
|
||||||
int cnt; |
|
||||||
|
|
||||||
if (argc < 3) { |
|
||||||
puts("ERROR!\n"); |
|
||||||
return -1; |
|
||||||
} |
|
||||||
|
|
||||||
addr = simple_strtol (argv[1], NULL, 16); |
|
||||||
cnt = simple_strtol (argv[2], NULL, 16); |
|
||||||
data0 = simple_strtol (argv[3], NULL, 16); |
|
||||||
data1 = simple_strtol (argv[4], NULL, 16); |
|
||||||
data2 = simple_strtol (argv[5], NULL, 16); |
|
||||||
data3 = simple_strtol (argv[6], NULL, 16); |
|
||||||
|
|
||||||
printf("Writing %d bytes to device %lx!\n", cnt, addr); |
|
||||||
buf[0] = (uchar)data0; |
|
||||||
buf[1] = (uchar)data1; |
|
||||||
buf[2] = (uchar)data2; |
|
||||||
buf[3] = (uchar)data3; |
|
||||||
i2c_write(addr, 0, 0, buf, cnt); |
|
||||||
|
|
||||||
return 0; |
|
||||||
} |
|
||||||
U_BOOT_CMD( |
|
||||||
iwrite, 6, 1, do_iwrite, |
|
||||||
"Write n bytes to I2C-device", |
|
||||||
"addr cnt data0 ... datan" |
|
||||||
); |
|
||||||
|
|
||||||
/*
|
|
||||||
*/ |
|
||||||
int do_iread(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) |
|
||||||
{ |
|
||||||
ulong addr; |
|
||||||
ulong cnt; |
|
||||||
uchar buf[32]; |
|
||||||
int i; |
|
||||||
|
|
||||||
if (argc < 3) { |
|
||||||
puts("ERROR!\n"); |
|
||||||
return -1; |
|
||||||
} |
|
||||||
|
|
||||||
addr = simple_strtol (argv[1], NULL, 16); |
|
||||||
cnt = simple_strtol (argv[2], NULL, 16); |
|
||||||
|
|
||||||
i2c_read(addr, 0, 0, buf, cnt); |
|
||||||
printf("I2C Data:"); |
|
||||||
for (i=0; i<cnt; i++) { |
|
||||||
printf(" %02X", buf[i]); |
|
||||||
} |
|
||||||
printf("\n"); |
|
||||||
|
|
||||||
return 0; |
|
||||||
} |
|
||||||
U_BOOT_CMD( |
|
||||||
iread, 3, 1, do_iread, |
|
||||||
"Read from I2C <addr> <cnt>", |
|
||||||
"" |
|
||||||
); |
|
||||||
|
|
||||||
/*
|
|
||||||
*/ |
|
||||||
int do_ireadl(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) |
|
||||||
{ |
|
||||||
ulong addr; |
|
||||||
uchar buf[32]; |
|
||||||
int cnt; |
|
||||||
|
|
||||||
if (argc < 2) { |
|
||||||
puts("ERROR!\n"); |
|
||||||
return -1; |
|
||||||
} |
|
||||||
|
|
||||||
addr = simple_strtol (argv[1], NULL, 16); |
|
||||||
cnt = 1; |
|
||||||
|
|
||||||
printf("iread looping on addr 0x%lx (cntrl-c aborts)...\n", addr); |
|
||||||
|
|
||||||
for (;;) { |
|
||||||
i2c_read(addr, 0, 0, buf, cnt); |
|
||||||
|
|
||||||
/* Abort if ctrl-c was pressed */ |
|
||||||
if (ctrlc()) { |
|
||||||
puts("\nAbort\n"); |
|
||||||
return 0; |
|
||||||
} |
|
||||||
|
|
||||||
udelay(3000); |
|
||||||
} |
|
||||||
|
|
||||||
return 0; |
|
||||||
} |
|
||||||
U_BOOT_CMD( |
|
||||||
ireadl, 2, 1, do_ireadl, |
|
||||||
"Read-loop from I2C <addr>", |
|
||||||
"" |
|
||||||
); |
|
||||||
#endif |
|
@ -1,82 +0,0 @@ |
|||||||
/* |
|
||||||
* (C) Copyright 2000 |
|
||||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
|
||||||
* |
|
||||||
* SPDX-License-Identifier: GPL-2.0+ |
|
||||||
*/ |
|
||||||
|
|
||||||
OUTPUT_ARCH(m68k) |
|
||||||
|
|
||||||
SECTIONS |
|
||||||
{ |
|
||||||
.text : |
|
||||||
{ |
|
||||||
arch/m68k/cpu/mcf52x2/start.o (.text*) |
|
||||||
|
|
||||||
*(.text*) |
|
||||||
} |
|
||||||
_etext = .; |
|
||||||
PROVIDE (etext = .); |
|
||||||
.rodata : |
|
||||||
{ |
|
||||||
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) |
|
||||||
} |
|
||||||
|
|
||||||
/* Read-write section, merged into data segment: */ |
|
||||||
. = (. + 0x00FF) & 0xFFFFFF00; |
|
||||||
_erotext = .; |
|
||||||
PROVIDE (erotext = .); |
|
||||||
|
|
||||||
.reloc : |
|
||||||
{ |
|
||||||
__got_start = .; |
|
||||||
KEEP(*(.got)) |
|
||||||
__got_end = .; |
|
||||||
_GOT2_TABLE_ = .; |
|
||||||
KEEP(*(.got2)) |
|
||||||
_FIXUP_TABLE_ = .; |
|
||||||
KEEP(*(.fixup)) |
|
||||||
} |
|
||||||
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; |
|
||||||
__fixup_entries = (. - _FIXUP_TABLE_)>>2; |
|
||||||
|
|
||||||
.data : |
|
||||||
{ |
|
||||||
*(.data*) |
|
||||||
*(.sdata*) |
|
||||||
} |
|
||||||
_edata = .; |
|
||||||
PROVIDE (edata = .); |
|
||||||
|
|
||||||
. = .; |
|
||||||
|
|
||||||
. = ALIGN(4); |
|
||||||
.u_boot_list : { |
|
||||||
KEEP(*(SORT(.u_boot_list*))); |
|
||||||
} |
|
||||||
|
|
||||||
. = .; |
|
||||||
__start___ex_table = .; |
|
||||||
__ex_table : { *(__ex_table) } |
|
||||||
__stop___ex_table = .; |
|
||||||
|
|
||||||
. = ALIGN(256); |
|
||||||
__init_begin = .; |
|
||||||
.text.init : { *(.text.init) } |
|
||||||
.data.init : { *(.data.init) } |
|
||||||
. = ALIGN(256); |
|
||||||
__init_end = .; |
|
||||||
|
|
||||||
__bss_start = .; |
|
||||||
.bss (NOLOAD) : |
|
||||||
{ |
|
||||||
_sbss = .; |
|
||||||
*(.bss*) |
|
||||||
*(.sbss*) |
|
||||||
*(COMMON) |
|
||||||
. = ALIGN(4); |
|
||||||
_ebss = .; |
|
||||||
} |
|
||||||
__bss_end = . ; |
|
||||||
PROVIDE (end = .); |
|
||||||
} |
|
@ -1,2 +0,0 @@ |
|||||||
CONFIG_M68K=y |
|
||||||
CONFIG_TARGET_TASREG=y |
|
@ -1,287 +0,0 @@ |
|||||||
/*
|
|
||||||
* Configuation settings for the esd TASREG board. |
|
||||||
* |
|
||||||
* (C) Copyright 2004 |
|
||||||
* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com |
|
||||||
* |
|
||||||
* SPDX-License-Identifier: GPL-2.0+ |
|
||||||
*/ |
|
||||||
|
|
||||||
/*
|
|
||||||
* board/config.h - configuration options, board specific |
|
||||||
*/ |
|
||||||
|
|
||||||
#ifndef _TASREG_H |
|
||||||
#define _TASREG_H |
|
||||||
|
|
||||||
#ifndef __ASSEMBLY__ |
|
||||||
#include <asm/m5249.h> |
|
||||||
#endif |
|
||||||
|
|
||||||
/*
|
|
||||||
* High Level Configuration Options |
|
||||||
* (easy to change) |
|
||||||
*/ |
|
||||||
#define CONFIG_MCF52x2 /* define processor family */ |
|
||||||
#define CONFIG_M5249 /* define processor type */ |
|
||||||
|
|
||||||
#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ |
|
||||||
|
|
||||||
#define CONFIG_MCFTMR |
|
||||||
|
|
||||||
#define CONFIG_MCFUART |
|
||||||
#define CONFIG_SYS_UART_PORT (0) |
|
||||||
#define CONFIG_BAUDRATE 19200 |
|
||||||
|
|
||||||
#undef CONFIG_WATCHDOG |
|
||||||
|
|
||||||
#undef CONFIG_MONITOR_IS_IN_RAM /* no pre-loader required!!! ;-) */ |
|
||||||
|
|
||||||
|
|
||||||
/*
|
|
||||||
* BOOTP options |
|
||||||
*/ |
|
||||||
#define CONFIG_BOOTP_BOOTFILESIZE |
|
||||||
#define CONFIG_BOOTP_BOOTPATH |
|
||||||
#define CONFIG_BOOTP_GATEWAY |
|
||||||
#define CONFIG_BOOTP_HOSTNAME |
|
||||||
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Command line configuration. |
|
||||||
*/ |
|
||||||
#include <config_cmd_default.h> |
|
||||||
|
|
||||||
#define CONFIG_CMD_BSP |
|
||||||
#define CONFIG_CMD_EEPROM |
|
||||||
#define CONFIG_CMD_I2C |
|
||||||
|
|
||||||
#undef CONFIG_CMD_NET |
|
||||||
|
|
||||||
|
|
||||||
#define CONFIG_BOOTDELAY 3 |
|
||||||
|
|
||||||
#define CONFIG_SYS_LONGHELP /* undef to save memory */ |
|
||||||
|
|
||||||
#if defined(CONFIG_CMD_KGDB) |
|
||||||
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
|
||||||
#else |
|
||||||
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
|
||||||
#endif |
|
||||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
|
||||||
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ |
|
||||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ |
|
||||||
|
|
||||||
#define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */ |
|
||||||
#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/ |
|
||||||
#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */ |
|
||||||
#define CONFIG_LOOPW 1 /* enable loopw command */ |
|
||||||
#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ |
|
||||||
|
|
||||||
#define CONFIG_SYS_LOAD_ADDR 0x200000 /* default load address */ |
|
||||||
|
|
||||||
#define CONFIG_SYS_MEMTEST_START 0x400 |
|
||||||
#define CONFIG_SYS_MEMTEST_END 0x380000 |
|
||||||
|
|
||||||
/*
|
|
||||||
* Clock configuration: enable only one of the following options |
|
||||||
*/ |
|
||||||
|
|
||||||
#if 0 /* this setting will run the cpu at 11MHz */
|
|
||||||
#define CONFIG_SYS_PLL_BYPASS 1 /* bypass PLL for test purpose */ |
|
||||||
#undef CONFIG_SYS_FAST_CLK /* MCF5249 can run at 140MHz */ |
|
||||||
#define CONFIG_SYS_CLK 11289600 /* PLL bypass */ |
|
||||||
#endif |
|
||||||
|
|
||||||
#if 0 /* this setting will run the cpu at 70MHz */
|
|
||||||
#undef CONFIG_SYS_PLL_BYPASS /* bypass PLL for test purpose */ |
|
||||||
#undef CONFIG_SYS_FAST_CLK /* MCF5249 can run at 140MHz */ |
|
||||||
#define CONFIG_SYS_CLK 72185018 /* The next lower speed */ |
|
||||||
#endif |
|
||||||
|
|
||||||
#if 1 /* this setting will run the cpu at 140MHz */ |
|
||||||
#undef CONFIG_SYS_PLL_BYPASS /* bypass PLL for test purpose */ |
|
||||||
#define CONFIG_SYS_FAST_CLK 1 /* MCF5249 can run at 140MHz */ |
|
||||||
#define CONFIG_SYS_CLK 132025600 /* MCF5249 can run at 140MHz */ |
|
||||||
#endif |
|
||||||
|
|
||||||
/*
|
|
||||||
* Low Level Configuration Settings |
|
||||||
* (address mappings, register initial values, etc.) |
|
||||||
* You should know what you are doing if you make changes here. |
|
||||||
*/ |
|
||||||
|
|
||||||
#define CONFIG_SYS_MBAR 0x10000000 /* Register Base Addrs */ |
|
||||||
#define CONFIG_SYS_MBAR2 0x80000000 |
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
* I2C |
|
||||||
*/ |
|
||||||
#define CONFIG_SYS_I2C |
|
||||||
#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ |
|
||||||
#define CONFIG_SYS_I2C_SOFT_SPEED 100000 |
|
||||||
#define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F |
|
||||||
|
|
||||||
#if 0 /* push-pull */
|
|
||||||
#define SDA 0x00800000 |
|
||||||
#define SCL 0x00000008 |
|
||||||
#define DIR0 *((volatile ulong*)(CONFIG_SYS_MBAR2+MCFSIM_GPIO_EN)) |
|
||||||
#define DIR1 *((volatile ulong*)(CONFIG_SYS_MBAR2+MCFSIM_GPIO1_EN)) |
|
||||||
#define OUT0 *((volatile ulong*)(CONFIG_SYS_MBAR2+MCFSIM_GPIO_OUT)) |
|
||||||
#define OUT1 *((volatile ulong*)(CONFIG_SYS_MBAR2+MCFSIM_GPIO1_OUT)) |
|
||||||
#define IN0 *((volatile ulong*)(CONFIG_SYS_MBAR2+MCFSIM_GPIO_READ)) |
|
||||||
#define IN1 *((volatile ulong*)(CONFIG_SYS_MBAR2+MCFSIM_GPIO1_READ)) |
|
||||||
#define I2C_INIT {OUT1|=SDA;OUT0|=SCL;} |
|
||||||
#define I2C_READ ((IN1&SDA)?1:0) |
|
||||||
#define I2C_SDA(x) {if(x)OUT1|=SDA;else OUT1&=~SDA;} |
|
||||||
#define I2C_SCL(x) {if(x)OUT0|=SCL;else OUT0&=~SCL;} |
|
||||||
#define I2C_DELAY {udelay(5);} |
|
||||||
#define I2C_ACTIVE {DIR1|=SDA;} |
|
||||||
#define I2C_TRISTATE {DIR1&=~SDA;} |
|
||||||
#else /* open-collector */ |
|
||||||
#define SDA 0x00800000 |
|
||||||
#define SCL 0x00000008 |
|
||||||
#define DIR0 *((volatile ulong*)(CONFIG_SYS_MBAR2+MCFSIM_GPIO_EN)) |
|
||||||
#define DIR1 *((volatile ulong*)(CONFIG_SYS_MBAR2+MCFSIM_GPIO1_EN)) |
|
||||||
#define OUT0 *((volatile ulong*)(CONFIG_SYS_MBAR2+MCFSIM_GPIO_OUT)) |
|
||||||
#define OUT1 *((volatile ulong*)(CONFIG_SYS_MBAR2+MCFSIM_GPIO1_OUT)) |
|
||||||
#define IN0 *((volatile ulong*)(CONFIG_SYS_MBAR2+MCFSIM_GPIO_READ)) |
|
||||||
#define IN1 *((volatile ulong*)(CONFIG_SYS_MBAR2+MCFSIM_GPIO1_READ)) |
|
||||||
#define I2C_INIT {DIR1&=~SDA;DIR0&=~SCL;OUT1&=~SDA;OUT0&=~SCL;} |
|
||||||
#define I2C_READ ((IN1&SDA)?1:0) |
|
||||||
#define I2C_SDA(x) {if(x)DIR1&=~SDA;else DIR1|=SDA;} |
|
||||||
#define I2C_SCL(x) {if(x)DIR0&=~SCL;else DIR0|=SCL;} |
|
||||||
#define I2C_DELAY {udelay(5);} |
|
||||||
#define I2C_ACTIVE {DIR1|=SDA;} |
|
||||||
#define I2C_TRISTATE {DIR1&=~SDA;} |
|
||||||
#endif |
|
||||||
|
|
||||||
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC32 */ |
|
||||||
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */ |
|
||||||
/* mask of address bits that overflow into the "EEPROM chip address" */ |
|
||||||
#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x01 |
|
||||||
/*
|
|
||||||
* The Catalyst CAT24WC32 has 32 byte page write mode using |
|
||||||
* last 5 bits of the address |
|
||||||
*/ |
|
||||||
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 |
|
||||||
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ |
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
* Definitions for initial stack pointer and data area (in DPRAM) |
|
||||||
*/ |
|
||||||
#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 |
|
||||||
#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */ |
|
||||||
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
|
||||||
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
|
||||||
|
|
||||||
#define CONFIG_ENV_IS_IN_FLASH 1 |
|
||||||
#define CONFIG_ENV_ADDR 0xFFC40000 /* Address of Environment Sector*/ |
|
||||||
#define CONFIG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */ |
|
||||||
#define CONFIG_ENV_SECT_SIZE 0x10000 /* see README - env sector total size */ |
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
* Start addresses for the final memory configuration |
|
||||||
* (Set up by the startup code) |
|
||||||
* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
|
||||||
*/ |
|
||||||
#define CONFIG_SYS_SDRAM_BASE 0x00000000 |
|
||||||
#define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */ |
|
||||||
#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE |
|
||||||
|
|
||||||
#if 0 /* test-only */
|
|
||||||
#define CONFIG_PRAM 512 /* test-only for SDRAM problem!!!!!!!!!!!!!!!!!!!! */ |
|
||||||
#endif |
|
||||||
|
|
||||||
#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) |
|
||||||
|
|
||||||
#define CONFIG_SYS_MONITOR_LEN 0x20000 |
|
||||||
#define CONFIG_SYS_MALLOC_LEN (1 * 1024*1024) /* Reserve 1 MB for malloc() */ |
|
||||||
#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 |
|
||||||
|
|
||||||
/*
|
|
||||||
* For booting Linux, the board info and command line data |
|
||||||
* have to be in the first 8 MB of memory, since this is |
|
||||||
* the maximum mapped by the Linux kernel during initialization ?? |
|
||||||
*/ |
|
||||||
#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
* FLASH organization |
|
||||||
*/ |
|
||||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
|
||||||
#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ |
|
||||||
|
|
||||||
#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
|
||||||
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ |
|
||||||
|
|
||||||
#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */ |
|
||||||
#define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */ |
|
||||||
#define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */ |
|
||||||
/*
|
|
||||||
* The following defines are added for buggy IOP480 byte interface. |
|
||||||
* All other boards should use the standard values (CPCI405 etc.) |
|
||||||
*/ |
|
||||||
#define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */ |
|
||||||
#define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */ |
|
||||||
#define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */ |
|
||||||
|
|
||||||
#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ |
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
* Cache Configuration |
|
||||||
*/ |
|
||||||
#define CONFIG_SYS_CACHELINE_SIZE 16 |
|
||||||
|
|
||||||
#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ |
|
||||||
CONFIG_SYS_INIT_RAM_SIZE - 8) |
|
||||||
#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ |
|
||||||
CONFIG_SYS_INIT_RAM_SIZE - 4) |
|
||||||
#define CONFIG_SYS_ICACHE_INV (CF_CACR_DCM) |
|
||||||
#define CONFIG_SYS_CACHE_ACR1 (CONFIG_SYS_SDRAM_BASE | \ |
|
||||||
CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
|
|
||||||
CF_ACR_EN | CF_ACR_SM_ALL) |
|
||||||
#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CEIB | \ |
|
||||||
CF_CACR_DBWE) |
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
* Memory bank definitions |
|
||||||
*/ |
|
||||||
|
|
||||||
/* CS0 - AMD Flash, address 0xffc00000 */ |
|
||||||
#define CONFIG_SYS_CS0_BASE 0xffc00000 |
|
||||||
#define CONFIG_SYS_CS0_CTRL 0x00001980 /* WS=0110, AA=1, PS=10 */ |
|
||||||
/** Note: There is a CSMR0/DRAM vector problem, need to disable C/I ***/ |
|
||||||
#define CONFIG_SYS_CS0_MASK 0x003f0021 /* 4MB, AA=0, WP=0, C/I=1, V=1 */ |
|
||||||
|
|
||||||
/* CS1 - FPGA, address 0xe0000000 */ |
|
||||||
#define CONFIG_SYS_CS1_BASE 0xe0000000 |
|
||||||
#define CONFIG_SYS_CS1_CTRL 0x00000d80 /* WS=0011, AA=1, PS=10 */ |
|
||||||
#define CONFIG_SYS_CS1_MASK 0x00010001 /* 128kB, AA=0, WP=0, C/I=0, V=1*/ |
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
* Port configuration |
|
||||||
*/ |
|
||||||
#define CONFIG_SYS_GPIO_FUNC 0x00000008 /* Set gpio pins: none */ |
|
||||||
#define CONFIG_SYS_GPIO1_FUNC 0x00df00f0 /* 36-39(SWITCH),48-52(FPGAs),54*/ |
|
||||||
#define CONFIG_SYS_GPIO_EN 0x00000008 /* Set gpio output enable */ |
|
||||||
#define CONFIG_SYS_GPIO1_EN 0x00c70000 /* Set gpio output enable */ |
|
||||||
#define CONFIG_SYS_GPIO_OUT 0x00000008 /* Set outputs to default state */ |
|
||||||
#define CONFIG_SYS_GPIO1_OUT 0x00c70000 /* Set outputs to default state */ |
|
||||||
|
|
||||||
#define CONFIG_SYS_GPIO1_LED 0x00400000 /* user led */ |
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
* FPGA stuff |
|
||||||
*/ |
|
||||||
#define CONFIG_SYS_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */ |
|
||||||
#define CONFIG_SYS_FPGA_MAX_SIZE 512*1024 /* 512kByte is enough for XC2S200*/ |
|
||||||
|
|
||||||
/* FPGA program pin configuration */ |
|
||||||
#define CONFIG_SYS_FPGA_PRG 0x00010000 /* FPGA program pin (ppc output) */ |
|
||||||
#define CONFIG_SYS_FPGA_CLK 0x00040000 /* FPGA clk pin (ppc output) */ |
|
||||||
#define CONFIG_SYS_FPGA_DATA 0x00020000 /* FPGA data pin (ppc output) */ |
|
||||||
#define CONFIG_SYS_FPGA_INIT 0x00080000 /* FPGA init pin (ppc input) */ |
|
||||||
#define CONFIG_SYS_FPGA_DONE 0x00100000 /* FPGA done pin (ppc input) */ |
|
||||||
|
|
||||||
#endif /* _TASREG_H */ |
|
Loading…
Reference in new issue