Whitebox
/
u-boot
1
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity

microblaze: Fix irq.S code

Browse Source 
It is ancient code. There is possible to save several instructions
just if we use offset instead of addik

Signed-off-by: Michal Simek <monstr@monstr.eu>
master
Michal Simek 15 years ago
parent 398b1d57a6
commit cc53690e05
1 changed files with 62 additions and 120 deletions
Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL
Show Stats Download Patch File Download Diff File
  1. 182
      arch/microblaze/cpu/irq.S

182
arch/microblaze/cpu/irq.S
Unescape View File

@ -27,129 +27,71 @@
.text
.global _interrupt_handler
_interrupt_handler:
addi r1, r1, -4
swi r2, r1, 0
addi r1, r1, -4
swi r3, r1, 0
addi r1, r1, -4
swi r4, r1, 0
addi r1, r1, -4
swi r5, r1, 0
addi r1, r1, -4
swi r6, r1, 0
addi r1, r1, -4
swi r7, r1, 0
addi r1, r1, -4
swi r8, r1, 0
addi r1, r1, -4
swi r9, r1, 0
addi r1, r1, -4
swi r10, r1, 0
addi r1, r1, -4
swi r11, r1, 0
addi r1, r1, -4
swi r12, r1, 0
addi r1, r1, -4
swi r13, r1, 0
addi r1, r1, -4
swi r14, r1, 0
addi r1, r1, -4
swi r15, r1, 0
addi r1, r1, -4
swi r16, r1, 0
addi r1, r1, -4
swi r17, r1, 0
addi r1, r1, -4
swi r18, r1, 0
addi r1, r1, -4
swi r19, r1, 0
addi r1, r1, -4
swi r20, r1, 0
addi r1, r1, -4
swi r21, r1, 0
addi r1, r1, -4
swi r22, r1, 0
addi r1, r1, -4
swi r23, r1, 0
addi r1, r1, -4
swi r24, r1, 0
addi r1, r1, -4
swi r25, r1, 0
addi r1, r1, -4
swi r26, r1, 0
addi r1, r1, -4
swi r27, r1, 0
addi r1, r1, -4
swi r28, r1, 0
addi r1, r1, -4
swi r29, r1, 0
addi r1, r1, -4
swi r30, r1, 0
addi r1, r1, -4
swi r31, r1, 0
swi r2, r1, -4
swi r3, r1, -8
swi r4, r1, -12
swi r5, r1, -16
swi r6, r1, -20
swi r7, r1, -24
swi r8, r1, -28
swi r9, r1, -32
swi r10, r1, -36
swi r11, r1, -40
swi r12, r1, -44
swi r13, r1, -48
swi r14, r1, -52
swi r15, r1, -56
swi r16, r1, -60
swi r17, r1, -64
swi r18, r1, -68
swi r19, r1, -72
swi r20, r1, -76
swi r21, r1, -80
swi r22, r1, -84
swi r23, r1, -88
swi r24, r1, -92
swi r25, r1, -96
swi r26, r1, -100
swi r27, r1, -104
swi r28, r1, -108
swi r29, r1, -112
swi r30, r1, -116
swi r31, r1, -120
addik r1, r1, -124
brlid r15, interrupt_handler
nop
nop
lwi r31, r1, 0
addi r1, r1, 4
lwi r30, r1, 0
addi r1, r1, 4
lwi r29, r1, 0
addi r1, r1, 4
lwi r28, r1, 0
addi r1, r1, 4
lwi r27, r1, 0
addi r1, r1, 4
lwi r26, r1, 0
addi r1, r1, 4
lwi r25, r1, 0
addi r1, r1, 4
lwi r24, r1, 0
addi r1, r1, 4
lwi r23, r1, 0
addi r1, r1, 4
lwi r22, r1, 0
addi r1, r1, 4
lwi r21, r1, 0
addi r1, r1, 4
lwi r20, r1, 0
addi r1, r1, 4
lwi r19, r1, 0
addi r1, r1, 4
lwi r18, r1, 0
addi r1, r1, 4
lwi r17, r1, 0
addi r1, r1, 4
lwi r16, r1, 0
addi r1, r1, 4
lwi r15, r1, 0
addi r1, r1, 4
lwi r14, r1, 0
addi r1, r1, 4
lwi r13, r1, 0
addi r1, r1, 4
lwi r12, r1, 0
addi r1, r1, 4
lwi r11, r1, 0
addi r1, r1, 4
lwi r10, r1, 0
addi r1, r1, 4
lwi r9, r1, 0
addi r1, r1, 4
lwi r8, r1, 0
addi r1, r1, 4
lwi r7, r1, 0
addi r1, r1, 4
lwi r6, r1, 0
addi r1, r1, 4
lwi r5, r1, 0
addi r1, r1, 4
lwi r4, r1, 0
addi r1, r1, 4
lwi r3, r1, 0
addi r1, r1, 4
lwi r2, r1, 0
addi r1, r1, 4
addik r1, r1, 124
lwi r31, r1, -120
lwi r30, r1, -116
lwi r29, r1, -112
lwi r28, r1, -108
lwi r27, r1, -104
lwi r26, r1, -100
lwi r25, r1, -96
lwi r24, r1, -92
lwi r23, r1, -88
lwi r22, r1, -84
lwi r21, r1, -80
lwi r20, r1, -76
lwi r19, r1, -72
lwi r18, r1, -68
lwi r17, r1, -64
lwi r16, r1, -60
lwi r15, r1, -56
lwi r14, r1, -52
lwi r13, r1, -48
lwi r12, r1, -44
lwi r11, r1, -40
lwi r10, r1, -36
lwi r9, r1, -32
lwi r8, r1, -28
lwi r7, r1, -24
lwi r6, r1, -20
lwi r5, r1, -16
lwi r4, r1, -12
lwi r3, r1, -8
lwi r2, r1, -4
/* enable_interrupt */
#ifdef XILINX_USE_MSR_INSTR

Write Preview
Loading…
Cancel
Save