Merge branch 'master' of git://git.denx.de/u-boot-imx

arch/arm/cpu/arm926ejs/mx25/reset.c

@@ -43,14 +43,14 @@ void reset_cpu (ulong ignored)
 {
 	struct wdog_regs *regs = (struct wdog_regs *)IMX_WDT_BASE;
 	/* Disable watchdog and set Time-Out field to 0 */
-	writel (0x00000000, &regs->wcr);
+	writew(0, &regs->wcr);
 
 	/* Write Service Sequence */
-	writel (0x00005555, &regs->wsr);
+	writew(WSR_UNLOCK1, &regs->wsr);
-	writel (0x0000AAAA, &regs->wsr);
+	writew(WSR_UNLOCK2, &regs->wsr);
 
 	/* Enable watchdog */
-	writel (WCR_WDE, &regs->wcr);
+	writew(WCR_WDE, &regs->wcr);
 
 	while (1) ;
 }

arch/arm/cpu/armv7/mx5/clock.c

@@ -269,7 +269,7 @@ u32 imx_get_fecclk(void)
 /*
  * Dump some core clockes.
  */
-int do_mx5_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+int do_mx5_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
 	u32 freq;
 

arch/arm/cpu/armv7/mx5/u-boot.lds

@@ -1,73 +0,0 @@
-/*
- * January 2004 - Changed to support H4 device
- * Copyright (c) 2004 Texas Instruments
- *
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
- *
- * (C) Copyright 2009 Freescale Semiconductor, Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
-OUTPUT_ARCH(arm)
-ENTRY(_start)
-SECTIONS
-{
-	. = 0x00000000;
-
-	. = ALIGN(4);
-	.text	   :
-	{
-	  arch/arm/cpu/armv7/start.o
-	  *(.text)
-	}
-
-	. = ALIGN(4);
-	.rodata : { *(.rodata) }
-
-	. = ALIGN(4);
-	.data : {
-		*(.data)
-	__datarel_start = .;
-		*(.data.rel)
-	__datarelrolocal_start = .;
-		*(.data.rel.ro.local)
-	__datarellocal_start = .;
-		*(.data.rel.local)
-	__datarelro_start = .;
-		*(.data.rel.ro)
-	}
-
-	__got_start = .;
-	. = ALIGN(4);
-	.got : { *(.got) }
-	__got_end = .;
-
-	. = .;
-	__u_boot_cmd_start = .;
-	.u_boot_cmd : { *(.u_boot_cmd) }
-	__u_boot_cmd_end = .;
-
-	. = ALIGN(4);
-	__bss_start = .;
-	.bss : { *(.bss) }
-	_end = .;
-}

arch/arm/include/asm/arch-mx25/imx-regs.h

@@ -108,11 +108,11 @@ struct gpt_regs {
 
 /* Watchdog Timer (WDOG) registers */
 struct wdog_regs {
-	u32 wcr;	/* Control */
+	u16 wcr;	/* Control */
-	u32 wsr;	/* Service */
+	u16 wsr;	/* Service */
-	u32 wrsr;	/* Reset Status */
+	u16 wrsr;	/* Reset Status */
-	u32 wicr;	/* Interrupt Control */
+	u16 wicr;	/* Interrupt Control */
-	u32 wmcr;	/* Misc Control */
+	u16 wmcr;	/* Misc Control */
 };
 
 /* IIM control registers */
@@ -308,7 +308,9 @@ struct iim_regs {
 #define GPT_CTRL_TEN		1		/* Timer enable	*/
 
 /* WDOG enable */
-#define WCR_WDE 0x04
+#define WCR_WDE 		0x04
+#define WSR_UNLOCK1		0x5555
+#define WSR_UNLOCK2		0xAAAA
 
 /* FUSE bank offsets */
 #define IIM0_MAC		0x1a

arch/arm/include/asm/arch-mx5/imx-regs.h

@@ -26,7 +26,8 @@
 /*
  * IRAM
  */
-#define IRAM_BASE_ADDR		0x1FFE8000	/* internal ram */
+#define IRAM_BASE_ADDR		0x1FFE0000	/* internal ram */
+#define IRAM_SIZE		0x00020000	/* 128 KB */
 /*
  * Graphics Memory of GPU
  */

board/freescale/mx51evk/config.mk

@@ -20,7 +20,6 @@
 # MA 02111-1307 USA
 #
 
-LDSCRIPT = $(CPUDIR)/$(SOC)/u-boot.lds
 CONFIG_SYS_TEXT_BASE = 0x97800000
 IMX_CONFIG = $(SRCTREE)/board/$(BOARDDIR)/imximage.cfg
 ALL += $(obj)u-boot.imx

board/freescale/mx51evk/mx51evk.c

@@ -52,9 +52,9 @@ u32 get_board_rev(void)
 
 int dram_init(void)
 {
-	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	/* dram_init must store complete ramsize in gd->ram_size */
-	gd->bd->bi_dram[0].size = get_ram_size((long *)PHYS_SDRAM_1,
+	gd->ram_size = get_ram_size((volatile void *)CONFIG_SYS_SDRAM_BASE,
-			PHYS_SDRAM_1_SIZE);
+				PHYS_SDRAM_1_SIZE);
 	return 0;
 }
 
@@ -188,10 +188,10 @@ static void power_init(void)
 	val &= ~PWGT2SPIEN;
 	pmic_reg_write(REG_POWER_MISC, val);
 
-	/* Write needed to update Charger 0 */
+	/* Externally powered */
-	pmic_reg_write(REG_CHARGE, VCHRG0 | VCHRG1 | VCHRG2 |
+	val = pmic_reg_read(REG_CHARGE);
-		ICHRG0 | ICHRG1 | ICHRG2 | ICHRG3 | ICHRGTR0 |
+	val |= ICHRG0 | ICHRG1 | ICHRG2 | ICHRG3 | CHGAUTOB;
-		OVCTRL1 | UCHEN | CHRGLEDEN | CYCLB);
+	pmic_reg_write(REG_CHARGE, val);
 
 	/* power up the system first */
 	pmic_reg_write(REG_POWER_MISC, PWUP);

board/ttcontrol/vision2/config.mk

@@ -20,6 +20,6 @@
 # MA 02111-1307 USA
 #
 
-LDSCRIPT = $(CPUDIR)/$(SOC)/u-boot.lds
+CONFIG_SYS_TEXT_BASE = 0x97800000
-TEXT_BASE = 0x97800000
 IMX_CONFIG = $(SRCTREE)/board/$(BOARDDIR)/imximage_hynix.cfg
+ALL += $(obj)u-boot.imx

include/configs/mx51evk.h

@@ -24,6 +24,7 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
+#include <asm/arch/imx-regs.h>
 
  /* High Level Configuration Options */
 
@@ -50,7 +51,6 @@
  * Size of malloc() pool
  */
 #define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 2 * 1024 * 1024)
-/* size in bytes reserved for initial data */
 
 #define BOARD_LATE_INIT
 
@@ -124,18 +124,42 @@
 
 #define CONFIG_LOADADDR		0x90800000	/* loadaddr env var */
 
-#define	CONFIG_EXTRA_ENV_SETTINGS					\
+#define CONFIG_EXTRA_ENV_SETTINGS \
-		"netdev=eth0\0"						\
+	"script=boot.scr\0" \
-		"uboot_addr=0xa0000000\0"				\
+	"uimage=uImage\0" \
-		"uboot=u-boot.bin\0"			\
+	"mmcdev=0\0" \
-		"loadaddr=0x90800000\0"			\
+	"mmcpart=2\0" \
-		"bootargs_base=setenv bootargs console=tty "\
+	"mmcroot=/dev/mmcblk0p3 rw\0" \
-			"console=ttymxc0,${baudrate}\0"\
+	"mmcrootfstype=ext3 rootwait\0" \
-		"bootargs_nfs=setenv bootargs ${bootargs} root=/dev/nfs "\
+	"mmcargs=setenv bootargs console=ttymxc0,${baudrate} " \
-			"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0"\
+		"root=${mmcroot} " \
-		"bootcmd=run bootcmd_net\0"				\
+		"rootfstype=${mmcrootfstype}\0" \
-		"bootcmd_net=run bootargs_base bootargs_nfs; "		\
+	"loadbootscript=" \
-			"tftpboot ${loadaddr} ${kernel}; bootm\0"
+		"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
+	"bootscript=echo Running bootscript from mmc ...; " \
+		"source\0" \
+	"loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \
+	"mmcboot=echo Booting from mmc ...; " \
+		"run mmcargs; " \
+		"bootm\0" \
+	"netargs=setenv bootargs console=ttymxc0,${baudrate} " \
+		"root=/dev/nfs " \
+		"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
+	"netboot=echo Booting from net ...; " \
+		"run netargs; " \
+		"dhcp ${uimage}; bootm\0" \
+
+#define CONFIG_BOOTCOMMAND \
+	"if mmc rescan ${mmcdev}; then " \
+		"if run loadbootscript; then " \
+			"run bootscript; " \
+		"else " \
+			"if run loaduimage; then " \
+				"run mmcboot; " \
+			"else run netboot; " \
+			"fi; " \
+		"fi; " \
+	"else run netboot; fi"
 
 #define CONFIG_ARP_TIMEOUT	200UL
 
@@ -143,6 +167,8 @@
  * Miscellaneous configurable options
  */
 #define CONFIG_SYS_LONGHELP		/* undef to save memory */
+#define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser */
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
 #define CONFIG_SYS_PROMPT		"MX51EVK U-Boot > "
 #define CONFIG_AUTO_COMPLETE
 #define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size */
@@ -173,6 +199,15 @@
 #define PHYS_SDRAM_1		CSD0_BASE_ADDR
 #define PHYS_SDRAM_1_SIZE	(512 * 1024 * 1024)
 
+#define CONFIG_SYS_SDRAM_BASE		(PHYS_SDRAM_1)
+#define CONFIG_SYS_INIT_RAM_ADDR	(IRAM_BASE_ADDR)
+#define CONFIG_SYS_INIT_RAM_SIZE	(IRAM_SIZE)
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
 #define CONFIG_SYS_DDR_CLKSEL	0
 #define CONFIG_SYS_CLKTL_CBCDR	0x59E35100
 

include/mc13892.h

@@ -29,24 +29,24 @@
 
 /* REG_CHARGE */
 
-#define VCHRG0		0
+#define VCHRG0		(1 << 0)
 #define VCHRG1		(1 << 1)
 #define VCHRG2		(1 << 2)
 #define ICHRG0		(1 << 3)
 #define ICHRG1		(1 << 4)
 #define ICHRG2		(1 << 5)
 #define ICHRG3		(1 << 6)
-#define ICHRGTR0	(1 << 7)
+#define TREN		(1 << 7)
-#define ICHRGTR1	(1 << 8)
+#define ACKLPB		(1 << 8)
-#define ICHRGTR2	(1 << 9)
+#define THCHKB		(1 << 9)
 #define FETOVRD		(1 << 10)
 #define FETCTRL		(1 << 11)
 #define RVRSMODE	(1 << 13)
-#define OVCTRL0		(1 << 15)
+#define PLIM0		(1 << 15)
-#define OVCTRL1		(1 << 16)
+#define PLIM1		(1 << 16)
-#define UCHEN		(1 << 17)
+#define PLIMDIS		(1 << 17)
 #define CHRGLEDEN	(1 << 18)
-#define CHRGRAWPDEN	(1 << 19)
+#define CHGTMRRST	(1 << 19)
 #define CHGRESTART	(1 << 20)
 #define CHGAUTOB	(1 << 21)
 #define CYCLB		(1 << 22)