-This patchs gives support for the embbedded ppc440 on the Virtex5 FPGAs -interrupts.c divided in uic.c and interrupts.c -xilinx_irq.c for xilinx interrupt controller -Include modifications propossed by Stefan Roese Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@uam.es> Acked-by: Stefan Roese <sr@denx.de>master
Ricardo Ribalda Delgado
17 years ago
committed by
Stefan Roese
parent
42246dacf6
commit
d865fd0980
@ -0,0 +1,209 @@ |
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/*
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* (C) Copyright 2000-2002 |
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
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* |
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* (C) Copyright 2002 (440 port) |
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* Scott McNutt, Artesyn Communication Producs, smcnutt@artsyncp.com |
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* |
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* (C) Copyright 2003 (440GX port) |
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* Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com |
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* |
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* (C) Copyright 2008 (PPC440X05 port for Virtex 5 FX) |
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* Ricardo Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es |
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* Work supported by Qtechnology (htpp://qtec.com)
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#include <common.h> |
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#include <watchdog.h> |
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#include <command.h> |
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#include <asm/processor.h> |
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#include <asm/interrupt.h> |
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#include <ppc4xx.h> |
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#include <ppc_asm.tmpl> |
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#include <commproc.h> |
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#if (UIC_MAX > 3) |
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#define UICB0_ALL (UIC_MASK(VECNUM_UIC1CI) | UIC_MASK(VECNUM_UIC1NCI) | \ |
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UIC_MASK(VECNUM_UIC2CI) | UIC_MASK(VECNUM_UIC2NCI) | \
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UIC_MASK(VECNUM_UIC3CI) | UIC_MASK(VECNUM_UIC3NCI)) |
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#elif (UIC_MAX > 2) |
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#define UICB0_ALL (UIC_MASK(VECNUM_UIC1CI) | UIC_MASK(VECNUM_UIC1NCI) | \ |
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UIC_MASK(VECNUM_UIC2CI) | UIC_MASK(VECNUM_UIC2NCI)) |
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#elif (UIC_MAX > 1) |
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#define UICB0_ALL (UIC_MASK(VECNUM_UIC1CI) | UIC_MASK(VECNUM_UIC1NCI)) |
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#else |
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#define UICB0_ALL 0 |
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#endif |
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u32 get_dcr(u16); |
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DECLARE_GLOBAL_DATA_PTR; |
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void pic_enable(void) |
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{ |
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#if (UIC_MAX > 1) |
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/* Install the UIC1 handlers */ |
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irq_install_handler(VECNUM_UIC1NCI, (void *)(void *)external_interrupt, |
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0); |
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irq_install_handler(VECNUM_UIC1CI, (void *)(void *)external_interrupt, |
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0); |
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#endif |
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#if (UIC_MAX > 2) |
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irq_install_handler(VECNUM_UIC2NCI, (void *)(void *)external_interrupt, |
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0); |
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irq_install_handler(VECNUM_UIC2CI, (void *)(void *)external_interrupt, |
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0); |
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#endif |
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#if (UIC_MAX > 3) |
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irq_install_handler(VECNUM_UIC3NCI, (void *)(void *)external_interrupt, |
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0); |
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irq_install_handler(VECNUM_UIC3CI, (void *)(void *)external_interrupt, |
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0); |
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#endif |
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} |
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/* Handler for UIC interrupt */ |
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static void uic_interrupt(u32 uic_base, int vec_base) |
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{ |
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u32 uic_msr; |
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u32 msr_shift; |
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int vec; |
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/*
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* Read masked interrupt status register to determine interrupt source |
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*/ |
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uic_msr = get_dcr(uic_base + UIC_MSR); |
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msr_shift = uic_msr; |
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vec = vec_base; |
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while (msr_shift != 0) { |
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if (msr_shift & 0x80000000) |
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interrupt_run_handler(vec); |
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/*
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* Shift msr to next position and increment vector |
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*/ |
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msr_shift <<= 1; |
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vec++; |
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} |
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} |
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/*
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* Handle external interrupts |
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*/ |
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void external_interrupt(struct pt_regs *regs) |
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{ |
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u32 uic_msr; |
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/*
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* Read masked interrupt status register to determine interrupt source |
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*/ |
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uic_msr = mfdcr(uic0msr); |
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#if (UIC_MAX > 1) |
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if ((UIC_MASK(VECNUM_UIC1CI) & uic_msr) || |
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(UIC_MASK(VECNUM_UIC1NCI) & uic_msr)) |
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uic_interrupt(UIC1_DCR_BASE, 32); |
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#endif |
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#if (UIC_MAX > 2) |
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if ((UIC_MASK(VECNUM_UIC2CI) & uic_msr) || |
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(UIC_MASK(VECNUM_UIC2NCI) & uic_msr)) |
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uic_interrupt(UIC2_DCR_BASE, 64); |
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#endif |
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#if (UIC_MAX > 3) |
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if ((UIC_MASK(VECNUM_UIC3CI) & uic_msr) || |
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(UIC_MASK(VECNUM_UIC3NCI) & uic_msr)) |
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uic_interrupt(UIC3_DCR_BASE, 96); |
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#endif |
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if (uic_msr & ~(UICB0_ALL)) |
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uic_interrupt(UIC0_DCR_BASE, 0); |
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mtdcr(uic0sr, uic_msr); |
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return; |
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} |
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void pic_irq_ack(unsigned int vec) |
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{ |
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if ((vec >= 0) && (vec < 32)) |
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mtdcr(uicsr, UIC_MASK(vec)); |
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#if (UIC_MAX > 1) |
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else if ((vec >= 32) && (vec < 64)) |
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mtdcr(uic1sr, UIC_MASK(vec)); |
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#endif |
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#if (UIC_MAX > 2) |
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else if ((vec >= 64) && (vec < 96)) |
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mtdcr(uic2sr, UIC_MASK(vec)); |
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#endif |
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#if (UIC_MAX > 3) |
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else if (vec >= 96) |
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mtdcr(uic3sr, UIC_MASK(vec)); |
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#endif |
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} |
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/*
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* Install and free a interrupt handler. |
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*/ |
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void pic_irq_enable(unsigned int vec) |
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{ |
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if ((vec >= 0) && (vec < 32)) |
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mtdcr(uicer, mfdcr(uicer) | UIC_MASK(vec)); |
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#if (UIC_MAX > 1) |
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else if ((vec >= 32) && (vec < 64)) |
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mtdcr(uic1er, mfdcr(uic1er) | UIC_MASK(vec)); |
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#endif |
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#if (UIC_MAX > 2) |
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else if ((vec >= 64) && (vec < 96)) |
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mtdcr(uic2er, mfdcr(uic2er) | UIC_MASK(vec)); |
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#endif |
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#if (UIC_MAX > 3) |
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else if (vec >= 96) |
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mtdcr(uic3er, mfdcr(uic3er) | UIC_MASK(vec)); |
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#endif |
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debug("Install interrupt for vector %d ==> %p\n", vec, handler); |
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} |
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void pic_irq_disable(unsigned int vec) |
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{ |
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if ((vec >= 0) && (vec < 32)) |
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mtdcr(uicer, mfdcr(uicer) & ~UIC_MASK(vec)); |
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#if (UIC_MAX > 1) |
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else if ((vec >= 32) && (vec < 64)) |
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mtdcr(uic1er, mfdcr(uic1er) & ~UIC_MASK(vec)); |
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#endif |
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#if (UIC_MAX > 2) |
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else if ((vec >= 64) && (vec < 96)) |
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mtdcr(uic2er, mfdcr(uic2er) & ~UIC_MASK(vec)); |
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#endif |
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#if (UIC_MAX > 3) |
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else if (vec >= 96) |
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mtdcr(uic3er, mfdcr(uic3er) & ~UIC_MASK(vec)); |
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#endif |
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} |
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@ -0,0 +1,100 @@ |
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/*
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* (C) Copyright 2008 |
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* Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es |
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* This work has been supported by: QTechnology http://qtec.com/
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* Based on interrupts.c Wolfgang Denk-DENX Software Engineering-wd@denx.de |
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* This program is free software: you can redistribute it and/or modify |
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* it under the terms of the GNU General Public License as published by |
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* the Free Software Foundation, either version 2 of the License, or |
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* (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/ |
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#include <common.h> |
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#include <watchdog.h> |
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#include <command.h> |
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#include <asm/processor.h> |
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#include <asm/interrupt.h> |
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#include <ppc4xx.h> |
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#include <ppc_asm.tmpl> |
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#include <commproc.h> |
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#include <asm/io.h> |
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#include <asm/xilinx_irq.h> |
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DECLARE_GLOBAL_DATA_PTR; |
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void pic_enable(void) |
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{ |
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debug("Xilinx PIC at 0x%8x\n", intc); |
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/*
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* Disable all external interrupts until they are |
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* explicitly requested. |
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*/ |
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out_be32((u32 *) IER, 0); |
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/* Acknowledge any pending interrupts just in case. */ |
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out_be32((u32 *) IAR, 0xffffffff); |
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/* Turn on the Master Enable. */ |
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out_be32((u32 *) MER, 0x3UL); |
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return; |
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} |
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int xilinx_pic_irq_get(void) |
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{ |
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u32 irq; |
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irq = in_be32((u32 *) IVR); |
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/* If no interrupt is pending then all bits of the IVR are set to 1. As
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* the IVR is as many bits wide as numbers of inputs are available. |
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* Therefore, if all bits of the IVR are set to one, its content will |
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* be bigger than XPAR_INTC_MAX_NUM_INTR_INPUTS. |
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*/ |
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if (irq >= XPAR_INTC_MAX_NUM_INTR_INPUTS) |
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irq = -1; /* report no pending interrupt. */ |
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debug("get_irq: %d\n", irq); |
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return (irq); |
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} |
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void pic_irq_enable(unsigned int irq) |
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{ |
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u32 mask = IRQ_MASK(irq); |
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debug("enable: %d\n", irq); |
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out_be32((u32 *) SIE, mask); |
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} |
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void pic_irq_disable(unsigned int irq) |
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{ |
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u32 mask = IRQ_MASK(irq); |
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debug("disable: %d\n", irq); |
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out_be32((u32 *) CIE, mask); |
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} |
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void pic_irq_ack(unsigned int irq) |
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{ |
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u32 mask = IRQ_MASK(irq); |
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debug("ack: %d\n", irq); |
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out_be32((u32 *) IAR, mask); |
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} |
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void external_interrupt(struct pt_regs *regs) |
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{ |
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int irq; |
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irq = xilinx_pic_irq_get(); |
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if (irq < 0) |
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return; |
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interrupt_run_handler(irq); |
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return; |
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} |
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@ -0,0 +1,36 @@ |
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/*
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* (C) Copyright 2008 |
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* Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es |
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* This work has been supported by: QTechnology http://qtec.com/
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* Based on interrupts.c Wolfgang Denk-DENX Software Engineering-wd@denx.de |
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* |
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* This program is free software: you can redistribute it and/or modify |
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* it under the terms of the GNU General Public License as published by |
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* the Free Software Foundation, either version 2 of the License, or |
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* (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/ |
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#ifndef INTERRUPT_H |
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#define INTERRUPT_H |
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#if defined(CONFIG_XILINX_440) |
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#include <asm/xilinx_irq.h> |
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#else |
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#include <asm/ppc4xx-uic.h> |
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#endif |
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void pic_enable(void); |
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void pic_irq_enable(unsigned int irq); |
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void pic_irq_disable(unsigned int irq); |
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void pic_irq_ack(unsigned int irq); |
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void external_interrupt(struct pt_regs *regs); |
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void interrupt_run_handler(int vec); |
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#endif |
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@ -0,0 +1,36 @@ |
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/*
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* (C) Copyright 2008 |
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* Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es |
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* This work has been supported by: QTechnology http://qtec.com/
|
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* Based on interrupts.c Wolfgang Denk-DENX Software Engineering-wd@denx.de |
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* This program is free software: you can redistribute it and/or modify |
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* it under the terms of the GNU General Public License as published by |
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* the Free Software Foundation, either version 2 of the License, or |
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* (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/ |
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#ifndef XILINX_IRQ_H |
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#define XILINX_IRQ_H |
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#define intc XPAR_INTC_0_BASEADDR |
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#define ISR (intc+(0*4)) /* Interrupt Status Register */ |
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#define IPR (intc+(1*4)) /* Interrupt Pending Register */ |
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#define IER (intc+(2*4)) /* Interrupt Enable Register */ |
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#define IAR (intc+(3*4)) /* Interrupt Acknowledge Register */ |
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#define SIE (intc+(4*4)) /* Set Interrupt Enable bits */ |
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#define CIE (intc+(5*4)) /* Clear Interrupt Enable bits */ |
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#define IVR (intc+(6*4)) /* Interrupt Vector Register */ |
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#define MER (intc+(7*4)) /* Master Enable Register */ |
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#define IRQ_MASK(irq) (1<<(irq&0x1f)) |
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#define IRQ_MAX XPAR_INTC_MAX_NUM_INTR_INPUTS |
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#endif |
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