@ -17,7 +17,9 @@
/* Link Definitions */
# define CONFIG_SYS_TEXT_BASE 0x30000000
# ifdef CONFIG_EMU
# define CONFIG_SYS_NO_FLASH
# endif
# define CONFIG_SUPPORT_RAW_INITRD
@ -118,6 +120,66 @@
# define CONFIG_SYS_NOR_FTIM3 0x04000000
# define CONFIG_SYS_IFC_CCR 0x01000000
# ifndef CONFIG_SYS_NO_FLASH
# define CONFIG_FLASH_CFI_DRIVER
# define CONFIG_SYS_FLASH_CFI
# define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
# define CONFIG_SYS_FLASH_QUIET_TEST
# define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
# define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
# define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
# define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
# define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
# define CONFIG_SYS_FLASH_EMPTY_INFO
# define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
# endif
# define CONFIG_NAND_FSL_IFC
# define CONFIG_SYS_NAND_MAX_ECCPOS 256
# define CONFIG_SYS_NAND_MAX_OOBFREE 2
# define CONFIG_SYS_NAND_BASE 0x520000000
# define CONFIG_SYS_NAND_BASE_PHYS 0x20000000
# define CONFIG_SYS_NAND_CSPR_EXT (0x0)
# define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
| CSPR_MSEL_NAND /* MSEL = NAND */ \
| CSPR_V )
# define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
# define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
| CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
| CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
| CSOR_NAND_RAL_3 /* RAL = 2Byes */ \
| CSOR_NAND_PGS_2K /* Page Size = 2K */ \
| CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \
| CSOR_NAND_PB ( 64 ) ) /*Pages Per Block = 64*/
# define CONFIG_SYS_NAND_ONFI_DETECTION
/* ONFI NAND Flash mode0 Timing Params */
# define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
FTIM0_NAND_TWP ( 0x18 ) | \
FTIM0_NAND_TWCHT ( 0x07 ) | \
FTIM0_NAND_TWH ( 0x0a ) )
# define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
FTIM1_NAND_TWBE ( 0x39 ) | \
FTIM1_NAND_TRR ( 0x0e ) | \
FTIM1_NAND_TRP ( 0x18 ) )
# define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
FTIM2_NAND_TREH ( 0x0a ) | \
FTIM2_NAND_TWHRE ( 0x1e ) )
# define CONFIG_SYS_NAND_FTIM3 0x0
# define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
# define CONFIG_SYS_MAX_NAND_DEVICE 1
# define CONFIG_MTD_NAND_VERIFY_WRITE
# define CONFIG_CMD_NAND
# define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
# define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
# define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY
# define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR