|
|
@ -2,6 +2,9 @@ |
|
|
|
* (C) Copyright 2003 |
|
|
|
* (C) Copyright 2003 |
|
|
|
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
|
|
|
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
|
|
|
* |
|
|
|
* |
|
|
|
|
|
|
|
* (C) Copyright 2004 |
|
|
|
|
|
|
|
* Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. |
|
|
|
|
|
|
|
* |
|
|
|
* See file CREDITS for list of people who contributed to this |
|
|
|
* See file CREDITS for list of people who contributed to this |
|
|
|
* project. |
|
|
|
* project. |
|
|
|
* |
|
|
|
* |
|
|
@ -25,90 +28,84 @@ |
|
|
|
#include <mpc5xxx.h> |
|
|
|
#include <mpc5xxx.h> |
|
|
|
#include <pci.h> |
|
|
|
#include <pci.h> |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
#if defined(CONFIG_MPC5200_DDR) |
|
|
|
|
|
|
|
#include "mt46v16m16-75.h" |
|
|
|
|
|
|
|
#else |
|
|
|
|
|
|
|
#include "mt48lc16m16a2-75.h" |
|
|
|
|
|
|
|
#endif |
|
|
|
|
|
|
|
|
|
|
|
#ifndef CFG_RAMBOOT |
|
|
|
#ifndef CFG_RAMBOOT |
|
|
|
static void sdram_start (int hi_addr) |
|
|
|
static void sdram_start (int hi_addr) |
|
|
|
{ |
|
|
|
{ |
|
|
|
long hi_addr_bit = hi_addr ? 0x01000000 : 0; |
|
|
|
long hi_addr_bit = hi_addr ? 0x01000000 : 0; |
|
|
|
|
|
|
|
|
|
|
|
#ifdef CONFIG_MPC5200_DDR |
|
|
|
|
|
|
|
/* unlock mode register */ |
|
|
|
/* unlock mode register */ |
|
|
|
*(vu_long *)MPC5XXX_SDRAM_CTRL = 0xf05f0f00 | hi_addr_bit; |
|
|
|
*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit; |
|
|
|
|
|
|
|
__asm__ volatile ("sync"); |
|
|
|
|
|
|
|
|
|
|
|
/* precharge all banks */ |
|
|
|
/* precharge all banks */ |
|
|
|
*(vu_long *)MPC5XXX_SDRAM_CTRL = 0xf05f0f02 | hi_addr_bit; |
|
|
|
*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit; |
|
|
|
|
|
|
|
__asm__ volatile ("sync"); |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
#if SDRAM_DDR |
|
|
|
/* set mode register: extended mode */ |
|
|
|
/* set mode register: extended mode */ |
|
|
|
*(vu_long *)MPC5XXX_SDRAM_MODE = 0x40090000; |
|
|
|
*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE; |
|
|
|
|
|
|
|
__asm__ volatile ("sync"); |
|
|
|
|
|
|
|
|
|
|
|
/* set mode register: reset DLL */ |
|
|
|
/* set mode register: reset DLL */ |
|
|
|
*(vu_long *)MPC5XXX_SDRAM_MODE = 0x058d0000; |
|
|
|
*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000; |
|
|
|
/* precharge all banks */ |
|
|
|
__asm__ volatile ("sync"); |
|
|
|
*(vu_long *)MPC5XXX_SDRAM_CTRL = 0xf05f0f02 | hi_addr_bit; |
|
|
|
|
|
|
|
/* auto refresh */ |
|
|
|
|
|
|
|
*(vu_long *)MPC5XXX_SDRAM_CTRL = 0xf05f0f04 | hi_addr_bit; |
|
|
|
|
|
|
|
/* set mode register */ |
|
|
|
|
|
|
|
*(vu_long *)MPC5XXX_SDRAM_MODE = 0x018d0000; |
|
|
|
|
|
|
|
/* normal operation */ |
|
|
|
|
|
|
|
*(vu_long *)MPC5XXX_SDRAM_CTRL = 0x705f0f00 | hi_addr_bit; |
|
|
|
|
|
|
|
#else |
|
|
|
|
|
|
|
/* unlock mode register */ |
|
|
|
|
|
|
|
*(vu_long *)MPC5XXX_SDRAM_CTRL = 0xd04f0000 | hi_addr_bit; |
|
|
|
|
|
|
|
/* precharge all banks */ |
|
|
|
|
|
|
|
*(vu_long *)MPC5XXX_SDRAM_CTRL = 0xd04f0002 | hi_addr_bit; |
|
|
|
|
|
|
|
/* set mode register */ |
|
|
|
|
|
|
|
#if defined(CONFIG_MPC5200) |
|
|
|
|
|
|
|
*(vu_long *)MPC5XXX_SDRAM_MODE = 0x00cd0000; |
|
|
|
|
|
|
|
#elif defined(CONFIG_MGT5100) |
|
|
|
|
|
|
|
*(vu_long *)MPC5XXX_SDRAM_MODE = 0x008d0000; |
|
|
|
|
|
|
|
#endif |
|
|
|
#endif |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
/* precharge all banks */ |
|
|
|
|
|
|
|
*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit; |
|
|
|
|
|
|
|
__asm__ volatile ("sync"); |
|
|
|
|
|
|
|
|
|
|
|
/* auto refresh */ |
|
|
|
/* auto refresh */ |
|
|
|
*(vu_long *)MPC5XXX_SDRAM_CTRL = 0xd04f0004 | hi_addr_bit; |
|
|
|
*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit; |
|
|
|
/* auto refresh */ |
|
|
|
__asm__ volatile ("sync"); |
|
|
|
*(vu_long *)MPC5XXX_SDRAM_CTRL = 0xd04f0004 | hi_addr_bit; |
|
|
|
|
|
|
|
/* set mode register */ |
|
|
|
/* set mode register */ |
|
|
|
*(vu_long *)MPC5XXX_SDRAM_MODE = 0x00cd0000; |
|
|
|
*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE; |
|
|
|
|
|
|
|
__asm__ volatile ("sync"); |
|
|
|
|
|
|
|
|
|
|
|
/* normal operation */ |
|
|
|
/* normal operation */ |
|
|
|
*(vu_long *)MPC5XXX_SDRAM_CTRL = 0x504f0000 | hi_addr_bit; |
|
|
|
*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit; |
|
|
|
#endif |
|
|
|
__asm__ volatile ("sync"); |
|
|
|
} |
|
|
|
} |
|
|
|
#endif |
|
|
|
#endif |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
|
|
|
* ATTENTION: Although partially referenced initdram does NOT make real use |
|
|
|
|
|
|
|
* use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE |
|
|
|
|
|
|
|
* is something else than 0x00000000. |
|
|
|
|
|
|
|
*/ |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
#if defined(CONFIG_MPC5200) |
|
|
|
long int initdram (int board_type) |
|
|
|
long int initdram (int board_type) |
|
|
|
{ |
|
|
|
{ |
|
|
|
ulong dramsize = 0; |
|
|
|
ulong dramsize = 0; |
|
|
|
#ifdef CONFIG_MPC5200_DDR |
|
|
|
|
|
|
|
ulong dramsize2 = 0; |
|
|
|
ulong dramsize2 = 0; |
|
|
|
#endif |
|
|
|
|
|
|
|
#ifndef CFG_RAMBOOT |
|
|
|
#ifndef CFG_RAMBOOT |
|
|
|
ulong test1, test2; |
|
|
|
ulong test1, test2; |
|
|
|
|
|
|
|
|
|
|
|
/* configure SDRAM start/end */ |
|
|
|
/* setup SDRAM chip selects */ |
|
|
|
#if defined(CONFIG_MPC5200) |
|
|
|
|
|
|
|
*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e;/* 2G at 0x0 */ |
|
|
|
*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e;/* 2G at 0x0 */ |
|
|
|
*(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000;/* disabled */ |
|
|
|
*(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000;/* disabled */ |
|
|
|
|
|
|
|
__asm__ volatile ("sync"); |
|
|
|
|
|
|
|
|
|
|
|
#ifdef CONFIG_MPC5200_DDR |
|
|
|
|
|
|
|
/* setup config registers */ |
|
|
|
/* setup config registers */ |
|
|
|
*(vu_long *)MPC5XXX_SDRAM_CONFIG1 = 0x73722930; |
|
|
|
*(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1; |
|
|
|
*(vu_long *)MPC5XXX_SDRAM_CONFIG2 = 0x47770000; |
|
|
|
*(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2; |
|
|
|
|
|
|
|
__asm__ volatile ("sync"); |
|
|
|
|
|
|
|
|
|
|
|
/* set tap delay to 0x10 */ |
|
|
|
#if SDRAM_DDR |
|
|
|
*(vu_long *)MPC5XXX_CDM_PORCFG = 0x10000000; |
|
|
|
/* set tap delay */ |
|
|
|
#else |
|
|
|
*(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY; |
|
|
|
/* setup config registers */ |
|
|
|
__asm__ volatile ("sync"); |
|
|
|
*(vu_long *)MPC5XXX_SDRAM_CONFIG1 = 0xd2322800; |
|
|
|
|
|
|
|
*(vu_long *)MPC5XXX_SDRAM_CONFIG2 = 0x8ad70000; |
|
|
|
|
|
|
|
#endif |
|
|
|
#endif |
|
|
|
|
|
|
|
|
|
|
|
#elif defined(CONFIG_MGT5100) |
|
|
|
/* find RAM size using SDRAM CS0 only */ |
|
|
|
*(vu_long *)MPC5XXX_SDRAM_START = 0x00000000; |
|
|
|
|
|
|
|
*(vu_long *)MPC5XXX_SDRAM_STOP = 0x0000ffff;/* 2G */ |
|
|
|
|
|
|
|
*(vu_long *)MPC5XXX_ADDECR |= (1 << 22); /* Enable SDRAM */ |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
/* setup config registers */ |
|
|
|
|
|
|
|
*(vu_long *)MPC5XXX_SDRAM_CONFIG1 = 0xc2222600; |
|
|
|
|
|
|
|
*(vu_long *)MPC5XXX_SDRAM_CONFIG2 = 0x88b70004; |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
/* address select register */ |
|
|
|
|
|
|
|
*(vu_long *)MPC5XXX_SDRAM_XLBSEL = 0x03000000; |
|
|
|
|
|
|
|
#endif |
|
|
|
|
|
|
|
sdram_start(0); |
|
|
|
sdram_start(0); |
|
|
|
test1 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000); |
|
|
|
test1 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000); |
|
|
|
sdram_start(1); |
|
|
|
sdram_start(1); |
|
|
@ -119,11 +116,24 @@ long int initdram (int board_type) |
|
|
|
} else { |
|
|
|
} else { |
|
|
|
dramsize = test2; |
|
|
|
dramsize = test2; |
|
|
|
} |
|
|
|
} |
|
|
|
#if defined(CONFIG_MPC5200) |
|
|
|
|
|
|
|
*(vu_long *)MPC5XXX_SDRAM_CS0CFG = |
|
|
|
/* memory smaller than 1MB is impossible */ |
|
|
|
(0x13 + __builtin_ffs(dramsize >> 20) - 1); |
|
|
|
if (dramsize < (1 << 20)) { |
|
|
|
#ifdef CONFIG_MPC5200_DDR |
|
|
|
dramsize = 0; |
|
|
|
|
|
|
|
} |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
/* set SDRAM CS0 size according to the amount of RAM found */ |
|
|
|
|
|
|
|
if (dramsize > 0) { |
|
|
|
|
|
|
|
*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1; |
|
|
|
|
|
|
|
} else { |
|
|
|
|
|
|
|
*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */ |
|
|
|
|
|
|
|
} |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
/* let SDRAM CS1 start right after CS0 */ |
|
|
|
*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */ |
|
|
|
*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */ |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
/* find RAM size using SDRAM CS1 only */ |
|
|
|
sdram_start(0); |
|
|
|
sdram_start(0); |
|
|
|
test1 = get_ram_size((ulong *)(CFG_SDRAM_BASE + dramsize), 0x80000000); |
|
|
|
test1 = get_ram_size((ulong *)(CFG_SDRAM_BASE + dramsize), 0x80000000); |
|
|
|
sdram_start(1); |
|
|
|
sdram_start(1); |
|
|
@ -134,34 +144,94 @@ long int initdram (int board_type) |
|
|
|
} else { |
|
|
|
} else { |
|
|
|
dramsize2 = test2; |
|
|
|
dramsize2 = test2; |
|
|
|
} |
|
|
|
} |
|
|
|
*(vu_long *)MPC5XXX_SDRAM_CS1CFG = |
|
|
|
|
|
|
|
dramsize + (0x13 + __builtin_ffs(dramsize2 >> 20) - 1); |
|
|
|
/* memory smaller than 1MB is impossible */ |
|
|
|
#else |
|
|
|
if (dramsize2 < (1 << 20)) { |
|
|
|
*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */ |
|
|
|
dramsize2 = 0; |
|
|
|
#endif |
|
|
|
} |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
/* set SDRAM CS1 size according to the amount of RAM found */ |
|
|
|
|
|
|
|
if (dramsize2 > 0) { |
|
|
|
|
|
|
|
*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize |
|
|
|
|
|
|
|
| (0x13 + __builtin_ffs(dramsize2 >> 20) - 1); |
|
|
|
|
|
|
|
} else { |
|
|
|
|
|
|
|
*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */ |
|
|
|
|
|
|
|
} |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
#else /* CFG_RAMBOOT */ |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
/* retrieve size of memory connected to SDRAM CS0 */ |
|
|
|
|
|
|
|
dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF; |
|
|
|
|
|
|
|
if (dramsize >= 0x13) { |
|
|
|
|
|
|
|
dramsize = (1 << (dramsize - 0x13)) << 20; |
|
|
|
|
|
|
|
} else { |
|
|
|
|
|
|
|
dramsize = 0; |
|
|
|
|
|
|
|
} |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
/* retrieve size of memory connected to SDRAM CS1 */ |
|
|
|
|
|
|
|
dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF; |
|
|
|
|
|
|
|
if (dramsize2 >= 0x13) { |
|
|
|
|
|
|
|
dramsize2 = (1 << (dramsize2 - 0x13)) << 20; |
|
|
|
|
|
|
|
} else { |
|
|
|
|
|
|
|
dramsize2 = 0; |
|
|
|
|
|
|
|
} |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
#endif /* CFG_RAMBOOT */ |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
return dramsize + dramsize2; |
|
|
|
|
|
|
|
} |
|
|
|
|
|
|
|
|
|
|
|
#elif defined(CONFIG_MGT5100) |
|
|
|
#elif defined(CONFIG_MGT5100) |
|
|
|
*(vu_long *)MPC5XXX_SDRAM_STOP = ((dramsize - 1) >> 15); |
|
|
|
|
|
|
|
#endif |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
#else /* CFG_RAMBOOT */ |
|
|
|
long int initdram (int board_type) |
|
|
|
#ifdef CONFIG_MGT5100 |
|
|
|
{ |
|
|
|
|
|
|
|
ulong dramsize = 0; |
|
|
|
|
|
|
|
#ifndef CFG_RAMBOOT |
|
|
|
|
|
|
|
ulong test1, test2; |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
/* setup and enable SDRAM chip selects */ |
|
|
|
|
|
|
|
*(vu_long *)MPC5XXX_SDRAM_START = 0x00000000; |
|
|
|
|
|
|
|
*(vu_long *)MPC5XXX_SDRAM_STOP = 0x0000ffff;/* 2G */ |
|
|
|
*(vu_long *)MPC5XXX_ADDECR |= (1 << 22); /* Enable SDRAM */ |
|
|
|
*(vu_long *)MPC5XXX_ADDECR |= (1 << 22); /* Enable SDRAM */ |
|
|
|
|
|
|
|
__asm__ volatile ("sync"); |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
/* setup config registers */ |
|
|
|
|
|
|
|
*(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1; |
|
|
|
|
|
|
|
*(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2; |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
/* address select register */ |
|
|
|
|
|
|
|
*(vu_long *)MPC5XXX_SDRAM_XLBSEL = SDRAM_ADDRSEL; |
|
|
|
|
|
|
|
__asm__ volatile ("sync"); |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
/* find RAM size */ |
|
|
|
|
|
|
|
sdram_start(0); |
|
|
|
|
|
|
|
test1 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000); |
|
|
|
|
|
|
|
sdram_start(1); |
|
|
|
|
|
|
|
test2 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000); |
|
|
|
|
|
|
|
if (test1 > test2) { |
|
|
|
|
|
|
|
sdram_start(0); |
|
|
|
|
|
|
|
dramsize = test1; |
|
|
|
|
|
|
|
} else { |
|
|
|
|
|
|
|
dramsize = test2; |
|
|
|
|
|
|
|
} |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
/* set SDRAM end address according to size */ |
|
|
|
|
|
|
|
*(vu_long *)MPC5XXX_SDRAM_STOP = ((dramsize - 1) >> 15); |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
#else /* CFG_RAMBOOT */ |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
/* Retrieve amount of SDRAM available */ |
|
|
|
dramsize = ((*(vu_long *)MPC5XXX_SDRAM_STOP + 1) << 15); |
|
|
|
dramsize = ((*(vu_long *)MPC5XXX_SDRAM_STOP + 1) << 15); |
|
|
|
#else |
|
|
|
|
|
|
|
dramsize = ((1 << (*(vu_long *)MPC5XXX_SDRAM_CS0CFG - 0x13)) << 20); |
|
|
|
|
|
|
|
#ifdef CONFIG_MPC5200_DDR |
|
|
|
|
|
|
|
dramsize2 = ((1 << (*(vu_long *)MPC5XXX_SDRAM_CS1CFG - 0x13)) << 20); |
|
|
|
|
|
|
|
#endif |
|
|
|
|
|
|
|
#endif |
|
|
|
|
|
|
|
#endif /* CFG_RAMBOOT */ |
|
|
|
#endif /* CFG_RAMBOOT */ |
|
|
|
|
|
|
|
|
|
|
|
#ifdef CONFIG_MPC5200_DDR |
|
|
|
|
|
|
|
dramsize += dramsize2; |
|
|
|
|
|
|
|
#endif |
|
|
|
|
|
|
|
/* return total ram size */ |
|
|
|
|
|
|
|
return dramsize; |
|
|
|
return dramsize; |
|
|
|
} |
|
|
|
} |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
#else |
|
|
|
|
|
|
|
#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined |
|
|
|
|
|
|
|
#endif |
|
|
|
|
|
|
|
|
|
|
|
int checkboard (void) |
|
|
|
int checkboard (void) |
|
|
|
{ |
|
|
|
{ |
|
|
|
#if defined(CONFIG_MPC5200) |
|
|
|
#if defined(CONFIG_MPC5200) |
|
|
|