ARM: rmobile: Add support salvator-x board

Salvator-x is an entry level development board based on
R-Car H3 SoC (R8A7795). This commit supports SCIF only.

Signed-off-by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>

arch/arm/mach-rmobile/Kconfig.64

@@ -1,12 +1,28 @@
 if RCAR_GEN3
 
+config R8A7795
+	bool
+
 choice
 	prompt "Renesus ARM64 SoCs board select"
 	optional
 
+config TARGET_SALVATOR_X
+	bool "Salvator-X board"
+	select R8A7795
+	help
+          Support for Renesas R-Car Gen3 R8a7795 platform
+
 endchoice
 
 config SYS_SOC
 	default "rmobile"
 
+config RCAR_GEN3_EXTRAM_BOOT
+	bool "Enable boot from RAM"
+	depends on TARGET_SALVATOR_X
+	default n
+
+source "board/renesas/salvator-x/Kconfig"
+
 endif

board/renesas/salvator-x/Kconfig

@@ -0,0 +1,15 @@
+if TARGET_SALVATOR_X
+
+config SYS_SOC
+	default "rmobile"
+
+config SYS_BOARD
+	default "salvator-x"
+
+config SYS_VENDOR
+	default "renesas"
+
+config SYS_CONFIG_NAME
+	default "salvator-x"
+
+endif

board/renesas/salvator-x/MAINTAINERS

@@ -0,0 +1,6 @@
+SALVATOR_X BOARD
+M:	Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+S:	Maintained
+F:	board/renesas/salvator-x/
+F:	include/configs/salvator-x.h
+F:	configs/salvator-x_defconfig

board/renesas/salvator-x/Makefile

@@ -0,0 +1,9 @@
+#
+# board/renesas/salvator-x/Makefile
+#
+# Copyright (C) 2015 Renesas Electronics Corporation
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y	:= salvator-x.o ../rcar-common/common.o

board/renesas/salvator-x/salvator-x.c

@@ -0,0 +1,120 @@
+/*
+ * board/renesas/salvator-x/salvator-x.c
+ *     This file is Salvator-X board support.
+ *
+ * Copyright (C) 2015 Renesas Electronics Corporation
+ * Copyright (C) 2015 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <netdev.h>
+#include <dm.h>
+#include <dm/platform_data/serial_sh.h>
+#include <asm/processor.h>
+#include <asm/mach-types.h>
+#include <asm/io.h>
+#include <asm/errno.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/rmobile.h>
+#include <asm/arch/rcar-mstp.h>
+#include <i2c.h>
+#include <mmc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define CPGWPCR	0xE6150904
+#define CPGWPR  0xE615090C
+
+#define CLK2MHZ(clk)	(clk / 1000 / 1000)
+void s_init(void)
+{
+	struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE;
+	struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE;
+
+	/* Watchdog init */
+	writel(0xA5A5A500, &rwdt->rwtcsra);
+	writel(0xA5A5A500, &swdt->swtcsra);
+
+	writel(0xA5A50000, CPGWPCR);
+	writel(0xFFFFFFFF, CPGWPR);
+}
+
+#define GSX_MSTP112	(1 << 12)	/* 3DG */
+#define TMU0_MSTP125	(1 << 25)	/* secure */
+#define TMU1_MSTP124	(1 << 24)	/* non-secure */
+#define SCIF2_MSTP310	(1 << 10)	/* SCIF2 */
+
+int board_early_init_f(void)
+{
+	/* TMU0,1 */		/* which use ? */
+	mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125 | TMU1_MSTP124);
+	/* SCIF2 */
+	mstp_clrbits_le32(MSTPSR3, SMSTPCR3, SCIF2_MSTP310);
+
+	return 0;
+}
+
+/* SYSC */
+/* R/- 32 Power status register 2(3DG) */
+#define	SYSC_PWRSR2	0xE6180100
+/* -/W 32 Power resume control register 2 (3DG) */
+#define	SYSC_PWRONCR2	0xE618010C
+
+DECLARE_GLOBAL_DATA_PTR;
+int board_init(void)
+{
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = CONFIG_SYS_TEXT_BASE + 0x50000;
+
+	/* Init PFC controller */
+	r8a7795_pinmux_init();
+
+	/* GSX: force power and clock supply */
+	writel(0x0000001F, SYSC_PWRONCR2);
+	while (readl(SYSC_PWRSR2) != 0x000003E0)
+		mdelay(20);
+
+	mstp_clrbits_le32(MSTPSR1, SMSTPCR1, GSX_MSTP112);
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+
+	return 0;
+}
+
+const struct rmobile_sysinfo sysinfo = {
+	CONFIG_RCAR_BOARD_STRING
+};
+
+#define RST_BASE	0xE6160000
+#define RST_CA57RESCNT	(RST_BASE + 0x40)
+#define RST_CA53RESCNT	(RST_BASE + 0x44)
+#define RST_RSTOUTCR	(RST_BASE + 0x58)
+#define RST_CODE	0xA5A5000F
+
+void reset_cpu(ulong addr)
+{
+	/* only CA57 ? */
+	writel(RST_CODE, RST_CA57RESCNT);
+}
+
+static const struct sh_serial_platdata serial_platdata = {
+	.base = SCIF2_BASE,
+	.type = PORT_SCIF,
+	.clk = 14745600,		/* 0xE10000 */
+	.clk_mode = EXT_CLK,
+};
+
+U_BOOT_DEVICE(salvator_x_scif2) = {
+	.name = "serial_sh",
+	.platdata = &serial_platdata,
+};

configs/salvator-x_defconfig

@@ -0,0 +1,4 @@
+CONFIG_ARM=y
+CONFIG_RCAR_GEN3=y
+CONFIG_TARGET_SALVATOR_X=y
+CONFIG_SPL=y

include/configs/rcar-gen3-common.h

@@ -0,0 +1,105 @@
+/*
+ * include/configs/rcar-gen3-common.h
+ *	This file is R-Car Gen3 common configuration file.
+ *
+ * Copyright (C) 2015 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __RCAR_GEN3_COMMON_H
+#define __RCAR_GEN3_COMMON_H
+
+#include <asm/arch/rmobile.h>
+
+#define CONFIG_CMD_BOOTI
+#define CONFIG_CMD_EDITENV
+#define CONFIG_CMD_SAVEENV
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_DFL
+#define CONFIG_CMD_SDRAM
+#define CONFIG_CMD_RUN
+#define CONFIG_CMD_LOADS
+#define CONFIG_CMD_BOOTZ
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_EXT4
+#define CONFIG_CMD_EXT4_WRITE
+
+#define CONFIG_REMAKE_ELF
+
+/* boot option */
+#define CONFIG_SUPPORT_RAW_INITRD
+
+/* Support File sytems */
+#define CONFIG_FAT_WRITE
+#define CONFIG_DOS_PARTITION
+#define CONFIG_SUPPORT_VFAT
+#define CONFIG_FS_EXT4
+#define CONFIG_EXT4_WRITE
+
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_OF_LIBFDT
+
+#define CONFIG_BAUDRATE		115200
+#define CONFIG_BOOTDELAY	3
+
+#define CONFIG_VERSION_VARIABLE
+#undef	CONFIG_SHOW_BOOT_PROGRESS
+
+#define CONFIG_ARCH_CPU_INIT
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+#define CONFIG_BOARD_EARLY_INIT_F
+
+#define CONFIG_SH_GPIO_PFC
+
+/* console */
+#undef  CONFIG_SYS_CONSOLE_INFO_QUIET
+#undef  CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
+#undef  CONFIG_SYS_CONSOLE_ENV_OVERWRITE
+
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_CBSIZE		256
+#define CONFIG_SYS_PBSIZE		256
+#define CONFIG_SYS_MAXARGS		16
+#define CONFIG_SYS_BARGSIZE		512
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 115200, 38400 }
+
+/* MEMORY */
+#define CONFIG_SYS_TEXT_BASE		0x49000000
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_TEXT_BASE + 0x7fff0)
+
+#define CONFIG_SYS_SDRAM_BASE		(0x48000000)
+#define CONFIG_SYS_SDRAM_SIZE		(1024u * 1024 * 1024 - 0x08000000)
+#define CONFIG_SYS_LOAD_ADDR		(0x48080000)
+#define CONFIG_NR_DRAM_BANKS		1
+
+#define CONFIG_SYS_MONITOR_BASE		0x00000000
+#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)
+#define CONFIG_SYS_MALLOC_LEN		(1 * 1024 * 1024)
+#define CONFIG_SYS_BOOTMAPSZ		(8 * 1024 * 1024)
+
+/* ENV setting */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_ENV_SECT_SIZE	(128 * 1024)
+#define CONFIG_ENV_SIZE		(CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
+
+#define CONFIG_EXTRA_ENV_SETTINGS	\
+	"fdt_high=0xffffffffffffffff\0"	\
+	"initrd_high=0xffffffffffffffff\0"
+
+#define CONFIG_BOOTARGS	\
+	"console=ttySC0,115200 rw root=/dev/nfs "	\
+	"nfsroot=192.168.0.1:/export/rfs ip=192.168.0.20"
+
+#define CONFIG_BOOTCOMMAND	\
+	"tftp 0x48080000 Image; " \
+	"tftp 0x48000000 Image-r8a7795-salvator-x.dtb; " \
+	"booti 0x48080000 - 0x48000000"
+
+#endif	/* __RCAR_GEN3_COMMON_H */

include/configs/salvator-x.h

@@ -0,0 +1,54 @@
+/*
+ * include/configs/salvator-x.h
+ *     This file is Salvator-X board configuration.
+ *
+ * Copyright (C) 2015 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __SALVATOR_X_H
+#define __SALVATOR_X_H
+
+#undef DEBUG
+
+#define CONFIG_RCAR_BOARD_STRING "Salvator-X"
+
+#include "rcar-gen3-common.h"
+
+/* SCIF */
+#define CONFIG_SCIF_CONSOLE
+#define CONFIG_CONS_SCIF2
+#define CONFIG_CONS_INDEX	2
+#define CONFIG_SH_SCIF_CLK_FREQ	CONFIG_SYS_CLK_FREQ
+
+/* [A] Hyper Flash */
+/* use to RPC(SPI Multi I/O Bus Controller) */
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_ENV_IS_NOWHERE
+
+/* Board Clock */
+/* XTAL_CLK : 33.33MHz */
+#define RCAR_XTAL_CLK		33333333u
+#define CONFIG_SYS_CLK_FREQ	RCAR_XTAL_CLK
+/* ch0to2 CPclk, ch3to11 S3D2_PEREclk, ch12to14 S3D2_RTclk */
+/* CPclk 16.66MHz, S3D2 133.33MHz                          */
+#define CONFIG_CP_CLK_FREQ	(CONFIG_SYS_CLK_FREQ / 2)
+#define CONFIG_PLL1_CLK_FREQ	(CONFIG_SYS_CLK_FREQ * 192 / 2)
+#define CONFIG_S3D2_CLK_FREQ	(266666666u/2)
+
+/* Generic Timer Definitions (use in assembler source) */
+#define COUNTER_FREQUENCY	0xFE502A	/* 16.66MHz from CPclk */
+
+/* Generic Interrupt Controller Definitions */
+#define CONFIG_GICV2
+#define GICD_BASE	0xF1010000
+#define GICC_BASE	0xF1020000
+
+/* Module stop status bits */
+/* MFIS, SCIF1 */
+#define CONFIG_SMSTP2_ENA	0x00002040
+/* INTC-AP, IRQC */
+#define CONFIG_SMSTP4_ENA	0x00000180
+
+#endif /* __SALVATOR_X_H */