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@ -158,7 +158,7 @@ _start_440: |
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/*----------------------------------------------------------------+ |
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| Core bug fix. Clear the esr |
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+-----------------------------------------------------------------*/ |
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addi r0,r0,0x0000 |
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li r0,0 |
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mtspr esr,r0 |
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/*----------------------------------------------------------------*/ |
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/* Clear and set up some registers. */ |
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@ -217,17 +217,15 @@ _start_440: |
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| g. FCOM: Normal operation |
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| h. MMUPEI: Record even parity. Normal operation. |
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| i. FFF: Flush only as much data as necessary. |
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| j. TCS: Timebase increments from externally supplied clock |
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| j. TCS: Timebase increments from CPU clock. |
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+-----------------------------------------------------------------*/ |
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addis r0, r0, 0x0000 |
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ori r0, r0, 0x0080 |
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li r0,0 |
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mtspr ccr1, r0 |
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/*----------------------------------------------------------------+ |
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| Reset the timebase. |
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| The previous write to CCR1 sets the timebase source. |
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+-----------------------------------------------------------------*/ |
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addi r0, r0, 0x0000 |
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mtspr tbl, r0 |
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mtspr tbu, r0 |
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#endif |
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