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Merge branch 'rmobile' of git://git.denx.de/u-boot-sh

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master
Tom Rini 7 years ago
parent 0031af9ce7 f7f79b4493
commit f72b96ec8f
9 changed files with 120 additions and 105 deletions
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  1. 4
      arch/arm/dts/r8a7795.dtsi
  2. 4
      arch/arm/dts/r8a7796.dtsi
  3. 39
      board/renesas/salvator-x/salvator-x.c
  4. 35
      board/renesas/ulcb/ulcb.c
  5. 4
      configs/r8a7795_salvator-x_defconfig
  6. 3
      configs/r8a7795_ulcb_defconfig
  7. 4
      configs/r8a7796_salvator-x_defconfig
  8. 3
      configs/r8a7796_ulcb_defconfig
  9. 129
      drivers/clk/renesas/clk-rcar-gen3.c

4
arch/arm/dts/r8a7795.dtsi
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@ -129,6 +129,7 @@
#clock-cells = <0>;
/* This value must be overridden by the board */
clock-frequency = <0>;
u-boot,dm-pre-reloc;
};
extalr_clk: extalr {
@ -136,6 +137,7 @@
#clock-cells = <0>;
/* This value must be overridden by the board */
clock-frequency = <0>;
u-boot,dm-pre-reloc;
};
/*
@ -189,6 +191,7 @@
#address-cells = <2>;
#size-cells = <2>;
ranges;
u-boot,dm-pre-reloc;
gic: interrupt-controller@f1010000 {
compatible = "arm,gic-400";
@ -380,6 +383,7 @@
#clock-cells = <2>;
#power-domain-cells = <0>;
#reset-cells = <1>;
u-boot,dm-pre-reloc;
};
rst: reset-controller@e6160000 {

4
arch/arm/dts/r8a7796.dtsi
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@ -111,6 +111,7 @@
#clock-cells = <0>;
/* This value must be overridden by the board */
clock-frequency = <0>;
u-boot,dm-pre-reloc;
};
extalr_clk: extalr {
@ -118,6 +119,7 @@
#clock-cells = <0>;
/* This value must be overridden by the board */
clock-frequency = <0>;
u-boot,dm-pre-reloc;
};
/* External CAN clock - to be overridden by boards that provide it */
@ -140,6 +142,7 @@
#address-cells = <2>;
#size-cells = <2>;
ranges;
u-boot,dm-pre-reloc;
gic: interrupt-controller@f1010000 {
compatible = "arm,gic-400";
@ -333,6 +336,7 @@
#clock-cells = <2>;
#power-domain-cells = <0>;
#reset-cells = <1>;
u-boot,dm-pre-reloc;
};
rst: reset-controller@e6160000 {

39
board/renesas/salvator-x/salvator-x.c
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@ -161,22 +161,9 @@ int board_init(void)
return 0;
}
static struct eth_pdata salvator_x_ravb_platdata = {
.iobase = 0xE6800000,
.phy_interface = 0,
.max_speed = 1000,
};
U_BOOT_DEVICE(salvator_x_ravb) = {
.name = "ravb",
.platdata = &salvator_x_ravb_platdata,
};
#ifdef CONFIG_SH_SDHI
int board_mmc_init(bd_t *bis)
{
int ret = -ENODEV;
/* SDHI0 */
gpio_request(GPIO_GFN_SD0_DAT0, NULL);
gpio_request(GPIO_GFN_SD0_DAT1, NULL);
@ -192,11 +179,6 @@ int board_mmc_init(bd_t *bis)
gpio_direction_output(GPIO_GP_5_2, 1); /* power on */
gpio_direction_output(GPIO_GP_5_1, 1); /* 1: 3.3V, 0: 1.8V */
ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI0_BASE, 0,
SH_SDHI_QUIRK_64BIT_BUF);
if (ret)
return ret;
/* SDHI1/SDHI2 eMMC */
gpio_request(GPIO_GFN_SD1_DAT0, NULL);
gpio_request(GPIO_GFN_SD1_DAT1, NULL);
@ -219,11 +201,6 @@ int board_mmc_init(bd_t *bis)
gpio_direction_output(GPIO_GP_5_3, 0); /* 1: 3.3V, 0: 1.8V */
gpio_direction_output(GPIO_GP_5_9, 0); /* 1: 3.3V, 0: 1.8V */
ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI2_BASE, 1,
SH_SDHI_QUIRK_64BIT_BUF);
if (ret)
return ret;
#if defined(CONFIG_R8A7795)
/* SDHI3 */
gpio_request(GPIO_GFN_SD3_DAT0, NULL); /* GP_4_9 */
@ -251,9 +228,7 @@ int board_mmc_init(bd_t *bis)
gpio_direction_output(GPIO_GP_3_15, 1); /* power on */
gpio_direction_output(GPIO_GP_3_14, 1); /* 1: 3.3V, 0: 1.8V */
ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI3_BASE, 2,
SH_SDHI_QUIRK_64BIT_BUF);
return ret;
return 0;
}
#endif
@ -311,15 +286,3 @@ void reset_cpu(ulong addr)
writel(RST_CODE, RST_CA57RESCNT);
#endif
}
static const struct sh_serial_platdata serial_platdata = {
.base = SCIF2_BASE,
.type = PORT_SCIF,
.clk = CONFIG_SH_SCIF_CLK_FREQ,
.clk_mode = INT_CLK,
};
U_BOOT_DEVICE(salvator_x_scif2) = {
.name = "serial_sh",
.platdata = &serial_platdata,
};

35
board/renesas/ulcb/ulcb.c
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@ -140,22 +140,9 @@ int board_init(void)
return 0;
}
static struct eth_pdata salvator_x_ravb_platdata = {
.iobase = 0xE6800000,
.phy_interface = 0,
.max_speed = 1000,
};
U_BOOT_DEVICE(salvator_x_ravb) = {
.name = "ravb",
.platdata = &salvator_x_ravb_platdata,
};
#ifdef CONFIG_SH_SDHI
int board_mmc_init(bd_t *bis)
{
int ret = -ENODEV;
/* SDHI0 */
gpio_request(GPIO_GFN_SD0_DAT0, NULL);
gpio_request(GPIO_GFN_SD0_DAT1, NULL);
@ -171,11 +158,6 @@ int board_mmc_init(bd_t *bis)
gpio_direction_output(GPIO_GP_5_2, 1); /* power on */
gpio_direction_output(GPIO_GP_5_1, 1); /* 1: 3.3V, 0: 1.8V */
ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI0_BASE, 0,
SH_SDHI_QUIRK_64BIT_BUF);
if (ret)
return ret;
/* SDHI1/SDHI2 eMMC */
gpio_request(GPIO_GFN_SD1_DAT0, NULL);
gpio_request(GPIO_GFN_SD1_DAT1, NULL);
@ -198,10 +180,7 @@ int board_mmc_init(bd_t *bis)
gpio_direction_output(GPIO_GP_5_3, 0); /* 1: 3.3V, 0: 1.8V */
gpio_direction_output(GPIO_GP_5_9, 0); /* 1: 3.3V, 0: 1.8V */
ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI2_BASE, 1,
SH_SDHI_QUIRK_64BIT_BUF);
return ret;
return 0;
}
#endif
@ -243,15 +222,3 @@ int dram_init_banksize(void)
const struct rmobile_sysinfo sysinfo = {
CONFIG_RCAR_BOARD_STRING
};
static const struct sh_serial_platdata serial_platdata = {
.base = SCIF2_BASE,
.type = PORT_SCIF,
.clk = CONFIG_SH_SCIF_CLK_FREQ,
.clk_mode = INT_CLK,
};
U_BOOT_DEVICE(salvator_x_scif2) = {
.name = "serial_sh",
.platdata = &serial_platdata,
};

4
configs/r8a7795_salvator-x_defconfig
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@ -10,6 +10,7 @@ CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttySC0,115200 rw root=/dev/nfs nfsroot=192.168.0.1:/export/rfs ip=192.168.0.20"
CONFIG_DEFAULT_FDT_FILE="r8a7795-salvator-x.dtb"
CONFIG_VERSION_VARIABLE=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_MMC=y
@ -22,12 +23,15 @@ CONFIG_CMD_FAT=y
CONFIG_OF_CONTROL=y
CONFIG_CLK=y
CONFIG_CLK_RENESAS=y
CONFIG_DM_MMC=y
CONFIG_SH_SDHI=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_DM_ETH=y
CONFIG_RENESAS_RAVB=y
CONFIG_SCIF_CONSOLE=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_SMBIOS_MANUFACTURER=""

3
configs/r8a7795_ulcb_defconfig
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@ -9,6 +9,7 @@ CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttySC0,115200 rw root=/dev/nfs nfsroot=192.168.0.1:/export/rfs ip=192.168.0.20"
CONFIG_DEFAULT_FDT_FILE="r8a7795-h3ulcb.dtb"
CONFIG_VERSION_VARIABLE=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_MMC=y
@ -20,11 +21,13 @@ CONFIG_OF_CONTROL=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_CLK=y
CONFIG_CLK_RENESAS=y
CONFIG_DM_MMC=y
CONFIG_SH_SDHI=y
CONFIG_DM_ETH=y
CONFIG_RENESAS_RAVB=y
CONFIG_SCIF_CONSOLE=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_SMBIOS_MANUFACTURER=""

4
configs/r8a7796_salvator-x_defconfig
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@ -11,6 +11,7 @@ CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttySC0,115200 rw root=/dev/nfs nfsroot=192.168.0.1:/export/rfs ip=192.168.0.20"
CONFIG_DEFAULT_FDT_FILE="r8a7796-salvator-x.dtb"
CONFIG_VERSION_VARIABLE=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_MMC=y
@ -23,12 +24,15 @@ CONFIG_CMD_FAT=y
CONFIG_OF_CONTROL=y
CONFIG_CLK=y
CONFIG_CLK_RENESAS=y
CONFIG_DM_MMC=y
CONFIG_SH_SDHI=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_DM_ETH=y
CONFIG_RENESAS_RAVB=y
CONFIG_SCIF_CONSOLE=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_SMBIOS_MANUFACTURER=""

3
configs/r8a7796_ulcb_defconfig
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@ -10,6 +10,7 @@ CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttySC0,115200 rw root=/dev/nfs nfsroot=192.168.0.1:/export/rfs ip=192.168.0.20"
CONFIG_DEFAULT_FDT_FILE="r8a7796-m3ulcb.dtb"
CONFIG_VERSION_VARIABLE=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_MMC=y
@ -21,11 +22,13 @@ CONFIG_OF_CONTROL=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_CLK=y
CONFIG_CLK_RENESAS=y
CONFIG_DM_MMC=y
CONFIG_SH_SDHI=y
CONFIG_DM_ETH=y
CONFIG_RENESAS_RAVB=y
CONFIG_SCIF_CONSOLE=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_SMBIOS_MANUFACTURER=""

129
drivers/clk/renesas/clk-rcar-gen3.c
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@ -73,6 +73,8 @@ struct gen3_clk_priv {
struct clk clk_extal;
struct clk clk_extalr;
const struct rcar_gen3_cpg_pll_config *cpg_pll_config;
const struct cpg_core_clk *core_clk;
u32 core_clk_size;
const struct mssr_mod_clk *mod_clk;
u32 mod_clk_size;
};
@ -181,7 +183,7 @@ enum clk_ids {
MOD_CLK_BASE
};
static const struct cpg_core_clk gen3_core_clks[] = {
static const struct cpg_core_clk r8a7795_core_clks[] = {
/* External Clock Inputs */
DEF_INPUT("extal", CLK_EXTAL),
DEF_INPUT("extalr", CLK_EXTALR),
@ -203,38 +205,38 @@ static const struct cpg_core_clk gen3_core_clks[] = {
DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1),
/* Core Clock Outputs */
DEF_FIXED("ztr", R8A7796_CLK_ZTR, CLK_PLL1_DIV2, 6, 1),
DEF_FIXED("ztrd2", R8A7796_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
DEF_FIXED("zt", R8A7796_CLK_ZT, CLK_PLL1_DIV2, 4, 1),
DEF_FIXED("zx", R8A7796_CLK_ZX, CLK_PLL1_DIV2, 2, 1),
DEF_FIXED("s0d1", R8A7796_CLK_S0D1, CLK_S0, 1, 1),
DEF_FIXED("s0d2", R8A7796_CLK_S0D2, CLK_S0, 2, 1),
DEF_FIXED("s0d3", R8A7796_CLK_S0D3, CLK_S0, 3, 1),
DEF_FIXED("s0d4", R8A7796_CLK_S0D4, CLK_S0, 4, 1),
DEF_FIXED("s0d6", R8A7796_CLK_S0D6, CLK_S0, 6, 1),
DEF_FIXED("s0d8", R8A7796_CLK_S0D8, CLK_S0, 8, 1),
DEF_FIXED("s0d12", R8A7796_CLK_S0D12, CLK_S0, 12, 1),
DEF_FIXED("s1d1", R8A7796_CLK_S1D1, CLK_S1, 1, 1),
DEF_FIXED("s1d2", R8A7796_CLK_S1D2, CLK_S1, 2, 1),
DEF_FIXED("s1d4", R8A7796_CLK_S1D4, CLK_S1, 4, 1),
DEF_FIXED("s2d1", R8A7796_CLK_S2D1, CLK_S2, 1, 1),
DEF_FIXED("s2d2", R8A7796_CLK_S2D2, CLK_S2, 2, 1),
DEF_FIXED("s2d4", R8A7796_CLK_S2D4, CLK_S2, 4, 1),
DEF_FIXED("s3d1", R8A7796_CLK_S3D1, CLK_S3, 1, 1),
DEF_FIXED("s3d2", R8A7796_CLK_S3D2, CLK_S3, 2, 1),
DEF_FIXED("s3d4", R8A7796_CLK_S3D4, CLK_S3, 4, 1),
DEF_GEN3_SD("sd0", R8A7796_CLK_SD0, CLK_SDSRC, 0x074),
DEF_GEN3_SD("sd1", R8A7796_CLK_SD1, CLK_SDSRC, 0x078),
DEF_GEN3_SD("sd2", R8A7796_CLK_SD2, CLK_SDSRC, 0x268),
DEF_GEN3_SD("sd3", R8A7796_CLK_SD3, CLK_SDSRC, 0x26c),
DEF_FIXED("cl", R8A7796_CLK_CL, CLK_PLL1_DIV2, 48, 1),
DEF_FIXED("cp", R8A7796_CLK_CP, CLK_EXTAL, 2, 1),
DEF_FIXED("ztr", R8A7795_CLK_ZTR, CLK_PLL1_DIV2, 6, 1),
DEF_FIXED("ztrd2", R8A7795_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
DEF_FIXED("zt", R8A7795_CLK_ZT, CLK_PLL1_DIV2, 4, 1),
DEF_FIXED("zx", R8A7795_CLK_ZX, CLK_PLL1_DIV2, 2, 1),
DEF_FIXED("s0d1", R8A7795_CLK_S0D1, CLK_S0, 1, 1),
DEF_FIXED("s0d2", R8A7795_CLK_S0D2, CLK_S0, 2, 1),
DEF_FIXED("s0d3", R8A7795_CLK_S0D3, CLK_S0, 3, 1),
DEF_FIXED("s0d4", R8A7795_CLK_S0D4, CLK_S0, 4, 1),
DEF_FIXED("s0d6", R8A7795_CLK_S0D6, CLK_S0, 6, 1),
DEF_FIXED("s0d8", R8A7795_CLK_S0D8, CLK_S0, 8, 1),
DEF_FIXED("s0d12", R8A7795_CLK_S0D12, CLK_S0, 12, 1),
DEF_FIXED("s1d1", R8A7795_CLK_S1D1, CLK_S1, 1, 1),
DEF_FIXED("s1d2", R8A7795_CLK_S1D2, CLK_S1, 2, 1),
DEF_FIXED("s1d4", R8A7795_CLK_S1D4, CLK_S1, 4, 1),
DEF_FIXED("s2d1", R8A7795_CLK_S2D1, CLK_S2, 1, 1),
DEF_FIXED("s2d2", R8A7795_CLK_S2D2, CLK_S2, 2, 1),
DEF_FIXED("s2d4", R8A7795_CLK_S2D4, CLK_S2, 4, 1),
DEF_FIXED("s3d1", R8A7795_CLK_S3D1, CLK_S3, 1, 1),
DEF_FIXED("s3d2", R8A7795_CLK_S3D2, CLK_S3, 2, 1),
DEF_FIXED("s3d4", R8A7795_CLK_S3D4, CLK_S3, 4, 1),
DEF_GEN3_SD("sd0", R8A7795_CLK_SD0, CLK_SDSRC, 0x074),
DEF_GEN3_SD("sd1", R8A7795_CLK_SD1, CLK_SDSRC, 0x078),
DEF_GEN3_SD("sd2", R8A7795_CLK_SD2, CLK_SDSRC, 0x268),
DEF_GEN3_SD("sd3", R8A7795_CLK_SD3, CLK_SDSRC, 0x26c),
DEF_FIXED("cl", R8A7795_CLK_CL, CLK_PLL1_DIV2, 48, 1),
DEF_FIXED("cp", R8A7795_CLK_CP, CLK_EXTAL, 2, 1),
/* NOTE: HDMI, CSI, CAN etc. clock are missing */
DEF_BASE("r", R8A7796_CLK_R, CLK_TYPE_GEN3_R, CLK_RINT),
DEF_BASE("r", R8A7795_CLK_R, CLK_TYPE_GEN3_R, CLK_RINT),
};
static const struct mssr_mod_clk r8a7795_mod_clks[] = {
@ -392,6 +394,62 @@ static const struct mssr_mod_clk r8a7795_mod_clks[] = {
DEF_MOD("scu-src0", 1031, MOD_CLK_ID(1017)),
};
static const struct cpg_core_clk r8a7796_core_clks[] = {
/* External Clock Inputs */
DEF_INPUT("extal", CLK_EXTAL),
DEF_INPUT("extalr", CLK_EXTALR),
/* Internal Core Clocks */
DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL),
DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN3_PLL0, CLK_MAIN),
DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN),
DEF_BASE(".pll2", CLK_PLL2, CLK_TYPE_GEN3_PLL2, CLK_MAIN),
DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN),
DEF_BASE(".pll4", CLK_PLL4, CLK_TYPE_GEN3_PLL4, CLK_MAIN),
DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
DEF_FIXED(".pll1_div4", CLK_PLL1_DIV4, CLK_PLL1_DIV2, 2, 1),
DEF_FIXED(".s0", CLK_S0, CLK_PLL1_DIV2, 2, 1),
DEF_FIXED(".s1", CLK_S1, CLK_PLL1_DIV2, 3, 1),
DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 4, 1),
DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1),
DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1),
/* Core Clock Outputs */
DEF_FIXED("ztr", R8A7796_CLK_ZTR, CLK_PLL1_DIV2, 6, 1),
DEF_FIXED("ztrd2", R8A7796_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
DEF_FIXED("zt", R8A7796_CLK_ZT, CLK_PLL1_DIV2, 4, 1),
DEF_FIXED("zx", R8A7796_CLK_ZX, CLK_PLL1_DIV2, 2, 1),
DEF_FIXED("s0d1", R8A7796_CLK_S0D1, CLK_S0, 1, 1),
DEF_FIXED("s0d2", R8A7796_CLK_S0D2, CLK_S0, 2, 1),
DEF_FIXED("s0d3", R8A7796_CLK_S0D3, CLK_S0, 3, 1),
DEF_FIXED("s0d4", R8A7796_CLK_S0D4, CLK_S0, 4, 1),
DEF_FIXED("s0d6", R8A7796_CLK_S0D6, CLK_S0, 6, 1),
DEF_FIXED("s0d8", R8A7796_CLK_S0D8, CLK_S0, 8, 1),
DEF_FIXED("s0d12", R8A7796_CLK_S0D12, CLK_S0, 12, 1),
DEF_FIXED("s1d1", R8A7796_CLK_S1D1, CLK_S1, 1, 1),
DEF_FIXED("s1d2", R8A7796_CLK_S1D2, CLK_S1, 2, 1),
DEF_FIXED("s1d4", R8A7796_CLK_S1D4, CLK_S1, 4, 1),
DEF_FIXED("s2d1", R8A7796_CLK_S2D1, CLK_S2, 1, 1),
DEF_FIXED("s2d2", R8A7796_CLK_S2D2, CLK_S2, 2, 1),
DEF_FIXED("s2d4", R8A7796_CLK_S2D4, CLK_S2, 4, 1),
DEF_FIXED("s3d1", R8A7796_CLK_S3D1, CLK_S3, 1, 1),
DEF_FIXED("s3d2", R8A7796_CLK_S3D2, CLK_S3, 2, 1),
DEF_FIXED("s3d4", R8A7796_CLK_S3D4, CLK_S3, 4, 1),
DEF_GEN3_SD("sd0", R8A7796_CLK_SD0, CLK_SDSRC, 0x074),
DEF_GEN3_SD("sd1", R8A7796_CLK_SD1, CLK_SDSRC, 0x078),
DEF_GEN3_SD("sd2", R8A7796_CLK_SD2, CLK_SDSRC, 0x268),
DEF_GEN3_SD("sd3", R8A7796_CLK_SD3, CLK_SDSRC, 0x26c),
DEF_FIXED("cl", R8A7796_CLK_CL, CLK_PLL1_DIV2, 48, 1),
DEF_FIXED("cp", R8A7796_CLK_CP, CLK_EXTAL, 2, 1),
/* NOTE: HDMI, CSI, CAN etc. clock are missing */
DEF_BASE("r", R8A7796_CLK_R, CLK_TYPE_GEN3_R, CLK_RINT),
};
static const struct mssr_mod_clk r8a7796_mod_clks[] = {
DEF_MOD("scif5", 202, R8A7796_CLK_S3D4),
DEF_MOD("scif4", 203, R8A7796_CLK_S3D4),
@ -648,17 +706,18 @@ static int gen3_clk_get_mod(struct clk *clk, const struct mssr_mod_clk **mssr)
static int gen3_clk_get_core(struct clk *clk, const struct cpg_core_clk **core)
{
struct gen3_clk_priv *priv = dev_get_priv(clk->dev);
const unsigned long clkid = clk->id & 0xffff;
int i;
if (gen3_clk_is_mod(clk))
return -EINVAL;
for (i = 0; i < ARRAY_SIZE(gen3_core_clks); i++) {
if (gen3_core_clks[i].id != clkid)
for (i = 0; i < priv->core_clk_size; i++) {
if (priv->core_clk[i].id != clkid)
continue;
*core = &gen3_core_clks[i];
*core = &priv->core_clk[i];
return 0;
}
@ -895,6 +954,8 @@ static int gen3_clk_probe(struct udevice *dev)
switch (model) {
case CLK_R8A7795:
priv->core_clk = r8a7795_core_clks;
priv->core_clk_size = ARRAY_SIZE(r8a7795_core_clks);
priv->mod_clk = r8a7795_mod_clks;
priv->mod_clk_size = ARRAY_SIZE(r8a7795_mod_clks);
ret = fdt_node_offset_by_compatible(gd->fdt_blob, -1,
@ -903,6 +964,8 @@ static int gen3_clk_probe(struct udevice *dev)
return ret;
break;
case CLK_R8A7796:
priv->core_clk = r8a7796_core_clks;
priv->core_clk_size = ARRAY_SIZE(r8a7796_core_clks);
priv->mod_clk = r8a7796_mod_clks;
priv->mod_clk_size = ARRAY_SIZE(r8a7796_mod_clks);
ret = fdt_node_offset_by_compatible(gd->fdt_blob, -1,

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