Kumar Gala
20 years ago
commit
f8edca2e9a
@ -0,0 +1,24 @@ |
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#
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# (C) Copyright 2000-2002
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
|
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# published by the Free Software Foundation; either version 2 of
|
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# the License, or (at your option) any later version.
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#
|
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# This program is distributed in the hope that it will be useful,
|
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
|
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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PLATFORM_CPPFLAGS += -DCONFIG_BLACKFIN -D__blackfin__
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@ -0,0 +1,117 @@ |
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/*
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* (C) Copyright 2006 DENX Software Engineering |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#include <common.h> |
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#if (CONFIG_COMMANDS & CFG_CMD_NAND) |
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#include <nand.h> |
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/*
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* hardware specific access to control-lines |
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* function borrowed from Linux 2.6 (drivers/mtd/nand/ppchameleonevb.c) |
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*/ |
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static void ppchameleonevb_hwcontrol(struct mtd_info *mtdinfo, int cmd) |
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{ |
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struct nand_chip *this = mtdinfo->priv; |
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ulong base = (ulong) this->IO_ADDR_W; |
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switch(cmd) { |
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case NAND_CTL_SETCLE: |
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MACRO_NAND_CTL_SETCLE((unsigned long)base); |
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break; |
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case NAND_CTL_CLRCLE: |
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MACRO_NAND_CTL_CLRCLE((unsigned long)base); |
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break; |
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case NAND_CTL_SETALE: |
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MACRO_NAND_CTL_SETALE((unsigned long)base); |
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break; |
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case NAND_CTL_CLRALE: |
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MACRO_NAND_CTL_CLRALE((unsigned long)base); |
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break; |
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case NAND_CTL_SETNCE: |
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MACRO_NAND_ENABLE_CE((unsigned long)base); |
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break; |
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case NAND_CTL_CLRNCE: |
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MACRO_NAND_DISABLE_CE((unsigned long)base); |
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break; |
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} |
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} |
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/*
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* read device ready pin |
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* function +/- borrowed from Linux 2.6 (drivers/mtd/nand/ppchameleonevb.c) |
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*/ |
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static int ppchameleonevb_device_ready(struct mtd_info *mtdinfo) |
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{ |
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struct nand_chip *this = mtdinfo->priv; |
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ulong rb_gpio_pin; |
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/* use the base addr to find out which chip are we dealing with */ |
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switch((ulong) this->IO_ADDR_W) { |
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case CFG_NAND0_BASE: |
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rb_gpio_pin = CFG_NAND0_RDY; |
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break; |
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case CFG_NAND1_BASE: |
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rb_gpio_pin = CFG_NAND1_RDY; |
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break; |
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default: /* this should never happen */ |
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return 0; |
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break; |
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} |
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if (in32(GPIO0_IR) & rb_gpio_pin) |
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return 1; |
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return 0; |
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} |
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/*
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* Board-specific NAND initialization. The following members of the |
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* argument are board-specific (per include/linux/mtd/nand.h): |
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* - IO_ADDR_R?: address to read the 8 I/O lines of the flash device |
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* - IO_ADDR_W?: address to write the 8 I/O lines of the flash device |
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* - hwcontrol: hardwarespecific function for accesing control-lines |
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* - dev_ready: hardwarespecific function for accesing device ready/busy line |
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* - enable_hwecc?: function to enable (reset) hardware ecc generator. Must |
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* only be provided if a hardware ECC is available |
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* - eccmode: mode of ecc, see defines |
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* - chip_delay: chip dependent delay for transfering data from array to |
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* read regs (tR) |
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* - options: various chip options. They can partly be set to inform |
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* nand_scan about special functionality. See the defines for further |
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* explanation |
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* Members with a "?" were not set in the merged testing-NAND branch, |
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* so they are not set here either. |
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*/ |
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void board_nand_init(struct nand_chip *nand) |
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{ |
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nand->hwcontrol = ppchameleonevb_hwcontrol; |
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nand->dev_ready = ppchameleonevb_device_ready; |
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nand->eccmode = NAND_ECC_SOFT; |
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nand->chip_delay = NAND_BIG_DELAY_US; |
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nand->options = NAND_SAMSUNG_LP_OPTIONS; |
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} |
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#endif /* (CONFIG_COMMANDS & CFG_CMD_NAND) */ |
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@ -0,0 +1,48 @@ |
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#
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# (C) Copyright 2000
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
|
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# modify it under the terms of the GNU General Public License as
|
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# published by the Free Software Foundation; either version 2 of
|
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
|
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
|
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# along with this program; if not, write to the Free Software
|
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk |
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LIB = lib$(BOARD).a
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OBJS := delta.o nand.o
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SOBJS := lowlevel_init.o
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$(LIB): $(OBJS) $(SOBJS) |
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$(AR) crv $@ $(OBJS) $(SOBJS)
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clean: |
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rm -f $(SOBJS) $(OBJS)
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distclean: clean |
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rm -f $(LIB) core *.bak .depend
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#########################################################################
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.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) |
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$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
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-include .depend |
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#########################################################################
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@ -0,0 +1,8 @@ |
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#TEXT_BASE = 0x0
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#TEXT_BASE = 0xa1700000
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#TEXT_BASE = 0xa3080000
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#TEXT_BASE = 0x9ffe0000
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TEXT_BASE = 0xa3008000
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# Compile the new NAND code (needed iff #ifdef CONFIG_NEW_NAND_CODE)
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BOARDLIBS = drivers/nand/libnand.a
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@ -0,0 +1,75 @@ |
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/*
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* (C) Copyright 2002 |
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* Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net |
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* |
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* (C) Copyright 2002 |
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* Sysgo Real-Time Solutions, GmbH <www.elinos.com> |
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* Marius Groeger <mgroeger@sysgo.de> |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#include <common.h> |
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/* ------------------------------------------------------------------------- */ |
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/*
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* Miscelaneous platform dependent initialisations |
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*/ |
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int board_init (void) |
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{ |
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DECLARE_GLOBAL_DATA_PTR; |
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/* memory and cpu-speed are setup before relocation */ |
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/* so we do _nothing_ here */ |
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/* arch number of Lubbock-Board mk@tbd: fix this! */ |
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gd->bd->bi_arch_number = MACH_TYPE_LUBBOCK; |
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/* adress of boot parameters */ |
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gd->bd->bi_boot_params = 0xa0000100; |
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return 0; |
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} |
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int board_late_init(void) |
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{ |
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setenv("stdout", "serial"); |
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setenv("stderr", "serial"); |
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return 0; |
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} |
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int dram_init (void) |
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{ |
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DECLARE_GLOBAL_DATA_PTR; |
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gd->bd->bi_dram[0].start = PHYS_SDRAM_1; |
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gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; |
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gd->bd->bi_dram[1].start = PHYS_SDRAM_2; |
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gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; |
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gd->bd->bi_dram[2].start = PHYS_SDRAM_3; |
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gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE; |
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gd->bd->bi_dram[3].start = PHYS_SDRAM_4; |
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gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE; |
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return 0; |
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} |
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@ -0,0 +1,385 @@ |
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/* |
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* Most of this taken from Redboot hal_platform_setup.h with cleanup |
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* |
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* NOTE: I haven't clean this up considerably, just enough to get it |
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* running. See hal_platform_setup.h for the source. See |
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* board/cradle/lowlevel_init.S for another PXA250 setup that is |
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* much cleaner. |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or
|
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* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of
|
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
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* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software
|
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#include <config.h> |
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#include <version.h> |
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#include <asm/arch/pxa-regs.h> |
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DRAM_SIZE: .long CFG_DRAM_SIZE |
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/* wait for coprocessor write complete */ |
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.macro CPWAIT reg |
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mrc p15,0,\reg,c2,c0,0 |
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mov \reg,\reg |
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sub pc,pc,#4 |
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.endm |
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.macro wait time |
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ldr r2, =OSCR |
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mov r3, #0 |
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str r3, [r2] |
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0: |
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ldr r3, [r2] |
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cmp r3, \time |
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bls 0b |
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.endm |
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/* |
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* Memory setup |
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*/ |
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.globl lowlevel_init
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lowlevel_init: |
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/* Set up GPIO pins first ----------------------------------------- */ |
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mov r10, lr |
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/* Configure GPIO Pins 97, 98 UART1 / altern. Fkt. 1 */ |
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ldr r0, =GPIO97 |
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ldr r1, =0x801 |
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str r1, [r0] |
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ldr r0, =GPIO98 |
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ldr r1, =0x801 |
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str r1, [r0] |
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/* tebrandt - ASCR, clear the RDH bit */ |
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ldr r0, =ASCR |
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ldr r1, [r0] |
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bic r1, r1, #0x80000000 |
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str r1, [r0] |
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/* ---------------------------------------------------------------- */ |
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/* Enable memory interface */ |
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/* ---------------------------------------------------------------- */ |
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/* ---------------------------------------------------------------- */ |
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/* Step 1: Wait for at least 200 microsedonds to allow internal */ |
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/* clocks to settle. Only necessary after hard reset... */ |
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/* FIXME: can be optimized later */ |
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/* ---------------------------------------------------------------- */ |
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; wait #300
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mem_init: |
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#define NEW_SDRAM_INIT 1 |
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#ifdef NEW_SDRAM_INIT |
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/* Configure ACCR Register - enable DMEMC Clock at 260 / 2 MHz */ |
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ldr r0, =ACCR |
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ldr r1, [r0] |
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orr r1, r1, #0x3000 |
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str r1, [r0] |
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ldr r1, [r0] |
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|
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/* 2. Programm MDCNFG, leaving DMCEN de-asserted */ |
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ldr r0, =MDCNFG |
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ldr r1, =(MDCNFG_DMAP | MDCNFG_DTYPE | MDCNFG_DTC_2 | MDCNFG_DCSE0 | MDCNFG_DRAC_13) |
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/* ldr r1, =0x80000403 */ |
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str r1, [r0] |
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ldr r1, [r0] /* delay until written */ |
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|
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/* 3. wait nop power up waiting period (200ms) |
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* optimization: Steps 4+6 can be done during this |
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*/ |
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wait #300 |
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|
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/* 4. Perform an initial Rcomp-calibration cycle */ |
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ldr r0, =RCOMP |
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ldr r1, =0x80000000 |
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str r1, [r0] |
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ldr r1, [r0] /* delay until written */ |
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/* missing: program for automatic rcomp evaluation cycles */ |
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|
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/* 5. DDR DRAM strobe delay calibration */ |
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ldr r0, =DDR_HCAL |
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ldr r1, =0x88000007 |
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str r1, [r0] |
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wait #5 |
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ldr r1, [r0] /* delay until written */ |
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|
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/* Set MDMRS */ |
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ldr r0, =MDMRS |
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ldr r1, =0x60000033 |
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str r1, [r0] |
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wait #300 |
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|
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/* Configure MDREFR */ |
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ldr r0, =MDREFR |
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ldr r1, =0x00000006 |
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str r1, [r0] |
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ldr r1, [r0] |
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|
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/* Enable the dynamic memory controller */ |
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ldr r0, =MDCNFG |
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ldr r1, [r0] |
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orr r1, r1, #MDCNFG_DMCEN |
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str r1, [r0] |
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|
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|
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#else /* NEW_SDRAM_INIT */ |
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|
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/* configure the MEMCLKCFG register */ |
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ldr r1, =MEMCLKCFG |
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ldr r2, =0x00010001 |
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str r2, [r1] @ WRITE
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ldr r2, [r1] @ DELAY UNTIL WRITTEN
|
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|
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/* set CSADRCFG[0] to data flash SRAM mode */ |
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ldr r1, =CSADRCFG0 |
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ldr r2, =0x00320809 |
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str r2, [r1] @ WRITE
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ldr r2, [r1] @ DELAY UNTIL WRITTEN
|
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|
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/* set CSADRCFG[1] to data flash SRAM mode */ |
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ldr r1, =CSADRCFG1 |
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ldr r2, =0x00320809 |
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str r2, [r1] @ WRITE
|
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ldr r2, [r1] @ DELAY UNTIL WRITTEN
|
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|
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/* set MSC 0 register for SRAM memory */ |
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ldr r1, =MSC0 |
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ldr r2, =0x11191119 |
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str r2, [r1] @ WRITE
|
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ldr r2, [r1] @ DELAY UNTIL WRITTEN
|
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|
||||
/* set CSADRCFG[2] to data flash SRAM mode */ |
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ldr r1, =CSADRCFG2 |
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ldr r2, =0x00320809 |
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str r2, [r1] @ WRITE
|
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ldr r2, [r1] @ DELAY UNTIL WRITTEN
|
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|
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/* set CSADRCFG[3] to VLIO mode */ |
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ldr r1, =CSADRCFG3 |
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ldr r2, =0x0032080B |
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str r2, [r1] @ WRITE
|
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ldr r2, [r1] @ DELAY UNTIL WRITTEN
|
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|
||||
/* set MSC 1 register for VLIO memory */ |
||||
ldr r1, =MSC1 |
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ldr r2, =0x123C1119 |
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str r2, [r1] @ WRITE
|
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ldr r2, [r1] @ DELAY UNTIL WRITTEN
|
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|
||||
#if 0 |
||||
/* This does not work in Zylonite. -SC */ |
||||
ldr r0, =0x15fffff0 |
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ldr r1, =0xb10b |
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str r1, [r0] |
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str r1, [r0, #4] |
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#endif |
||||
|
||||
/* Configure ACCR Register */ |
||||
ldr r0, =ACCR @ ACCR
|
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ldr r1, =0x0180b108 |
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str r1, [r0] |
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ldr r1, [r0] |
||||
|
||||
/* Configure MDCNFG Register */ |
||||
ldr r0, =MDCNFG @ MDCNFG
|
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ldr r1, =0x403 |
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str r1, [r0] |
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ldr r1, [r0] |
||||
|
||||
/* Perform Resistive Compensation by configuring RCOMP register */ |
||||
ldr r1, =RCOMP @ RCOMP
|
||||
ldr r2, =0x000000ff |
||||
str r2, [r1] |
||||
ldr r2, [r1] |
||||
|
||||
/* Configure MDMRS Register for SDCS0 */ |
||||
ldr r1, =MDMRS @ MDMRS
|
||||
ldr r2, =0x60000023 |
||||
ldr r3, [r1] |
||||
orr r2, r2, r3 |
||||
str r2, [r1] |
||||
ldr r2, [r1] |
||||
|
||||
/* Configure MDMRS Register for SDCS1 */ |
||||
ldr r1, =MDMRS @ MDMRS
|
||||
ldr r2, =0xa0000023 |
||||
ldr r3, [r1] |
||||
orr r2, r2, r3 |
||||
str r2, [r1] |
||||
ldr r2, [r1] |
||||
|
||||
/* Configure MDREFR */ |
||||
ldr r1, =MDREFR @ MDREFR
|
||||
ldr r2, =0x00000006 |
||||
str r2, [r1] |
||||
ldr r2, [r1] |
||||
|
||||
/* Configure EMPI */ |
||||
ldr r1, =EMPI @ EMPI
|
||||
ldr r2, =0x80000000 |
||||
str r2, [r1] |
||||
ldr r2, [r1] |
||||
|
||||
/* Hardware DDR Read-Strobe Delay Calibration */ |
||||
ldr r0, =DDR_HCAL @ DDR_HCAL
|
||||
ldr r1, =0x803ffc07 @ the offset is correct? -SC
|
||||
str r1, [r0] |
||||
wait #5 |
||||
ldr r1, [r0] |
||||
|
||||
/* Here we assume the hardware calibration alwasy be successful. -SC */ |
||||
/* Set DMCEN bit in MDCNFG Register */ |
||||
ldr r0, =MDCNFG @ MDCNFG
|
||||
ldr r1, [r0] |
||||
orr r1, r1, #0x40000000 @ enable SDRAM for Normal Access
|
||||
str r1, [r0] |
||||
|
||||
#endif /* NEW_SDRAM_INIT */ |
||||
|
||||
#ifndef CFG_SKIP_DRAM_SCRUB |
||||
/* scrub/init SDRAM if enabled/present */ |
||||
ldr r8, =CFG_DRAM_BASE /* base address of SDRAM (CFG_DRAM_BASE) */ |
||||
ldr r9, =CFG_DRAM_SIZE /* size of memory to scrub (CFG_DRAM_SIZE) */ |
||||
mov r0, #0 /* scrub with 0x0000:0000 */ |
||||
mov r1, #0 |
||||
mov r2, #0 |
||||
mov r3, #0 |
||||
mov r4, #0 |
||||
mov r5, #0 |
||||
mov r6, #0 |
||||
mov r7, #0 |
||||
10: /* fastScrubLoop */ |
||||
subs r9, r9, #32 /* 8 words/line */ |
||||
stmia r8!, {r0-r7} |
||||
beq 15f |
||||
b 10b |
||||
#endif /* CFG_SKIP_DRAM_SCRUB */ |
||||
|
||||
15: |
||||
/* Mask all interrupts */ |
||||
mov r1, #0 |
||||
mcr p6, 0, r1, c1, c0, 0 @ ICMR
|
||||
|
||||
/* Disable software and data breakpoints */ |
||||
mov r0, #0 |
||||
mcr p15,0,r0,c14,c8,0 /* ibcr0 */ |
||||
mcr p15,0,r0,c14,c9,0 /* ibcr1 */ |
||||
mcr p15,0,r0,c14,c4,0 /* dbcon */ |
||||
|
||||
/* Enable all debug functionality */ |
||||
mov r0,#0x80000000 |
||||
mcr p14,0,r0,c10,c0,0 /* dcsr */ |
||||
|
||||
endlowlevel_init: |
||||
|
||||
mov pc, lr |
||||
|
||||
|
||||
/* |
||||
@********************************************************************************
|
||||
@ DDR calibration
|
||||
@
|
||||
@ This function is used to calibrate DQS delay lines.
|
||||
@ Monahans supports three ways to do it. One is software
|
||||
@ calibration. Two is hardware calibration. Three is hybrid
|
||||
@ calibration.
|
||||
@
|
||||
@ TBD
|
||||
@ -SC
|
||||
ddr_calibration: |
||||
|
||||
@ Case 1: Write the correct delay value once
|
||||
@ Configure DDR_SCAL Register
|
||||
ldr r0, =DDR_SCAL @ DDR_SCAL
|
||||
q ldr r1, =0xaf2f2f2f |
||||
str r1, [r0] |
||||
ldr r1, [r0] |
||||
*/ |
||||
/* @ Case 2: Software Calibration
|
||||
@ Write test pattern to memory
|
||||
ldr r5, =0x0faf0faf @ Data Pattern
|
||||
ldr r4, =0xa0000000 @ DDR ram
|
||||
str r5, [r4] |
||||
|
||||
mov r1, =0x0 @ delay count
|
||||
mov r6, =0x0 |
||||
mov r7, =0x0 |
||||
ddr_loop1: |
||||
add r1, r1, =0x1 |
||||
cmp r1, =0xf |
||||
ble end_loop |
||||
mov r3, r1 |
||||
mov r0, r1, lsl #30 |
||||
orr r3, r3, r0 |
||||
mov r0, r1, lsl #22 |
||||
orr r3, r3, r0 |
||||
mov r0, r1, lsl #14 |
||||
orr r3, r3, r0 |
||||
orr r3, r3, =0x80000000 |
||||
ldr r2, =DDR_SCAL |
||||
str r3, [r2] |
||||
|
||||
ldr r2, [r4] |
||||
cmp r2, r5 |
||||
bne ddr_loop1 |
||||
mov r6, r1 |
||||
ddr_loop2: |
||||
add r1, r1, =0x1 |
||||
cmp r1, =0xf |
||||
ble end_loop |
||||
mov r3, r1 |
||||
mov r0, r1, lsl #30 |
||||
orr r3, r3, r0 |
||||
mov r0, r1, lsl #22 |
||||
orr r3, r3, r0 |
||||
mov r0, r1, lsl #14 |
||||
orr r3, r3, r0 |
||||
orr r3, r3, =0x80000000 |
||||
ldr r2, =DDR_SCAL |
||||
str r3, [r2] |
||||
|
||||
ldr r2, [r4] |
||||
cmp r2, r5 |
||||
be ddr_loop2 |
||||
mov r7, r2 |
||||
|
||||
add r3, r6, r7 |
||||
lsr r3, r3, =0x1 |
||||
mov r0, r1, lsl #30 |
||||
orr r3, r3, r0 |
||||
mov r0, r1, lsl #22 |
||||
orr r3, r3, r0 |
||||
mov r0, r1, lsl #14 |
||||
orr r3, r3, r0 |
||||
orr r3, r3, =0x80000000 |
||||
ldr r2, =DDR_SCAL |
||||
|
||||
end_loop: |
||||
|
||||
@ Case 3: Hardware Calibratoin
|
||||
ldr r0, =DDR_HCAL @ DDR_HCAL
|
||||
ldr r1, =0x803ffc07 @ the offset is correct? -SC
|
||||
str r1, [r0] |
||||
wait #5 |
||||
ldr r1, [r0] |
||||
mov pc, lr |
||||
*/ |
||||
@ -0,0 +1,590 @@ |
||||
/*
|
||||
* (C) Copyright 2006 DENX Software Engineering |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_NAND) |
||||
#ifdef CONFIG_NEW_NAND_CODE |
||||
|
||||
#include <nand.h> |
||||
#include <asm/arch/pxa-regs.h> |
||||
|
||||
#ifdef CFG_DFC_DEBUG1 |
||||
# define DFC_DEBUG1(fmt, args...) printf(fmt, ##args) |
||||
#else |
||||
# define DFC_DEBUG1(fmt, args...) |
||||
#endif |
||||
|
||||
#ifdef CFG_DFC_DEBUG2 |
||||
# define DFC_DEBUG2(fmt, args...) printf(fmt, ##args) |
||||
#else |
||||
# define DFC_DEBUG2(fmt, args...) |
||||
#endif |
||||
|
||||
#ifdef CFG_DFC_DEBUG3 |
||||
# define DFC_DEBUG3(fmt, args...) printf(fmt, ##args) |
||||
#else |
||||
# define DFC_DEBUG3(fmt, args...) |
||||
#endif |
||||
|
||||
#define MIN(x, y) ((x < y) ? x : y) |
||||
|
||||
/* These really don't belong here, as they are specific to the NAND Model */ |
||||
static uint8_t scan_ff_pattern[] = { 0xff, 0xff }; |
||||
|
||||
static struct nand_bbt_descr delta_bbt_descr = { |
||||
.options = 0, |
||||
.offs = 0, |
||||
.len = 2, |
||||
.pattern = scan_ff_pattern |
||||
}; |
||||
|
||||
static struct nand_oobinfo delta_oob = { |
||||
.useecc = MTD_NANDECC_AUTOPL_USR, /* MTD_NANDECC_PLACEONLY, */ |
||||
.eccbytes = 6, |
||||
.eccpos = {2, 3, 4, 5, 6, 7}, |
||||
.oobfree = { {8, 2}, {12, 4} } |
||||
}; |
||||
|
||||
|
||||
/*
|
||||
* not required for Monahans DFC |
||||
*/ |
||||
static void dfc_hwcontrol(struct mtd_info *mtdinfo, int cmd) |
||||
{ |
||||
return; |
||||
} |
||||
|
||||
#if 0 |
||||
/* read device ready pin */ |
||||
static int dfc_device_ready(struct mtd_info *mtdinfo) |
||||
{ |
||||
if(NDSR & NDSR_RDY) |
||||
return 1; |
||||
else |
||||
return 0; |
||||
return 0; |
||||
} |
||||
#endif |
||||
|
||||
/*
|
||||
* Write buf to the DFC Controller Data Buffer |
||||
*/ |
||||
static void dfc_write_buf(struct mtd_info *mtd, const u_char *buf, int len) |
||||
{ |
||||
unsigned long bytes_multi = len & 0xfffffffc; |
||||
unsigned long rest = len & 0x3; |
||||
unsigned long *long_buf; |
||||
int i; |
||||
|
||||
DFC_DEBUG2("dfc_write_buf: writing %d bytes starting with 0x%x.\n", len, *((unsigned long*) buf)); |
||||
if(bytes_multi) { |
||||
for(i=0; i<bytes_multi; i+=4) { |
||||
long_buf = (unsigned long*) &buf[i]; |
||||
NDDB = *long_buf; |
||||
} |
||||
} |
||||
if(rest) { |
||||
printf("dfc_write_buf: ERROR, writing non 4-byte aligned data.\n"); |
||||
} |
||||
return; |
||||
} |
||||
|
||||
|
||||
/*
|
||||
* These functions are quite problematic for the DFC. Luckily they are |
||||
* not used in the current nand code, except for nand_command, which |
||||
* we've defined our own anyway. The problem is, that we always need |
||||
* to write 4 bytes to the DFC Data Buffer, but in these functions we |
||||
* don't know if to buffer the bytes/half words until we've gathered 4 |
||||
* bytes or if to send them straight away. |
||||
* |
||||
* Solution: Don't use these with Mona's DFC and complain loudly. |
||||
*/ |
||||
static void dfc_write_word(struct mtd_info *mtd, u16 word) |
||||
{ |
||||
printf("dfc_write_word: WARNING, this function does not work with the Monahans DFC!\n"); |
||||
} |
||||
static void dfc_write_byte(struct mtd_info *mtd, u_char byte) |
||||
{ |
||||
printf("dfc_write_byte: WARNING, this function does not work with the Monahans DFC!\n"); |
||||
} |
||||
|
||||
/* The original:
|
||||
* static void dfc_read_buf(struct mtd_info *mtd, const u_char *buf, int len) |
||||
* |
||||
* Shouldn't this be "u_char * const buf" ? |
||||
*/ |
||||
static void dfc_read_buf(struct mtd_info *mtd, u_char* const buf, int len) |
||||
{ |
||||
int i=0, j; |
||||
|
||||
/* we have to be carefull not to overflow the buffer if len is
|
||||
* not a multiple of 4 */ |
||||
unsigned long bytes_multi = len & 0xfffffffc; |
||||
unsigned long rest = len & 0x3; |
||||
unsigned long *long_buf; |
||||
|
||||
DFC_DEBUG3("dfc_read_buf: reading %d bytes.\n", len); |
||||
/* if there are any, first copy multiple of 4 bytes */ |
||||
if(bytes_multi) { |
||||
for(i=0; i<bytes_multi; i+=4) { |
||||
long_buf = (unsigned long*) &buf[i]; |
||||
*long_buf = NDDB; |
||||
} |
||||
} |
||||
|
||||
/* ...then the rest */ |
||||
if(rest) { |
||||
unsigned long rest_data = NDDB; |
||||
for(j=0;j<rest; j++) |
||||
buf[i+j] = (u_char) ((rest_data>>j) & 0xff); |
||||
} |
||||
|
||||
return; |
||||
} |
||||
|
||||
/*
|
||||
* read a word. Not implemented as not used in NAND code. |
||||
*/ |
||||
static u16 dfc_read_word(struct mtd_info *mtd) |
||||
{ |
||||
printf("dfc_write_byte: UNIMPLEMENTED.\n"); |
||||
return 0; |
||||
} |
||||
|
||||
/* global var, too bad: mk@tbd: move to ->priv pointer */ |
||||
static unsigned long read_buf = 0; |
||||
static int bytes_read = -1; |
||||
|
||||
/*
|
||||
* read a byte from NDDB Because we can only read 4 bytes from NDDB at |
||||
* a time, we buffer the remaining bytes. The buffer is reset when a |
||||
* new command is sent to the chip. |
||||
* |
||||
* WARNING: |
||||
* This function is currently only used to read status and id |
||||
* bytes. For these commands always 8 bytes need to be read from |
||||
* NDDB. So we read and discard these bytes right now. In case this |
||||
* function is used for anything else in the future, we must check |
||||
* what was the last command issued and read the appropriate amount of |
||||
* bytes respectively. |
||||
*/ |
||||
static u_char dfc_read_byte(struct mtd_info *mtd) |
||||
{ |
||||
unsigned char byte; |
||||
unsigned long dummy; |
||||
|
||||
if(bytes_read < 0) { |
||||
read_buf = NDDB; |
||||
dummy = NDDB; |
||||
bytes_read = 0; |
||||
} |
||||
byte = (unsigned char) (read_buf>>(8 * bytes_read++)); |
||||
if(bytes_read >= 4) |
||||
bytes_read = -1; |
||||
|
||||
DFC_DEBUG2("dfc_read_byte: byte %u: 0x%x of (0x%x).\n", bytes_read - 1, byte, read_buf); |
||||
return byte; |
||||
} |
||||
|
||||
/* calculate delta between OSCR values start and now */ |
||||
static unsigned long get_delta(unsigned long start) |
||||
{ |
||||
unsigned long cur = OSCR; |
||||
|
||||
if(cur < start) /* OSCR overflowed */ |
||||
return (cur + (start^0xffffffff)); |
||||
else |
||||
return (cur - start); |
||||
} |
||||
|
||||
/* delay function, this doesn't belong here */ |
||||
static void wait_us(unsigned long us) |
||||
{ |
||||
unsigned long start = OSCR; |
||||
us *= OSCR_CLK_FREQ; |
||||
|
||||
while (get_delta(start) < us) { |
||||
/* do nothing */ |
||||
} |
||||
} |
||||
|
||||
static void dfc_clear_nddb(void) |
||||
{ |
||||
NDCR &= ~NDCR_ND_RUN; |
||||
wait_us(CFG_NAND_OTHER_TO); |
||||
} |
||||
|
||||
/* wait_event with timeout */ |
||||
static unsigned long dfc_wait_event(unsigned long event) |
||||
{ |
||||
unsigned long ndsr, timeout, start = OSCR; |
||||
|
||||
if(!event) |
||||
return 0xff000000; |
||||
else if(event & (NDSR_CS0_CMDD | NDSR_CS0_BBD)) |
||||
timeout = CFG_NAND_PROG_ERASE_TO * OSCR_CLK_FREQ; |
||||
else |
||||
timeout = CFG_NAND_OTHER_TO * OSCR_CLK_FREQ; |
||||
|
||||
while(1) { |
||||
ndsr = NDSR; |
||||
if(ndsr & event) { |
||||
NDSR |= event; |
||||
break; |
||||
} |
||||
if(get_delta(start) > timeout) { |
||||
DFC_DEBUG1("dfc_wait_event: TIMEOUT waiting for event: 0x%x.\n", event); |
||||
return 0xff000000; |
||||
} |
||||
|
||||
} |
||||
return ndsr; |
||||
} |
||||
|
||||
/* we don't always wan't to do this */ |
||||
static void dfc_new_cmd(void) |
||||
{ |
||||
int retry = 0; |
||||
unsigned long status; |
||||
|
||||
while(retry++ <= CFG_NAND_SENDCMD_RETRY) { |
||||
/* Clear NDSR */ |
||||
NDSR = 0xFFF; |
||||
|
||||
/* set NDCR[NDRUN] */ |
||||
if(!(NDCR & NDCR_ND_RUN)) |
||||
NDCR |= NDCR_ND_RUN; |
||||
|
||||
status = dfc_wait_event(NDSR_WRCMDREQ); |
||||
|
||||
if(status & NDSR_WRCMDREQ) |
||||
return; |
||||
|
||||
DFC_DEBUG2("dfc_new_cmd: FAILED to get WRITECMDREQ, retry: %d.\n", retry); |
||||
dfc_clear_nddb(); |
||||
} |
||||
DFC_DEBUG1("dfc_new_cmd: giving up after %d retries.\n", retry); |
||||
} |
||||
|
||||
/* this function is called after Programm and Erase Operations to
|
||||
* check for success or failure */ |
||||
static int dfc_wait(struct mtd_info *mtd, struct nand_chip *this, int state) |
||||
{ |
||||
unsigned long ndsr=0, event=0; |
||||
|
||||
/* mk@tbd set appropriate timeouts */ |
||||
/* if (state == FL_ERASING) */ |
||||
/* timeo = CFG_HZ * 400; */ |
||||
/* else */ |
||||
/* timeo = CFG_HZ * 20; */ |
||||
if(state == FL_WRITING) { |
||||
event = NDSR_CS0_CMDD | NDSR_CS0_BBD; |
||||
} else if(state == FL_ERASING) { |
||||
event = NDSR_CS0_CMDD | NDSR_CS0_BBD; |
||||
} |
||||
|
||||
ndsr = dfc_wait_event(event); |
||||
|
||||
if((ndsr & NDSR_CS0_BBD) || (ndsr & 0xff000000)) |
||||
return(0x1); /* Status Read error */ |
||||
return 0; |
||||
} |
||||
|
||||
/* cmdfunc send commands to the DFC */ |
||||
static void dfc_cmdfunc(struct mtd_info *mtd, unsigned command, |
||||
int column, int page_addr) |
||||
{ |
||||
/* register struct nand_chip *this = mtd->priv; */ |
||||
unsigned long ndcb0=0, ndcb1=0, ndcb2=0, event=0; |
||||
|
||||
/* clear the ugly byte read buffer */ |
||||
bytes_read = -1; |
||||
read_buf = 0; |
||||
|
||||
switch (command) { |
||||
case NAND_CMD_READ0: |
||||
DFC_DEBUG3("dfc_cmdfunc: NAND_CMD_READ0, page_addr: 0x%x, column: 0x%x.\n", page_addr, (column>>1)); |
||||
dfc_new_cmd(); |
||||
ndcb0 = (NAND_CMD_READ0 | (4<<16)); |
||||
column >>= 1; /* adjust for 16 bit bus */ |
||||
ndcb1 = (((column>>1) & 0xff) | |
||||
((page_addr<<8) & 0xff00) | |
||||
((page_addr<<8) & 0xff0000) | |
||||
((page_addr<<8) & 0xff000000)); /* make this 0x01000000 ? */ |
||||
event = NDSR_RDDREQ; |
||||
goto write_cmd; |
||||
case NAND_CMD_READ1: |
||||
DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_READ1 unimplemented!\n"); |
||||
goto end; |
||||
case NAND_CMD_READOOB: |
||||
DFC_DEBUG1("dfc_cmdfunc: NAND_CMD_READOOB unimplemented!\n"); |
||||
goto end; |
||||
case NAND_CMD_READID: |
||||
dfc_new_cmd(); |
||||
DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_READID.\n"); |
||||
ndcb0 = (NAND_CMD_READID | (3 << 21) | (1 << 16)); /* addr cycles*/ |
||||
event = NDSR_RDDREQ; |
||||
goto write_cmd; |
||||
case NAND_CMD_PAGEPROG: |
||||
/* sent as a multicommand in NAND_CMD_SEQIN */ |
||||
DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_PAGEPROG empty due to multicmd.\n"); |
||||
goto end; |
||||
case NAND_CMD_ERASE1: |
||||
DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_ERASE1, page_addr: 0x%x, column: 0x%x.\n", page_addr, (column>>1)); |
||||
dfc_new_cmd(); |
||||
ndcb0 = (0xd060 | (1<<25) | (2<<21) | (1<<19) | (3<<16)); |
||||
ndcb1 = (page_addr & 0x00ffffff); |
||||
goto write_cmd; |
||||
case NAND_CMD_ERASE2: |
||||
DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_ERASE2 empty due to multicmd.\n"); |
||||
goto end; |
||||
case NAND_CMD_SEQIN: |
||||
/* send PAGE_PROG command(0x1080) */ |
||||
dfc_new_cmd(); |
||||
DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_SEQIN/PAGE_PROG, page_addr: 0x%x, column: 0x%x.\n", page_addr, (column>>1)); |
||||
ndcb0 = (0x1080 | (1<<25) | (1<<21) | (1<<19) | (4<<16)); |
||||
column >>= 1; /* adjust for 16 bit bus */ |
||||
ndcb1 = (((column>>1) & 0xff) | |
||||
((page_addr<<8) & 0xff00) | |
||||
((page_addr<<8) & 0xff0000) | |
||||
((page_addr<<8) & 0xff000000)); /* make this 0x01000000 ? */ |
||||
event = NDSR_WRDREQ; |
||||
goto write_cmd; |
||||
case NAND_CMD_STATUS: |
||||
DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_STATUS.\n"); |
||||
dfc_new_cmd(); |
||||
ndcb0 = NAND_CMD_STATUS | (4<<21); |
||||
event = NDSR_RDDREQ; |
||||
goto write_cmd; |
||||
case NAND_CMD_RESET: |
||||
DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_RESET.\n"); |
||||
ndcb0 = NAND_CMD_RESET | (5<<21); |
||||
event = NDSR_CS0_CMDD; |
||||
goto write_cmd; |
||||
default: |
||||
printk("dfc_cmdfunc: error, unsupported command.\n"); |
||||
goto end; |
||||
} |
||||
|
||||
write_cmd: |
||||
NDCB0 = ndcb0; |
||||
NDCB0 = ndcb1; |
||||
NDCB0 = ndcb2; |
||||
|
||||
/* wait_event: */ |
||||
dfc_wait_event(event); |
||||
end: |
||||
return; |
||||
} |
||||
|
||||
static void dfc_gpio_init(void) |
||||
{ |
||||
DFC_DEBUG2("Setting up DFC GPIO's.\n"); |
||||
|
||||
/* no idea what is done here, see zylonite.c */ |
||||
GPIO4 = 0x1; |
||||
|
||||
DF_ALE_WE1 = 0x00000001; |
||||
DF_ALE_WE2 = 0x00000001; |
||||
DF_nCS0 = 0x00000001; |
||||
DF_nCS1 = 0x00000001; |
||||
DF_nWE = 0x00000001; |
||||
DF_nRE = 0x00000001; |
||||
DF_IO0 = 0x00000001; |
||||
DF_IO8 = 0x00000001; |
||||
DF_IO1 = 0x00000001; |
||||
DF_IO9 = 0x00000001; |
||||
DF_IO2 = 0x00000001; |
||||
DF_IO10 = 0x00000001; |
||||
DF_IO3 = 0x00000001; |
||||
DF_IO11 = 0x00000001; |
||||
DF_IO4 = 0x00000001; |
||||
DF_IO12 = 0x00000001; |
||||
DF_IO5 = 0x00000001; |
||||
DF_IO13 = 0x00000001; |
||||
DF_IO6 = 0x00000001; |
||||
DF_IO14 = 0x00000001; |
||||
DF_IO7 = 0x00000001; |
||||
DF_IO15 = 0x00000001; |
||||
|
||||
DF_nWE = 0x1901; |
||||
DF_nRE = 0x1901; |
||||
DF_CLE_NOE = 0x1900; |
||||
DF_ALE_WE1 = 0x1901; |
||||
DF_INT_RnB = 0x1900; |
||||
} |
||||
|
||||
/*
|
||||
* Board-specific NAND initialization. The following members of the |
||||
* argument are board-specific (per include/linux/mtd/nand_new.h): |
||||
* - IO_ADDR_R?: address to read the 8 I/O lines of the flash device |
||||
* - IO_ADDR_W?: address to write the 8 I/O lines of the flash device |
||||
* - hwcontrol: hardwarespecific function for accesing control-lines |
||||
* - dev_ready: hardwarespecific function for accesing device ready/busy line |
||||
* - enable_hwecc?: function to enable (reset) hardware ecc generator. Must |
||||
* only be provided if a hardware ECC is available |
||||
* - eccmode: mode of ecc, see defines |
||||
* - chip_delay: chip dependent delay for transfering data from array to |
||||
* read regs (tR) |
||||
* - options: various chip options. They can partly be set to inform |
||||
* nand_scan about special functionality. See the defines for further |
||||
* explanation |
||||
* Members with a "?" were not set in the merged testing-NAND branch, |
||||
* so they are not set here either. |
||||
*/ |
||||
void board_nand_init(struct nand_chip *nand) |
||||
{ |
||||
unsigned long tCH, tCS, tWH, tWP, tRH, tRP, tRP_high, tR, tWHR, tAR; |
||||
|
||||
/* set up GPIO Control Registers */ |
||||
dfc_gpio_init(); |
||||
|
||||
/* turn on the NAND Controller Clock (104 MHz @ D0) */ |
||||
CKENA |= (CKENA_4_NAND | CKENA_9_SMC); |
||||
|
||||
#undef CFG_TIMING_TIGHT |
||||
#ifndef CFG_TIMING_TIGHT |
||||
tCH = MIN(((unsigned long) (NAND_TIMING_tCH * DFC_CLK_PER_US) + 1), |
||||
DFC_MAX_tCH); |
||||
tCS = MIN(((unsigned long) (NAND_TIMING_tCS * DFC_CLK_PER_US) + 1), |
||||
DFC_MAX_tCS); |
||||
tWH = MIN(((unsigned long) (NAND_TIMING_tWH * DFC_CLK_PER_US) + 1), |
||||
DFC_MAX_tWH); |
||||
tWP = MIN(((unsigned long) (NAND_TIMING_tWP * DFC_CLK_PER_US) + 1), |
||||
DFC_MAX_tWP); |
||||
tRH = MIN(((unsigned long) (NAND_TIMING_tRH * DFC_CLK_PER_US) + 1), |
||||
DFC_MAX_tRH); |
||||
tRP = MIN(((unsigned long) (NAND_TIMING_tRP * DFC_CLK_PER_US) + 1), |
||||
DFC_MAX_tRP); |
||||
tR = MIN(((unsigned long) (NAND_TIMING_tR * DFC_CLK_PER_US) + 1), |
||||
DFC_MAX_tR); |
||||
tWHR = MIN(((unsigned long) (NAND_TIMING_tWHR * DFC_CLK_PER_US) + 1), |
||||
DFC_MAX_tWHR); |
||||
tAR = MIN(((unsigned long) (NAND_TIMING_tAR * DFC_CLK_PER_US) + 1), |
||||
DFC_MAX_tAR); |
||||
#else /* this is the tight timing */ |
||||
|
||||
tCH = MIN(((unsigned long) (NAND_TIMING_tCH * DFC_CLK_PER_US)), |
||||
DFC_MAX_tCH); |
||||
tCS = MIN(((unsigned long) (NAND_TIMING_tCS * DFC_CLK_PER_US)), |
||||
DFC_MAX_tCS); |
||||
tWH = MIN(((unsigned long) (NAND_TIMING_tWH * DFC_CLK_PER_US)), |
||||
DFC_MAX_tWH); |
||||
tWP = MIN(((unsigned long) (NAND_TIMING_tWP * DFC_CLK_PER_US)), |
||||
DFC_MAX_tWP); |
||||
tRH = MIN(((unsigned long) (NAND_TIMING_tRH * DFC_CLK_PER_US)), |
||||
DFC_MAX_tRH); |
||||
tRP = MIN(((unsigned long) (NAND_TIMING_tRP * DFC_CLK_PER_US)), |
||||
DFC_MAX_tRP); |
||||
tR = MIN(((unsigned long) (NAND_TIMING_tR * DFC_CLK_PER_US) - tCH - 2), |
||||
DFC_MAX_tR); |
||||
tWHR = MIN(((unsigned long) (NAND_TIMING_tWHR * DFC_CLK_PER_US) - tCH - 2), |
||||
DFC_MAX_tWHR); |
||||
tAR = MIN(((unsigned long) (NAND_TIMING_tAR * DFC_CLK_PER_US) - 2), |
||||
DFC_MAX_tAR); |
||||
#endif /* CFG_TIMING_TIGHT */ |
||||
|
||||
|
||||
DFC_DEBUG2("tCH=%u, tCS=%u, tWH=%u, tWP=%u, tRH=%u, tRP=%u, tR=%u, tWHR=%u, tAR=%u.\n", tCH, tCS, tWH, tWP, tRH, tRP, tR, tWHR, tAR); |
||||
|
||||
/* tRP value is split in the register */ |
||||
if(tRP & (1 << 4)) { |
||||
tRP_high = 1; |
||||
tRP &= ~(1 << 4); |
||||
} else { |
||||
tRP_high = 0; |
||||
} |
||||
|
||||
NDTR0CS0 = (tCH << 19) | |
||||
(tCS << 16) | |
||||
(tWH << 11) | |
||||
(tWP << 8) | |
||||
(tRP_high << 6) | |
||||
(tRH << 3) | |
||||
(tRP << 0); |
||||
|
||||
NDTR1CS0 = (tR << 16) | |
||||
(tWHR << 4) | |
||||
(tAR << 0); |
||||
|
||||
/* If it doesn't work (unlikely) think about:
|
||||
* - ecc enable |
||||
* - chip select don't care |
||||
* - read id byte count |
||||
* |
||||
* Intentionally enabled by not setting bits: |
||||
* - dma (DMA_EN) |
||||
* - page size = 512 |
||||
* - cs don't care, see if we can enable later! |
||||
* - row address start position (after second cycle) |
||||
* - pages per block = 32 |
||||
* - ND_RDY : clears command buffer |
||||
*/ |
||||
/* NDCR_NCSX | /\* Chip select busy don't care *\/ */ |
||||
|
||||
NDCR = (NDCR_SPARE_EN | /* use the spare area */ |
||||
NDCR_DWIDTH_C | /* 16bit DFC data bus width */ |
||||
NDCR_DWIDTH_M | /* 16 bit Flash device data bus width */ |
||||
(2 << 16) | /* read id count = 7 ???? mk@tbd */ |
||||
NDCR_ND_ARB_EN | /* enable bus arbiter */ |
||||
NDCR_RDYM | /* flash device ready ir masked */ |
||||
NDCR_CS0_PAGEDM | /* ND_nCSx page done ir masked */ |
||||
NDCR_CS1_PAGEDM | |
||||
NDCR_CS0_CMDDM | /* ND_CSx command done ir masked */ |
||||
NDCR_CS1_CMDDM | |
||||
NDCR_CS0_BBDM | /* ND_CSx bad block detect ir masked */ |
||||
NDCR_CS1_BBDM | |
||||
NDCR_DBERRM | /* double bit error ir masked */ |
||||
NDCR_SBERRM | /* single bit error ir masked */ |
||||
NDCR_WRDREQM | /* write data request ir masked */ |
||||
NDCR_RDDREQM | /* read data request ir masked */ |
||||
NDCR_WRCMDREQM); /* write command request ir masked */ |
||||
|
||||
|
||||
/* wait 10 us due to cmd buffer clear reset */ |
||||
/* wait(10); */ |
||||
|
||||
|
||||
nand->hwcontrol = dfc_hwcontrol; |
||||
/* nand->dev_ready = dfc_device_ready; */ |
||||
nand->eccmode = NAND_ECC_SOFT; |
||||
nand->chip_delay = NAND_DELAY_US; |
||||
nand->options = NAND_BUSWIDTH_16; |
||||
nand->waitfunc = dfc_wait; |
||||
nand->read_byte = dfc_read_byte; |
||||
nand->write_byte = dfc_write_byte; |
||||
nand->read_word = dfc_read_word; |
||||
nand->write_word = dfc_write_word; |
||||
nand->read_buf = dfc_read_buf; |
||||
nand->write_buf = dfc_write_buf; |
||||
|
||||
nand->cmdfunc = dfc_cmdfunc; |
||||
nand->autooob = &delta_oob; |
||||
nand->badblock_pattern = &delta_bbt_descr; |
||||
} |
||||
|
||||
#else |
||||
#error "U-Boot legacy NAND support not available for Monahans DFC." |
||||
#endif |
||||
#endif |
||||
@ -0,0 +1,56 @@ |
||||
/* |
||||
* (C) Copyright 2000 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") |
||||
OUTPUT_ARCH(arm) |
||||
ENTRY(_start) |
||||
SECTIONS |
||||
{ |
||||
. = 0x00000000; |
||||
|
||||
. = ALIGN(4); |
||||
.text : |
||||
{ |
||||
cpu/pxa/start.o (.text) |
||||
*(.text) |
||||
} |
||||
|
||||
. = ALIGN(4); |
||||
.rodata : { *(.rodata) } |
||||
|
||||
. = ALIGN(4); |
||||
.data : { *(.data) } |
||||
|
||||
. = ALIGN(4); |
||||
.got : { *(.got) } |
||||
|
||||
. = .; |
||||
__u_boot_cmd_start = .; |
||||
.u_boot_cmd : { *(.u_boot_cmd) } |
||||
__u_boot_cmd_end = .; |
||||
|
||||
. = ALIGN(4); |
||||
__bss_start = .; |
||||
.bss : { *(.bss) } |
||||
_end = .; |
||||
} |
||||
@ -0,0 +1,46 @@ |
||||
#
|
||||
# Copyright (C) 2004 Arabella Software Ltd.
|
||||
# Yuli Barcohen <yuli@arabellasw.com>
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
include $(TOPDIR)/config.mk |
||||
|
||||
LIB = lib$(BOARD).a
|
||||
|
||||
OBJS := $(BOARD).o
|
||||
|
||||
$(LIB): $(OBJS) $(SOBJS) |
||||
$(AR) crv $@ $(OBJS)
|
||||
|
||||
clean: |
||||
rm -f $(SOBJS) $(OBJS)
|
||||
|
||||
distclean: clean |
||||
rm -f $(LIB) core *.bak .depend
|
||||
|
||||
#########################################################################
|
||||
|
||||
.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) |
||||
$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
|
||||
|
||||
-include .depend |
||||
|
||||
#########################################################################
|
||||
@ -0,0 +1,27 @@ |
||||
#
|
||||
# Copyright (C) 2005 Arabella Software Ltd.
|
||||
# Yuli Barcohen <yuli@arabellasw.com>
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
#
|
||||
# Embedded Planet EP88x boards
|
||||
#
|
||||
TEXT_BASE = 0xFC000000
|
||||
@ -0,0 +1,133 @@ |
||||
/*
|
||||
* Copyright (C) 2005 Arabella Software Ltd. |
||||
* Yuli Barcohen <yuli@arabellasw.com> |
||||
* |
||||
* Support for Embedded Planet EP88x boards. |
||||
* Tested on EP88xC with MPC885 CPU, 64MB SDRAM and 16MB flash. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <mpc8xx.h> |
||||
|
||||
/*
|
||||
* SDRAM uses two Micron chips. |
||||
* Minimal CPU frequency is 40MHz. |
||||
*/ |
||||
static uint sdram_table[] = { |
||||
/* Single read (offset 0x00 in UPM RAM) */ |
||||
0xEFCBCC04, 0x0F37C804, 0x0EEEC004, 0x01B98404, |
||||
0x1FF74C00, 0xFFFFCC05, 0xFFFFCC05, 0xFFFFCC05, |
||||
|
||||
/* Burst read (offset 0x08 in UPM RAM) */ |
||||
0xEFCBCC04, 0x0F37C804, 0x0EEEC004, 0x00BDC404, |
||||
0x00FFCC00, 0x00FFCC00, 0x01FB8C00, 0x1FF74C00, |
||||
0xFFFFCC05, 0xFFFFCC05, 0xFFFFCC05, 0xFFFFCC05, |
||||
0xFFFFCC05, 0xFFFFCC05, 0xFFFFCC05, 0xFFFFCC05, |
||||
|
||||
/* Single write (offset 0x18 in UPM RAM) */ |
||||
0xEFCBCC04, 0x0F37C804, 0x0EEE8002, 0x01B90404, |
||||
0x1FF74C05, 0xFFFFCC05, 0xFFFFCC05, 0xFFFFCC05, |
||||
|
||||
/* Burst write (offset 0x20 in UPM RAM) */ |
||||
0xEFCBCC04, 0x0F37C804, 0x0EEE8000, 0x00BD4400, |
||||
0x00FFCC00, 0x00FFCC02, 0x01FB8C04, 0x1FF74C05, |
||||
0xFFFFCC05, 0xFFFFCC05, 0xFFFFCC05, 0xFFFFCC05, |
||||
0xFFFFCC05, 0xFFFFCC05, 0xFFFFCC05, 0xFFFFCC05, |
||||
|
||||
/* Refresh (offset 0x30 in UPM RAM) */ |
||||
0xEFFACC04, 0x0FF5CC04, 0x0FFFCC04, 0x1FFFCC04, |
||||
0xFFFFCC05, 0xFFFFCC05, 0xEFFB8C34, 0x0FF74C34, |
||||
0x0FFACCB4, 0x0FF5CC34, 0x0FFFC034, 0x0FFFC0B4, |
||||
|
||||
/* Exception (offset 0x3C in UPM RAM) */ |
||||
0x0FEA8034, 0x1FB54034, 0xFFFFCC34, 0xFFFFCC05 |
||||
}; |
||||
|
||||
int board_early_init_f (void) |
||||
{ |
||||
vu_char *bcsr = (vu_char *)CFG_BCSR; |
||||
|
||||
bcsr[0] |= 0x0C; /* Turn the LEDs off */ |
||||
bcsr[2] |= 0x08; /* Enable flash WE# line - necessary for
|
||||
flash detection by CFI driver |
||||
*/ |
||||
|
||||
#if defined(CONFIG_8xx_CONS_SMC1) |
||||
bcsr[6] |= 0x10; /* Enables RS-232 transceiver */ |
||||
#endif |
||||
#if defined(CONFIG_8xx_CONS_SCC2) |
||||
bcsr[7] |= 0x10; /* Enables RS-232 transceiver */ |
||||
#endif |
||||
#ifdef CONFIG_ETHER_ON_FEC1 |
||||
bcsr[8] |= 0xC0; /* Enable Ethernet 1 PHY */ |
||||
#endif |
||||
#ifdef CONFIG_ETHER_ON_FEC2 |
||||
bcsr[8] |= 0x30; /* Enable Ethernet 2 PHY */ |
||||
#endif |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
long int initdram (int board_type) |
||||
{ |
||||
long int msize; |
||||
volatile immap_t *immap = (volatile immap_t *)CFG_IMMR; |
||||
volatile memctl8xx_t *memctl = &immap->im_memctl; |
||||
|
||||
upmconfig(UPMA, sdram_table, sizeof(sdram_table) / sizeof(uint)); |
||||
|
||||
/* Configure SDRAM refresh */ |
||||
memctl->memc_mptpr = MPTPR_PTP_DIV2; /* BRGCLK/2 */ |
||||
|
||||
memctl->memc_mamr = (65 << 24) | CFG_MAMR; /* No refresh */ |
||||
udelay(100); |
||||
|
||||
/* Run MRS pattern from location 0x36 */ |
||||
memctl->memc_mar = 0x88; |
||||
memctl->memc_mcr = 0x80002236; |
||||
udelay(100); |
||||
|
||||
memctl->memc_mamr |= MAMR_PTAE; /* Enable refresh */ |
||||
memctl->memc_or1 = ~(CFG_SDRAM_MAX_SIZE - 1) | OR_CSNT_SAM; |
||||
memctl->memc_br1 = CFG_SDRAM_BASE | BR_PS_32 | BR_MS_UPMA | BR_V; |
||||
|
||||
msize = get_ram_size(CFG_SDRAM_BASE, CFG_SDRAM_MAX_SIZE); |
||||
memctl->memc_or1 |= ~(msize - 1); |
||||
|
||||
return msize; |
||||
} |
||||
|
||||
int checkboard( void ) |
||||
{ |
||||
vu_char *bcsr = (vu_char *)CFG_BCSR; |
||||
|
||||
puts("Board: "); |
||||
switch (bcsr[15]) { |
||||
case 0xE7: |
||||
puts("EP88xC 1.0"); |
||||
break; |
||||
default: |
||||
printf("unknown ID=%02X", bcsr[15]); |
||||
} |
||||
printf(" CPLD revision %d\n", bcsr[14]); |
||||
|
||||
return 0; |
||||
} |
||||
@ -0,0 +1,122 @@ |
||||
/* |
||||
* (C) Copyright 2001-2003 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* Modified by Yuli Barcohen <yuli@arabellasw.com> |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
OUTPUT_ARCH(powerpc) |
||||
SECTIONS |
||||
{ |
||||
/* Read-only sections, merged into text segment: */ |
||||
. = + SIZEOF_HEADERS; |
||||
.interp : { *(.interp) } |
||||
.hash : { *(.hash) } |
||||
.dynsym : { *(.dynsym) } |
||||
.dynstr : { *(.dynstr) } |
||||
.rel.text : { *(.rel.text) } |
||||
.rela.text : { *(.rela.text) } |
||||
.rel.data : { *(.rel.data) } |
||||
.rela.data : { *(.rela.data) } |
||||
.rel.rodata : { *(.rel.rodata) } |
||||
.rela.rodata : { *(.rela.rodata) } |
||||
.rel.got : { *(.rel.got) } |
||||
.rela.got : { *(.rela.got) } |
||||
.rel.ctors : { *(.rel.ctors) } |
||||
.rela.ctors : { *(.rela.ctors) } |
||||
.rel.dtors : { *(.rel.dtors) } |
||||
.rela.dtors : { *(.rela.dtors) } |
||||
.rel.bss : { *(.rel.bss) } |
||||
.rela.bss : { *(.rela.bss) } |
||||
.rel.plt : { *(.rel.plt) } |
||||
.rela.plt : { *(.rela.plt) } |
||||
.init : { *(.init) } |
||||
.plt : { *(.plt) } |
||||
.text : |
||||
{ |
||||
cpu/mpc8xx/start.o (.text) |
||||
*(.text) |
||||
*(.fixup) |
||||
*(.got1) |
||||
. = ALIGN(16); |
||||
*(.rodata) |
||||
*(.rodata1) |
||||
*(.rodata.str1.4) |
||||
} |
||||
.fini : { *(.fini) } =0 |
||||
.ctors : { *(.ctors) } |
||||
.dtors : { *(.dtors) } |
||||
|
||||
/* Read-write section, merged into data segment: */ |
||||
. = (. + 0x0FFF) & 0xFFFFF000; |
||||
_erotext = .; |
||||
PROVIDE (erotext = .); |
||||
.reloc : |
||||
{ |
||||
*(.got) |
||||
_GOT2_TABLE_ = .; |
||||
*(.got2) |
||||
_FIXUP_TABLE_ = .; |
||||
*(.fixup) |
||||
} |
||||
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; |
||||
__fixup_entries = (. - _FIXUP_TABLE_) >> 2; |
||||
|
||||
.data : |
||||
{ |
||||
*(.data) |
||||
*(.data1) |
||||
*(.sdata) |
||||
*(.sdata2) |
||||
*(.dynamic) |
||||
CONSTRUCTORS |
||||
} |
||||
_edata = .; |
||||
PROVIDE (edata = .); |
||||
|
||||
__u_boot_cmd_start = .; |
||||
.u_boot_cmd : { *(.u_boot_cmd) } |
||||
__u_boot_cmd_end = .; |
||||
|
||||
|
||||
__start___ex_table = .; |
||||
__ex_table : { *(__ex_table) } |
||||
__stop___ex_table = .; |
||||
|
||||
. = ALIGN(4096); |
||||
__init_begin = .; |
||||
.text.init : { *(.text.init) } |
||||
.data.init : { *(.data.init) } |
||||
. = ALIGN(4096); |
||||
__init_end = .; |
||||
|
||||
__bss_start = .; |
||||
.bss : |
||||
{ |
||||
*(.sbss) *(.scommon) |
||||
*(.dynbss) |
||||
*(.bss) |
||||
*(COMMON) |
||||
} |
||||
_end = . ; |
||||
PROVIDE (end = .); |
||||
} |
||||
ENTRY(_start) |
||||
@ -0,0 +1,44 @@ |
||||
#
|
||||
# U-boot - Makefile
|
||||
#
|
||||
# Copyright (c) 2005 blackfin.uclinux.org
|
||||
#
|
||||
# (C) Copyright 2000-2004
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
include $(TOPDIR)/config.mk |
||||
|
||||
LIB = lib$(BOARD).a
|
||||
|
||||
OBJS = $(BOARD).o flash.o ezkit533.o
|
||||
|
||||
$(LIB): .depend $(OBJS) |
||||
$(AR) crv $@ $(OBJS)
|
||||
|
||||
#########################################################################
|
||||
|
||||
.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) |
||||
$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
|
||||
|
||||
sinclude .depend |
||||
|
||||
#########################################################################
|
||||
@ -0,0 +1,25 @@ |
||||
#
|
||||
# (C) Copyright 2001
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
TEXT_BASE = 0x01FC0000
|
||||
PLATFORM_CPPFLAGS += -I$(TOPDIR)
|
||||
@ -0,0 +1,71 @@ |
||||
/*
|
||||
* U-boot - ezkit533.c |
||||
* |
||||
* Copyright (c) 2005 blackfin.uclinux.org |
||||
* |
||||
* (C) Copyright 2000-2004 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#if defined(CONFIG_MISC_INIT_R) |
||||
#include "psd4256.h" |
||||
#endif |
||||
|
||||
int checkboard(void) |
||||
{ |
||||
printf("CPU: ADSP BF533 Rev.: 0.%d\n", *pCHIPID >> 28); |
||||
printf("Board: ADI BF533 EZ-Kit Lite board\n"); |
||||
printf(" Support: http://blackfin.uclinux.org/\n"); |
||||
printf(" Richard Klingler <richard@uclinux.net>\n"); |
||||
return 0; |
||||
} |
||||
|
||||
long int initdram(int board_type) |
||||
{ |
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
#ifdef DEBUG |
||||
int brate; |
||||
char *tmp = getenv("baudrate"); |
||||
brate = simple_strtoul(tmp, NULL, 16); |
||||
printf("Serial Port initialized with Baud rate = %x\n",brate); |
||||
printf("SDRAM attributes:\n"); |
||||
printf("tRCD %d SCLK Cycles,tRP %d SCLK Cycles,tRAS %d SCLK Cycles" |
||||
"tWR %d SCLK Cycles,CAS Latency %d SCLK cycles \n", |
||||
3, 3, 6, 2, 3); |
||||
printf("SDRAM Begin: 0x%x\n", CFG_SDRAM_BASE); |
||||
printf("Bank size = %d MB\n", CFG_MAX_RAM_SIZE >> 20); |
||||
#endif |
||||
gd->bd->bi_memstart = CFG_SDRAM_BASE; |
||||
gd->bd->bi_memsize = CFG_MAX_RAM_SIZE; |
||||
return CFG_MAX_RAM_SIZE; |
||||
} |
||||
|
||||
#if defined(CONFIG_MISC_INIT_R) |
||||
/* miscellaneous platform dependent initialisations */ |
||||
int misc_init_r(void) |
||||
{ |
||||
/* Set direction bits for Video en/decoder reset as output */ |
||||
*(volatile unsigned char *)(CFG_FLASH1_BASE + PSD_PORTA_DIR) = PSDA_VDEC_RST | PSDA_VENC_RST; |
||||
/* Deactivate Video en/decoder reset lines */ |
||||
*(volatile unsigned char *)(CFG_FLASH1_BASE + PSD_PORTA_DOUT) = PSDA_VDEC_RST | PSDA_VENC_RST; |
||||
} |
||||
#endif |
||||
@ -0,0 +1,130 @@ |
||||
/*
|
||||
* U-boot - flash-defines.h |
||||
* |
||||
* Copyright (c) 2005 blackfin.uclinux.org |
||||
* |
||||
* (C) Copyright 2000-2004 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#ifndef __FLASHDEFINES_H__ |
||||
#define __FLASHDEFINES_H__ |
||||
|
||||
#include <common.h> |
||||
|
||||
#define V_ULONG(a) (*(volatile unsigned long *)( a )) |
||||
#define V_BYTE(a) (*(volatile unsigned char *)( a )) |
||||
#define TRUE 0x1 |
||||
#define FALSE 0x0 |
||||
#define BUFFER_SIZE 0x80000 |
||||
#define NO_COMMAND 0 |
||||
#define GET_CODES 1 |
||||
#define RESET 2 |
||||
#define WRITE 3 |
||||
#define FILL 4 |
||||
#define ERASE_ALL 5 |
||||
#define ERASE_SECT 6 |
||||
#define READ 7 |
||||
#define GET_SECTNUM 8 |
||||
#define FLASH_START_L 0x0000 |
||||
#define FLASH_START_H 0x2000 |
||||
#define FLASH_TOT_SECT 40 |
||||
#define FLASH_SIZE 0x220000 |
||||
#define FLASH_MAN_ST 2 |
||||
#define CFG_FLASH0_BASE 0x20000000 |
||||
#define RESET_VAL 0xF0 |
||||
|
||||
|
||||
asm("#define FLASH_START_L 0x0000"); |
||||
asm("#define FLASH_START_H 0x2000"); |
||||
|
||||
flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; |
||||
|
||||
int get_codes(void); |
||||
int poll_toggle_bit(long lOffset); |
||||
void reset_flash(void); |
||||
int erase_flash(void); |
||||
int erase_block_flash(int,unsigned long); |
||||
void unlock_flash(long lOffset); |
||||
int write_data(long lStart, long lCount, long lStride, int *pnData); |
||||
int FillData(long lStart, long lCount, long lStride, int *pnData); |
||||
int read_data(long lStart, long lCount, long lStride, int *pnData); |
||||
int read_flash(long nOffset, int *pnValue); |
||||
int write_flash(long nOffset, int nValue); |
||||
void get_sector_number(long lOffset, int *pnSector); |
||||
int GetSectorProtectionStatus(flash_info_t * info, int nSector); |
||||
int GetOffset(int nBlock); |
||||
int AFP_NumSectors = 40; |
||||
long AFP_SectorSize1 = 0x10000; |
||||
int AFP_SectorSize2 = 0x4000; |
||||
|
||||
#define WRITESEQ1 0x0AAA |
||||
#define WRITESEQ2 0x0554 |
||||
#define WRITESEQ3 0x0AAA |
||||
#define WRITESEQ4 0x0AAA |
||||
#define WRITESEQ5 0x0554 |
||||
#define WRITESEQ6 0x0AAA |
||||
#define WRITEDATA1 0xaa |
||||
#define WRITEDATA2 0x55 |
||||
#define WRITEDATA3 0x80 |
||||
#define WRITEDATA4 0xaa |
||||
#define WRITEDATA5 0x55 |
||||
#define WRITEDATA6 0x10 |
||||
#define PriFlashABegin 0 |
||||
#define SecFlashABegin 32 |
||||
#define SecFlashBBegin 36 |
||||
#define PriFlashAOff 0x0 |
||||
#define PriFlashBOff 0x100000 |
||||
#define SecFlashAOff 0x200000 |
||||
#define SecFlashBOff 0x280000 |
||||
#define INVALIDLOCNSTART 0x20270000 |
||||
#define INVALIDLOCNEND 0x20280000 |
||||
#define BlockEraseVal 0x30 |
||||
#define UNLOCKDATA1 0xaa |
||||
#define UNLOCKDATA2 0x55 |
||||
#define UNLOCKDATA3 0xa0 |
||||
#define GETCODEDATA1 0xaa |
||||
#define GETCODEDATA2 0x55 |
||||
#define GETCODEDATA3 0x90 |
||||
#define SecFlashASec1Off 0x200000 |
||||
#define SecFlashASec2Off 0x204000 |
||||
#define SecFlashASec3Off 0x206000 |
||||
#define SecFlashASec4Off 0x208000 |
||||
#define SecFlashAEndOff 0x210000 |
||||
#define SecFlashBSec1Off 0x280000 |
||||
#define SecFlashBSec2Off 0x284000 |
||||
#define SecFlashBSec3Off 0x286000 |
||||
#define SecFlashBSec4Off 0x288000 |
||||
#define SecFlashBEndOff 0x290000 |
||||
|
||||
#define SECT32 32 |
||||
#define SECT33 33 |
||||
#define SECT34 34 |
||||
#define SECT35 35 |
||||
#define SECT36 36 |
||||
#define SECT37 37 |
||||
#define SECT38 38 |
||||
#define SECT39 39 |
||||
|
||||
#define FLASH_SUCCESS 0 |
||||
#define FLASH_FAIL -1 |
||||
|
||||
#endif |
||||
@ -0,0 +1,476 @@ |
||||
/*
|
||||
* U-boot - flash.c Flash driver for PSD4256GV |
||||
* |
||||
* Copyright (c) 2005 blackfin.uclinux.org |
||||
* This file is based on BF533EzFlash.c originally written by Analog Devices, Inc. |
||||
* |
||||
* (C) Copyright 2000-2004 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include "flash-defines.h" |
||||
|
||||
void flash_reset(void) |
||||
{ |
||||
reset_flash(); |
||||
} |
||||
|
||||
unsigned long flash_get_size(ulong baseaddr, flash_info_t * info, |
||||
int bank_flag) |
||||
{ |
||||
int id = 0, i = 0; |
||||
static int FlagDev = 1; |
||||
|
||||
id = get_codes(); |
||||
if(FlagDev) { |
||||
#ifdef DEBUG |
||||
printf("Device ID of the Flash is %x\n", id); |
||||
#endif |
||||
FlagDev = 0; |
||||
} |
||||
info->flash_id = id; |
||||
|
||||
switch (bank_flag) { |
||||
case 0: |
||||
for (i = PriFlashABegin; i < SecFlashABegin; i++) |
||||
info->start[i] = (baseaddr + (i * AFP_SectorSize1)); |
||||
info->size = 0x200000; |
||||
info->sector_count = 32; |
||||
break; |
||||
case 1: |
||||
info->start[0] = baseaddr + SecFlashASec1Off; |
||||
info->start[1] = baseaddr + SecFlashASec2Off; |
||||
info->start[2] = baseaddr + SecFlashASec3Off; |
||||
info->start[3] = baseaddr + SecFlashASec4Off; |
||||
info->size = 0x10000; |
||||
info->sector_count = 4; |
||||
break; |
||||
case 2: |
||||
info->start[0] = baseaddr + SecFlashBSec1Off; |
||||
info->start[1] = baseaddr + SecFlashBSec2Off; |
||||
info->start[2] = baseaddr + SecFlashBSec3Off; |
||||
info->start[3] = baseaddr + SecFlashBSec4Off; |
||||
info->size = 0x10000; |
||||
info->sector_count = 4; |
||||
break; |
||||
} |
||||
return (info->size); |
||||
} |
||||
|
||||
unsigned long flash_init(void) |
||||
{ |
||||
unsigned long size_b0, size_b1, size_b2; |
||||
int i; |
||||
|
||||
size_b0 = size_b1 = size_b2 = 0; |
||||
#ifdef DEBUG |
||||
printf("Flash Memory Start 0x%x\n", CFG_FLASH_BASE); |
||||
printf("Memory Map for the Flash\n"); |
||||
printf("0x20000000 - 0x200FFFFF Flash A Primary (1MB)\n"); |
||||
printf("0x20100000 - 0x201FFFFF Flash B Primary (1MB)\n"); |
||||
printf("0x20200000 - 0x2020FFFF Flash A Secondary (64KB)\n"); |
||||
printf("0x20280000 - 0x2028FFFF Flash B Secondary (64KB)\n"); |
||||
printf("Please type command flinfo for information on Sectors \n"); |
||||
#endif |
||||
for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) { |
||||
flash_info[i].flash_id = FLASH_UNKNOWN; |
||||
} |
||||
|
||||
size_b0 = flash_get_size(CFG_FLASH0_BASE, &flash_info[0], 0); |
||||
size_b1 = flash_get_size(CFG_FLASH0_BASE, &flash_info[1], 1); |
||||
size_b2 = flash_get_size(CFG_FLASH0_BASE, &flash_info[2], 2); |
||||
|
||||
if (flash_info[0].flash_id == FLASH_UNKNOWN || size_b0 == 0) { |
||||
printf("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", |
||||
size_b0, size_b0 >> 20); |
||||
} |
||||
|
||||
(void)flash_protect(FLAG_PROTECT_SET,CFG_FLASH0_BASE,(flash_info[0].start[2] - 1),&flash_info[0]); |
||||
|
||||
return (size_b0 + size_b1 + size_b2); |
||||
} |
||||
|
||||
void flash_print_info(flash_info_t * info) |
||||
{ |
||||
int i; |
||||
|
||||
if (info->flash_id == FLASH_UNKNOWN) { |
||||
printf("missing or unknown FLASH type\n"); |
||||
return; |
||||
} |
||||
|
||||
switch (info->flash_id) { |
||||
case FLASH_PSD4256GV: |
||||
printf("ST Microelectronics "); |
||||
break; |
||||
default: |
||||
printf("Unknown Vendor "); |
||||
break; |
||||
} |
||||
for (i = 0; i < info->sector_count; ++i) { |
||||
if ((i % 5) == 0) |
||||
printf("\n "); |
||||
printf(" %08lX%s", |
||||
info->start[i], |
||||
info->protect[i] ? " (RO)" : " "); |
||||
} |
||||
printf("\n"); |
||||
return; |
||||
} |
||||
|
||||
int flash_erase(flash_info_t * info, int s_first, int s_last) |
||||
{ |
||||
int cnt = 0,i; |
||||
int prot,sect; |
||||
|
||||
prot = 0; |
||||
for (sect = s_first; sect <= s_last; ++sect) { |
||||
if (info->protect[sect]) |
||||
prot++; |
||||
} |
||||
|
||||
if (prot) |
||||
printf ("- Warning: %d protected sectors will not be erased!\n", prot); |
||||
else |
||||
printf ("\n"); |
||||
|
||||
cnt = s_last - s_first + 1; |
||||
|
||||
if (cnt == FLASH_TOT_SECT) { |
||||
printf("Erasing flash, Please Wait \n"); |
||||
if(erase_flash() < 0) { |
||||
printf("Erasing flash failed \n"); |
||||
return FLASH_FAIL; |
||||
} |
||||
} else { |
||||
printf("Erasing Flash locations, Please Wait\n"); |
||||
for (i = s_first; i <= s_last; i++) { |
||||
if (info->protect[i] == 0) { /* not protected */ |
||||
if(erase_block_flash(i, info->start[i]) < 0) { |
||||
printf("Error Sector erasing \n"); |
||||
return FLASH_FAIL; |
||||
} |
||||
} |
||||
} |
||||
} |
||||
return FLASH_SUCCESS; |
||||
} |
||||
|
||||
int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt) |
||||
{ |
||||
int ret; |
||||
|
||||
ret = write_data(addr, cnt, 1, (int *) src); |
||||
if(ret == FLASH_FAIL) |
||||
return ERR_NOT_ERASED; |
||||
return FLASH_SUCCESS; |
||||
} |
||||
|
||||
|
||||
int write_data(long lStart, long lCount, long lStride, int *pnData) |
||||
{ |
||||
long i = 0; |
||||
int j = 0; |
||||
unsigned long ulOffset = lStart - CFG_FLASH_BASE; |
||||
int d; |
||||
int iShift = 0; |
||||
int iNumWords = 2; |
||||
int nLeftover = lCount % 4; |
||||
int nSector = 0; |
||||
|
||||
for (i = 0; (i < lCount / 4) && (i < BUFFER_SIZE); i++) { |
||||
for (iShift = 0, j = 0; (j < iNumWords); |
||||
j++, ulOffset += (lStride * 2)) { |
||||
if ((ulOffset >= INVALIDLOCNSTART) |
||||
&& (ulOffset < INVALIDLOCNEND)) { |
||||
printf("Invalid locations, Try writing to another location \n"); |
||||
return FLASH_FAIL; |
||||
} |
||||
get_sector_number(ulOffset, &nSector); |
||||
read_flash(ulOffset,&d); |
||||
if(d != 0xffff) { |
||||
printf("Flash not erased at offset 0x%x Please erase to reprogram \n",ulOffset); |
||||
return FLASH_FAIL; |
||||
} |
||||
unlock_flash(ulOffset); |
||||
if(write_flash(ulOffset, (pnData[i] >> iShift)) < 0) { |
||||
printf("Error programming the flash \n"); |
||||
return FLASH_FAIL; |
||||
} |
||||
iShift += 16; |
||||
} |
||||
} |
||||
if (nLeftover > 0) { |
||||
if ((ulOffset >= INVALIDLOCNSTART) |
||||
&& (ulOffset < INVALIDLOCNEND)) |
||||
return FLASH_FAIL; |
||||
get_sector_number(ulOffset, &nSector); |
||||
read_flash(ulOffset,&d); |
||||
if(d != 0xffff) { |
||||
printf("Flash already programmed. Please erase to reprogram \n"); |
||||
printf("uloffset = 0x%x \t d = 0x%x\n",ulOffset,d); |
||||
return FLASH_FAIL; |
||||
} |
||||
unlock_flash(ulOffset); |
||||
if(write_flash(ulOffset, pnData[i]) < 0) { |
||||
printf("Error programming the flash \n"); |
||||
return FLASH_FAIL; |
||||
} |
||||
} |
||||
return FLASH_SUCCESS; |
||||
} |
||||
|
||||
int read_data(long ulStart, long lCount, long lStride, int *pnData) |
||||
{ |
||||
long i = 0; |
||||
int j = 0; |
||||
long ulOffset = ulStart; |
||||
int iShift = 0; |
||||
int iNumWords = 2; |
||||
int nLeftover = lCount % 4; |
||||
int nHi, nLow; |
||||
int nSector = 0; |
||||
|
||||
for (i = 0; (i < lCount / 4) && (i < BUFFER_SIZE); i++) { |
||||
for (iShift = 0, j = 0; j < iNumWords; j += 2) { |
||||
if ((ulOffset >= INVALIDLOCNSTART) |
||||
&& (ulOffset < INVALIDLOCNEND)) |
||||
return FLASH_FAIL; |
||||
|
||||
get_sector_number(ulOffset, &nSector); |
||||
read_flash(ulOffset, &nLow); |
||||
ulOffset += (lStride * 2); |
||||
read_flash(ulOffset, &nHi); |
||||
ulOffset += (lStride * 2); |
||||
pnData[i] = (nHi << 16) | nLow; |
||||
} |
||||
} |
||||
if (nLeftover > 0) { |
||||
if ((ulOffset >= INVALIDLOCNSTART) |
||||
&& (ulOffset < INVALIDLOCNEND)) |
||||
return FLASH_FAIL; |
||||
|
||||
get_sector_number(ulOffset, &nSector); |
||||
read_flash(ulOffset, &pnData[i]); |
||||
} |
||||
return FLASH_SUCCESS; |
||||
} |
||||
|
||||
int write_flash(long nOffset, int nValue) |
||||
{ |
||||
long addr; |
||||
|
||||
addr = (CFG_FLASH_BASE + nOffset); |
||||
asm("ssync;"); |
||||
*(unsigned volatile short *) addr = nValue; |
||||
asm("ssync;"); |
||||
if(poll_toggle_bit(nOffset) < 0) |
||||
return FLASH_FAIL; |
||||
return FLASH_SUCCESS; |
||||
} |
||||
|
||||
int read_flash(long nOffset, int *pnValue) |
||||
{ |
||||
int nValue = 0x0; |
||||
long addr = (CFG_FLASH_BASE + nOffset); |
||||
|
||||
if (nOffset != 0x2) |
||||
reset_flash(); |
||||
asm("ssync;"); |
||||
nValue = *(volatile unsigned short *) addr; |
||||
asm("ssync;"); |
||||
*pnValue = nValue; |
||||
return TRUE; |
||||
} |
||||
|
||||
int poll_toggle_bit(long lOffset) |
||||
{ |
||||
unsigned int u1,u2; |
||||
unsigned long timeout = 0xFFFFFFFF; |
||||
volatile unsigned long *FB = (volatile unsigned long *)(0x20000000 + lOffset); |
||||
while(1) { |
||||
if(timeout < 0) |
||||
break; |
||||
u1 = *(volatile unsigned short *)FB; |
||||
u2 = *(volatile unsigned short *)FB; |
||||
if((u1 & 0x0040) == (u2 & 0x0040)) |
||||
return FLASH_SUCCESS; |
||||
if((u2 & 0x0020) == 0x0000) |
||||
continue; |
||||
u1 = *(volatile unsigned short *)FB; |
||||
if((u2 & 0x0040) == (u1 & 0x0040)) |
||||
return FLASH_SUCCESS; |
||||
else { |
||||
reset_flash(); |
||||
return FLASH_FAIL; |
||||
} |
||||
timeout--; |
||||
} |
||||
printf("Time out occured \n"); |
||||
if(timeout <0) return FLASH_FAIL; |
||||
} |
||||
|
||||
void reset_flash(void) |
||||
{ |
||||
write_flash(WRITESEQ1, RESET_VAL); |
||||
/* Wait for 10 micro seconds */ |
||||
udelay(10); |
||||
} |
||||
|
||||
int erase_flash(void) |
||||
{ |
||||
write_flash(WRITESEQ1, WRITEDATA1); |
||||
write_flash(WRITESEQ2, WRITEDATA2); |
||||
write_flash(WRITESEQ3, WRITEDATA3); |
||||
write_flash(WRITESEQ4, WRITEDATA4); |
||||
write_flash(WRITESEQ5, WRITEDATA5); |
||||
write_flash(WRITESEQ6, WRITEDATA6); |
||||
|
||||
if(poll_toggle_bit(0x0000) < 0) |
||||
return FLASH_FAIL; |
||||
|
||||
write_flash(SecFlashAOff + WRITESEQ1, WRITEDATA1); |
||||
write_flash(SecFlashAOff + WRITESEQ2, WRITEDATA2); |
||||
write_flash(SecFlashAOff + WRITESEQ3, WRITEDATA3); |
||||
write_flash(SecFlashAOff + WRITESEQ4, WRITEDATA4); |
||||
write_flash(SecFlashAOff + WRITESEQ5, WRITEDATA5); |
||||
write_flash(SecFlashAOff + WRITESEQ6, WRITEDATA6); |
||||
|
||||
if(poll_toggle_bit(SecFlashASec1Off) < 0) |
||||
return FLASH_FAIL; |
||||
|
||||
write_flash(PriFlashBOff + WRITESEQ1, WRITEDATA1); |
||||
write_flash(PriFlashBOff + WRITESEQ2, WRITEDATA2); |
||||
write_flash(PriFlashBOff + WRITESEQ3, WRITEDATA3); |
||||
write_flash(PriFlashBOff + WRITESEQ4, WRITEDATA4); |
||||
write_flash(PriFlashBOff + WRITESEQ5, WRITEDATA5); |
||||
write_flash(PriFlashBOff + WRITESEQ6, WRITEDATA6); |
||||
|
||||
if(poll_toggle_bit(PriFlashBOff) <0) |
||||
return FLASH_FAIL; |
||||
|
||||
write_flash(SecFlashBOff + WRITESEQ1, WRITEDATA1); |
||||
write_flash(SecFlashBOff + WRITESEQ2, WRITEDATA2); |
||||
write_flash(SecFlashBOff + WRITESEQ3, WRITEDATA3); |
||||
write_flash(SecFlashBOff + WRITESEQ4, WRITEDATA4); |
||||
write_flash(SecFlashBOff + WRITESEQ5, WRITEDATA5); |
||||
write_flash(SecFlashBOff + WRITESEQ6, WRITEDATA6); |
||||
|
||||
if(poll_toggle_bit(SecFlashBOff) < 0) |
||||
return FLASH_FAIL; |
||||
|
||||
return FLASH_SUCCESS; |
||||
} |
||||
|
||||
int erase_block_flash(int nBlock, unsigned long address) |
||||
{ |
||||
long ulSectorOff = 0x0; |
||||
|
||||
if ((nBlock < 0) || (nBlock > AFP_NumSectors)) |
||||
return FALSE; |
||||
|
||||
ulSectorOff = (address - CFG_FLASH_BASE); |
||||
|
||||
write_flash((WRITESEQ1 | ulSectorOff), WRITEDATA1); |
||||
write_flash((WRITESEQ2 | ulSectorOff), WRITEDATA2); |
||||
write_flash((WRITESEQ3 | ulSectorOff), WRITEDATA3); |
||||
write_flash((WRITESEQ4 | ulSectorOff), WRITEDATA4); |
||||
write_flash((WRITESEQ5 | ulSectorOff), WRITEDATA5); |
||||
|
||||
write_flash(ulSectorOff, BlockEraseVal); |
||||
|
||||
if(poll_toggle_bit(ulSectorOff) < 0) |
||||
return FLASH_FAIL; |
||||
|
||||
return FLASH_SUCCESS; |
||||
} |
||||
|
||||
void unlock_flash(long ulOffset) |
||||
{ |
||||
unsigned long ulOffsetAddr = ulOffset; |
||||
ulOffsetAddr &= 0xFFFF0000; |
||||
|
||||
write_flash((WRITESEQ1 | ulOffsetAddr), UNLOCKDATA1); |
||||
write_flash((WRITESEQ2 | ulOffsetAddr), UNLOCKDATA2); |
||||
write_flash((WRITESEQ3 | ulOffsetAddr), UNLOCKDATA3); |
||||
} |
||||
|
||||
int get_codes() |
||||
{ |
||||
int dev_id = 0; |
||||
|
||||
write_flash(WRITESEQ1, GETCODEDATA1); |
||||
write_flash(WRITESEQ2, GETCODEDATA2); |
||||
write_flash(WRITESEQ3, GETCODEDATA3); |
||||
|
||||
read_flash(0x0002, &dev_id); |
||||
dev_id &= 0x00FF; |
||||
|
||||
reset_flash(); |
||||
|
||||
return dev_id; |
||||
} |
||||
|
||||
void get_sector_number(long ulOffset, int *pnSector) |
||||
{ |
||||
int nSector = 0; |
||||
|
||||
if (ulOffset >= SecFlashAOff) { |
||||
if ((ulOffset < SecFlashASec1Off) |
||||
&& (ulOffset < SecFlashASec2Off)) { |
||||
nSector = SECT32; |
||||
} else if ((ulOffset >= SecFlashASec2Off) |
||||
&& (ulOffset < SecFlashASec3Off)) { |
||||
nSector = SECT33; |
||||
} else if ((ulOffset >= SecFlashASec3Off) |
||||
&& (ulOffset < SecFlashASec4Off)) { |
||||
nSector = SECT34; |
||||
} else if ((ulOffset >= SecFlashASec4Off) |
||||
&& (ulOffset < SecFlashAEndOff)) { |
||||
nSector = SECT35; |
||||
} |
||||
} else if (ulOffset >= SecFlashBOff) { |
||||
if ((ulOffset < SecFlashBSec1Off) |
||||
&& (ulOffset < SecFlashBSec2Off)) { |
||||
nSector = SECT36; |
||||
} |
||||
if ((ulOffset < SecFlashBSec2Off) |
||||
&& (ulOffset < SecFlashBSec3Off)) { |
||||
nSector = SECT37; |
||||
} |
||||
if ((ulOffset < SecFlashBSec3Off) |
||||
&& (ulOffset < SecFlashBSec4Off)) { |
||||
nSector = SECT38; |
||||
} |
||||
if ((ulOffset < SecFlashBSec4Off) |
||||
&& (ulOffset < SecFlashBEndOff)) { |
||||
nSector = SECT39; |
||||
} |
||||
} else if ((ulOffset >= PriFlashAOff) && (ulOffset < SecFlashAOff)) { |
||||
nSector = ulOffset & 0xffff0000; |
||||
nSector = ulOffset >> 16; |
||||
nSector = nSector & 0x000ff; |
||||
} |
||||
|
||||
if ((nSector >= 0) && (nSector < AFP_NumSectors)) { |
||||
*pnSector = nSector; |
||||
} |
||||
} |
||||
@ -0,0 +1,67 @@ |
||||
/*
|
||||
* U-boot - psd4256.h |
||||
* |
||||
* Copyright (c) 2005 blackfin.uclinux.org |
||||
* |
||||
* (C) Copyright 2000-2004 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
/*
|
||||
* Flash A/B Port A configuration registers. |
||||
* Addresses are offset values to CFG_FLASH1_BASE |
||||
* for Flash A and CFG_FLASH2_BASE for Flash B. |
||||
*/ |
||||
|
||||
#define PSD_PORTA_DIN 0x070000 |
||||
#define PSD_PORTA_DOUT 0x070004 |
||||
#define PSD_PORTA_DIR 0x070006 |
||||
|
||||
/*
|
||||
* Flash A/B Port B configuration registers |
||||
* Addresses are offset values to CFG_FLASH1_BASE |
||||
* for Flash A and CFG_FLASH2_BASE for Flash B. |
||||
*/ |
||||
|
||||
#define PSD_PORTB_DIN 0x070001 |
||||
#define PSD_PORTB_DOUT 0x070005 |
||||
#define PSD_PORTB_DIR 0x070007 |
||||
|
||||
/*
|
||||
* Flash A Port A Bit definitions |
||||
*/ |
||||
|
||||
#define PSDA_PPICLK1 0x20 /* PPI Clock select bit 1 */ |
||||
#define PSDA_PPICLK0 0x10 /* PPI Clock select bit 0 */ |
||||
#define PSDA_VDEC_RST 0x08 /* Video decoder reset, 0 = RESET */ |
||||
#define PSDA_VENC_RST 0x04 /* Video encoder reset, 0 = RESET */ |
||||
#define PSDA_CODEC_RST 0x01 /* Codec reset, 0 = RESET */ |
||||
|
||||
/*
|
||||
* Flash A Port B Bit definitions |
||||
*/ |
||||
|
||||
#define PSDA_LED9 0x20 /* LED 9, 1 = LED ON */ |
||||
#define PSDA_LED8 0x10 /* LED 8, 1 = LED ON */ |
||||
#define PSDA_LED7 0x08 /* LED 7, 1 = LED ON */ |
||||
#define PSDA_LED6 0x04 /* LED 6, 1 = LED ON */ |
||||
#define PSDA_LED5 0x02 /* LED 5, 1 = LED ON */ |
||||
#define PSDA_LED4 0x01 /* LED 4, 1 = LED ON */ |
||||
@ -0,0 +1,148 @@ |
||||
/* |
||||
* U-boot - u-boot.lds |
||||
* |
||||
* Copyright (c) 2005 blackfin.uclinux.org |
||||
* |
||||
* (C) Copyright 2000-2004 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
OUTPUT_ARCH(bfin) |
||||
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); |
||||
/* Do we need any of these for elf? |
||||
__DYNAMIC = 0; */ |
||||
SECTIONS |
||||
{ |
||||
/* Read-only sections, merged into text segment: */ |
||||
. = + SIZEOF_HEADERS; |
||||
.interp : { *(.interp) } |
||||
.hash : { *(.hash) } |
||||
.dynsym : { *(.dynsym) } |
||||
.dynstr : { *(.dynstr) } |
||||
.rel.text : { *(.rel.text) } |
||||
.rela.text : { *(.rela.text) } |
||||
.rel.data : { *(.rel.data) } |
||||
.rela.data : { *(.rela.data) } |
||||
.rel.rodata : { *(.rel.rodata) } |
||||
.rela.rodata : { *(.rela.rodata) } |
||||
.rel.got : { *(.rel.got) } |
||||
.rela.got : { *(.rela.got) } |
||||
.rel.ctors : { *(.rel.ctors) } |
||||
.rela.ctors : { *(.rela.ctors) } |
||||
.rel.dtors : { *(.rel.dtors) } |
||||
.rela.dtors : { *(.rela.dtors) } |
||||
.rel.bss : { *(.rel.bss) } |
||||
.rela.bss : { *(.rela.bss) } |
||||
.rel.plt : { *(.rel.plt) } |
||||
.rela.plt : { *(.rela.plt) } |
||||
.init : { *(.init) } |
||||
.plt : { *(.plt) } |
||||
.text : |
||||
{ |
||||
/* WARNING - the following is hand-optimized to fit within */ |
||||
/* the sector before the environment sector. If it throws */ |
||||
/* an error during compilation remove an object here to get */ |
||||
/* it linked after the configuration sector. */ |
||||
|
||||
cpu/bf533/start.o (.text) |
||||
cpu/bf533/start1.o (.text) |
||||
cpu/bf533/traps.o (.text) |
||||
cpu/bf533/interrupt.o (.text) |
||||
cpu/bf533/serial.o (.text) |
||||
common/dlmalloc.o (.text) |
||||
lib_generic/vsprintf.o (.text) |
||||
lib_generic/crc32.o (.text) |
||||
lib_generic/zlib.o (.text) |
||||
board/ezkit533/ezkit533.o (.text) |
||||
|
||||
. = DEFINED(env_offset) ? env_offset : .; |
||||
common/environment.o (.text) |
||||
|
||||
*(.text) |
||||
*(.fixup) |
||||
*(.got1) |
||||
} |
||||
_etext = .; |
||||
PROVIDE (etext = .); |
||||
.rodata : |
||||
{ |
||||
*(.rodata) |
||||
*(.rodata1) |
||||
*(.rodata.str1.4) |
||||
} |
||||
.fini : { *(.fini) } =0 |
||||
.ctors : { *(.ctors) } |
||||
.dtors : { *(.dtors) } |
||||
|
||||
/* Read-write section, merged into data segment: */ |
||||
. = (. + 0x00FF) & 0xFFFFFF00; |
||||
_erotext = .; |
||||
PROVIDE (erotext = .); |
||||
.reloc : |
||||
{ |
||||
*(.got) |
||||
_GOT2_TABLE_ = .; |
||||
*(.got2) |
||||
_FIXUP_TABLE_ = .; |
||||
*(.fixup) |
||||
} |
||||
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; |
||||
__fixup_entries = (. - _FIXUP_TABLE_)>>2; |
||||
|
||||
.data : |
||||
{ |
||||
*(.data) |
||||
*(.data1) |
||||
*(.sdata) |
||||
*(.sdata2) |
||||
*(.dynamic) |
||||
CONSTRUCTORS |
||||
} |
||||
_edata = .; |
||||
PROVIDE (edata = .); |
||||
|
||||
__u_boot_cmd_start = .; |
||||
.u_boot_cmd : { *(.u_boot_cmd) } |
||||
__u_boot_cmd_end = .; |
||||
|
||||
|
||||
__start___ex_table = .; |
||||
__ex_table : { *(__ex_table) } |
||||
__stop___ex_table = .; |
||||
|
||||
. = ALIGN(256); |
||||
__init_begin = .; |
||||
.text.init : { *(.text.init) } |
||||
.data.init : { *(.data.init) } |
||||
. = ALIGN(256); |
||||
__init_end = .; |
||||
|
||||
__bss_start = .; |
||||
.bss : |
||||
{ |
||||
*(.sbss) *(.scommon) |
||||
*(.dynbss) |
||||
*(.bss) |
||||
*(COMMON) |
||||
} |
||||
_end = . ; |
||||
PROVIDE (end = .); |
||||
} |
||||
@ -0,0 +1,37 @@ |
||||
/*
|
||||
* (C) Copyright 2004 |
||||
* Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#define SDRAM_DDR 1 /* is DDR */ |
||||
|
||||
#if defined(CONFIG_MPC5200) |
||||
/* Settings for XLB = 132 MHz */ |
||||
#define SDRAM_MODE 0x018D0000 |
||||
#define SDRAM_EMODE 0x40090000 |
||||
#define SDRAM_CONTROL 0x704f0f00 |
||||
#define SDRAM_CONFIG1 0x73722930 |
||||
#define SDRAM_CONFIG2 0x47770000 |
||||
#define SDRAM_TAPDELAY 0x10000000 |
||||
|
||||
#else |
||||
#error CONFIG_MPC5200 not defined |
||||
#endif |
||||
@ -0,0 +1,46 @@ |
||||
#
|
||||
# (C) Copyright 2003-2006
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
include $(TOPDIR)/config.mk |
||||
|
||||
LIB = lib$(BOARD).a
|
||||
|
||||
OBJS := $(BOARD).o
|
||||
|
||||
$(LIB): $(OBJS) $(SOBJS) |
||||
$(AR) crv $@ $(OBJS)
|
||||
|
||||
clean: |
||||
rm -f $(SOBJS) $(OBJS)
|
||||
|
||||
distclean: clean |
||||
rm -f $(LIB) core *.bak .depend
|
||||
|
||||
#########################################################################
|
||||
|
||||
.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) |
||||
$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
|
||||
|
||||
-include .depend |
||||
|
||||
#########################################################################
|
||||
@ -0,0 +1,43 @@ |
||||
#
|
||||
# (C) Copyright 2003-2006
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
#
|
||||
# MCC200 board:
|
||||
#
|
||||
# Valid values for TEXT_BASE are:
|
||||
#
|
||||
# 0xFFF00000 boot high (standard configuration)
|
||||
# 0xFE000000 boot low
|
||||
# 0x00100000 boot from RAM (for testing only)
|
||||
#
|
||||
|
||||
sinclude $(TOPDIR)/board/$(BOARDDIR)/config.tmp |
||||
|
||||
ifndef TEXT_BASE |
||||
## Standard: boot high
|
||||
TEXT_BASE = 0xFFF00000
|
||||
## For testing: boot from RAM
|
||||
# TEXT_BASE = 0x00100000
|
||||
endif |
||||
|
||||
PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board
|
||||
@ -0,0 +1,276 @@ |
||||
/*
|
||||
* (C) Copyright 2003-2006 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* (C) Copyright 2004 |
||||
* Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <mpc5xxx.h> |
||||
#include <pci.h> |
||||
|
||||
#include "mt48lc8m32b2-6-7.h" |
||||
|
||||
extern flash_info_t flash_info[]; /* FLASH chips info */ |
||||
|
||||
ulong flash_get_size (ulong base, int banknum); |
||||
|
||||
#ifndef CFG_RAMBOOT |
||||
static void sdram_start (int hi_addr) |
||||
{ |
||||
long hi_addr_bit = hi_addr ? 0x01000000 : 0; |
||||
|
||||
/* unlock mode register */ |
||||
*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit; |
||||
__asm__ volatile ("sync"); |
||||
|
||||
/* precharge all banks */ |
||||
*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit; |
||||
__asm__ volatile ("sync"); |
||||
|
||||
#if SDRAM_DDR |
||||
/* set mode register: extended mode */ |
||||
*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE; |
||||
__asm__ volatile ("sync"); |
||||
|
||||
/* set mode register: reset DLL */ |
||||
*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000; |
||||
__asm__ volatile ("sync"); |
||||
#endif |
||||
|
||||
/* precharge all banks */ |
||||
*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit; |
||||
__asm__ volatile ("sync"); |
||||
|
||||
/* auto refresh */ |
||||
*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit; |
||||
__asm__ volatile ("sync"); |
||||
|
||||
/* set mode register */ |
||||
*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE; |
||||
__asm__ volatile ("sync"); |
||||
|
||||
/* normal operation */ |
||||
*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit; |
||||
__asm__ volatile ("sync"); |
||||
} |
||||
#endif |
||||
|
||||
/*
|
||||
* ATTENTION: Although partially referenced initdram does NOT make real use |
||||
* use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE |
||||
* is something else than 0x00000000. |
||||
*/ |
||||
|
||||
long int initdram (int board_type) |
||||
{ |
||||
ulong dramsize = 0; |
||||
ulong dramsize2 = 0; |
||||
#ifndef CFG_RAMBOOT |
||||
ulong test1, test2; |
||||
|
||||
/* setup SDRAM chip selects */ |
||||
*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e;/* 2G at 0x0 */ |
||||
*(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000;/* disabled */ |
||||
__asm__ volatile ("sync"); |
||||
|
||||
/* setup config registers */ |
||||
*(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1; |
||||
*(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2; |
||||
__asm__ volatile ("sync"); |
||||
|
||||
#if SDRAM_DDR |
||||
/* set tap delay */ |
||||
*(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY; |
||||
__asm__ volatile ("sync"); |
||||
#endif |
||||
|
||||
/* find RAM size using SDRAM CS0 only */ |
||||
sdram_start(0); |
||||
test1 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000); |
||||
sdram_start(1); |
||||
test2 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000); |
||||
if (test1 > test2) { |
||||
sdram_start(0); |
||||
dramsize = test1; |
||||
} else { |
||||
dramsize = test2; |
||||
} |
||||
|
||||
/* memory smaller than 1MB is impossible */ |
||||
if (dramsize < (1 << 20)) { |
||||
dramsize = 0; |
||||
} |
||||
|
||||
/* set SDRAM CS0 size according to the amount of RAM found */ |
||||
if (dramsize > 0) { |
||||
*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1; |
||||
} else { |
||||
*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */ |
||||
} |
||||
|
||||
/* let SDRAM CS1 start right after CS0 */ |
||||
*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */ |
||||
|
||||
/* find RAM size using SDRAM CS1 only */ |
||||
if (!dramsize) |
||||
sdram_start(0); |
||||
test2 = test1 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x80000000); |
||||
if (!dramsize) { |
||||
sdram_start(1); |
||||
test2 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x80000000); |
||||
} |
||||
if (test1 > test2) { |
||||
sdram_start(0); |
||||
dramsize2 = test1; |
||||
} else { |
||||
dramsize2 = test2; |
||||
} |
||||
|
||||
/* memory smaller than 1MB is impossible */ |
||||
if (dramsize2 < (1 << 20)) { |
||||
dramsize2 = 0; |
||||
} |
||||
|
||||
/* set SDRAM CS1 size according to the amount of RAM found */ |
||||
if (dramsize2 > 0) { |
||||
*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize |
||||
| (0x13 + __builtin_ffs(dramsize2 >> 20) - 1); |
||||
} else { |
||||
*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */ |
||||
} |
||||
|
||||
#else /* CFG_RAMBOOT */ |
||||
|
||||
/* retrieve size of memory connected to SDRAM CS0 */ |
||||
dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF; |
||||
if (dramsize >= 0x13) { |
||||
dramsize = (1 << (dramsize - 0x13)) << 20; |
||||
} else { |
||||
dramsize = 0; |
||||
} |
||||
|
||||
/* retrieve size of memory connected to SDRAM CS1 */ |
||||
dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF; |
||||
if (dramsize2 >= 0x13) { |
||||
dramsize2 = (1 << (dramsize2 - 0x13)) << 20; |
||||
} else { |
||||
dramsize2 = 0; |
||||
} |
||||
|
||||
#endif /* CFG_RAMBOOT */ |
||||
|
||||
return dramsize + dramsize2; |
||||
} |
||||
|
||||
int checkboard (void) |
||||
{ |
||||
puts ("Board: MCC200\n"); |
||||
return 0; |
||||
} |
||||
|
||||
int misc_init_r (void) |
||||
{ |
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
/*
|
||||
* Adjust flash start and offset to detected values |
||||
*/ |
||||
gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize; |
||||
gd->bd->bi_flashoffset = 0; |
||||
|
||||
/*
|
||||
* Check if boot FLASH isn't max size |
||||
*/ |
||||
if (gd->bd->bi_flashsize < (0 - CFG_FLASH_BASE)) { |
||||
/* adjust mapping */ |
||||
*(vu_long *)MPC5XXX_BOOTCS_START = *(vu_long *)MPC5XXX_CS0_START = |
||||
START_REG(gd->bd->bi_flashstart); |
||||
*(vu_long *)MPC5XXX_BOOTCS_STOP = *(vu_long *)MPC5XXX_CS0_STOP = |
||||
STOP_REG(gd->bd->bi_flashstart, gd->bd->bi_flashsize); |
||||
|
||||
/*
|
||||
* Re-check to get correct base address |
||||
*/ |
||||
flash_get_size(gd->bd->bi_flashstart, CFG_MAX_FLASH_BANKS - 1); |
||||
|
||||
/*
|
||||
* Re-do flash protection upon new addresses |
||||
*/ |
||||
flash_protect (FLAG_PROTECT_CLEAR, |
||||
gd->bd->bi_flashstart, 0xffffffff, |
||||
&flash_info[CFG_MAX_FLASH_BANKS - 1]); |
||||
|
||||
/* Monitor protection ON by default */ |
||||
flash_protect (FLAG_PROTECT_SET, |
||||
CFG_MONITOR_BASE, CFG_MONITOR_BASE + monitor_flash_len - 1, |
||||
&flash_info[CFG_MAX_FLASH_BANKS - 1]); |
||||
|
||||
/* Environment protection ON by default */ |
||||
flash_protect (FLAG_PROTECT_SET, |
||||
CFG_ENV_ADDR, |
||||
CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1, |
||||
&flash_info[CFG_MAX_FLASH_BANKS - 1]); |
||||
|
||||
/* Redundant environment protection ON by default */ |
||||
flash_protect (FLAG_PROTECT_SET, |
||||
CFG_ENV_ADDR_REDUND, |
||||
CFG_ENV_ADDR_REDUND + CFG_ENV_SIZE_REDUND - 1, |
||||
&flash_info[CFG_MAX_FLASH_BANKS - 1]); |
||||
} |
||||
|
||||
return (0); |
||||
} |
||||
|
||||
#ifdef CONFIG_PCI |
||||
static struct pci_controller hose; |
||||
|
||||
extern void pci_mpc5xxx_init(struct pci_controller *); |
||||
|
||||
void pci_init_board(void) |
||||
{ |
||||
pci_mpc5xxx_init(&hose); |
||||
} |
||||
#endif |
||||
|
||||
#if defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) |
||||
|
||||
void init_ide_reset (void) |
||||
{ |
||||
debug ("init_ide_reset\n"); |
||||
|
||||
} |
||||
|
||||
void ide_set_reset (int idereset) |
||||
{ |
||||
debug ("ide_reset(%d)\n", idereset); |
||||
|
||||
} |
||||
#endif /* defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) */ |
||||
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_DOC) |
||||
extern void doc_probe (ulong physadr); |
||||
void doc_init (void) |
||||
{ |
||||
doc_probe (CFG_DOC_BASE); |
||||
} |
||||
#endif |
||||
@ -0,0 +1,37 @@ |
||||
/*
|
||||
* (C) Copyright 2004 |
||||
* Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#define SDRAM_DDR 1 /* is DDR */ |
||||
|
||||
#if defined(CONFIG_MPC5200) |
||||
/* Settings for XLB = 132 MHz */ |
||||
#define SDRAM_MODE 0x018D0000 |
||||
#define SDRAM_EMODE 0x40090000 |
||||
#define SDRAM_CONTROL 0x714f0f00 |
||||
#define SDRAM_CONFIG1 0x73722930 |
||||
#define SDRAM_CONFIG2 0x47770000 |
||||
#define SDRAM_TAPDELAY 0x10000000 |
||||
|
||||
#else |
||||
#error CONFIG_MPC5200 not defined |
||||
#endif |
||||
@ -0,0 +1,43 @@ |
||||
/*
|
||||
* (C) Copyright 2004 |
||||
* Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#define SDRAM_DDR 0 /* is SDR */ |
||||
|
||||
#if defined(CONFIG_MPC5200) |
||||
/* Settings for XLB = 132 MHz */ |
||||
#define SDRAM_MODE 0x00CD0000 |
||||
#define SDRAM_CONTROL 0x504F0000 |
||||
#define SDRAM_CONFIG1 0xD2322800 |
||||
#define SDRAM_CONFIG2 0x8AD70000 |
||||
|
||||
#elif defined(CONFIG_MGT5100) |
||||
/* Settings for XLB = 66 MHz */ |
||||
#define SDRAM_MODE 0x008D0000 |
||||
#define SDRAM_CONTROL 0x504F0000 |
||||
#define SDRAM_CONFIG1 0xC2222600 |
||||
#define SDRAM_CONFIG2 0x88B70004 |
||||
#define SDRAM_ADDRSEL 0x02000000 |
||||
|
||||
#else |
||||
#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined |
||||
#endif |
||||
@ -0,0 +1,12 @@ |
||||
/*
|
||||
* Configuration Registers for the MT48LC8M32B2 SDRAM on the MPC5200 platform |
||||
*/ |
||||
|
||||
#define SDRAM_DDR 0 /* is SDR */ |
||||
|
||||
/* Settings for XLB = 132 MHz */ |
||||
|
||||
#define SDRAM_MODE 0x008d0000 /* CL-3 BURST-8 -> Mode Register MBAR + 0x0100 */ |
||||
#define SDRAM_CONTROL 0x504f0000 /* Control Register MBAR + 0x0104 */ |
||||
#define SDRAM_CONFIG1 0xc2222900 /* Delays between commands -> Configuration Register 1 MBAR + 0x0108 */ |
||||
#define SDRAM_CONFIG2 0x88c70000 /* Delays between commands -> Configuration Register 2 MBAR + 0x010C */ |
||||
@ -0,0 +1,125 @@ |
||||
/* |
||||
* (C) Copyright 2003-2006 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
OUTPUT_ARCH(powerpc) |
||||
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); |
||||
/* Do we need any of these for elf? |
||||
__DYNAMIC = 0; */ |
||||
SECTIONS |
||||
{ |
||||
/* Read-only sections, merged into text segment: */ |
||||
. = + SIZEOF_HEADERS; |
||||
.interp : { *(.interp) } |
||||
.hash : { *(.hash) } |
||||
.dynsym : { *(.dynsym) } |
||||
.dynstr : { *(.dynstr) } |
||||
.rel.text : { *(.rel.text) } |
||||
.rela.text : { *(.rela.text) } |
||||
.rel.data : { *(.rel.data) } |
||||
.rela.data : { *(.rela.data) } |
||||
.rel.rodata : { *(.rel.rodata) } |
||||
.rela.rodata : { *(.rela.rodata) } |
||||
.rel.got : { *(.rel.got) } |
||||
.rela.got : { *(.rela.got) } |
||||
.rel.ctors : { *(.rel.ctors) } |
||||
.rela.ctors : { *(.rela.ctors) } |
||||
.rel.dtors : { *(.rel.dtors) } |
||||
.rela.dtors : { *(.rela.dtors) } |
||||
.rel.bss : { *(.rel.bss) } |
||||
.rela.bss : { *(.rela.bss) } |
||||
.rel.plt : { *(.rel.plt) } |
||||
.rela.plt : { *(.rela.plt) } |
||||
.init : { *(.init) } |
||||
.plt : { *(.plt) } |
||||
.text : |
||||
{ |
||||
cpu/mpc5xxx/start.o (.text) |
||||
*(.text) |
||||
*(.fixup) |
||||
*(.got1) |
||||
. = ALIGN(16); |
||||
*(.rodata) |
||||
*(.rodata1) |
||||
*(.rodata.str1.4) |
||||
*(.eh_frame) |
||||
} |
||||
.fini : { *(.fini) } =0 |
||||
.ctors : { *(.ctors) } |
||||
.dtors : { *(.dtors) } |
||||
|
||||
/* Read-write section, merged into data segment: */ |
||||
. = (. + 0x0FFF) & 0xFFFFF000; |
||||
_erotext = .; |
||||
PROVIDE (erotext = .); |
||||
.reloc : |
||||
{ |
||||
*(.got) |
||||
_GOT2_TABLE_ = .; |
||||
*(.got2) |
||||
_FIXUP_TABLE_ = .; |
||||
*(.fixup) |
||||
} |
||||
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; |
||||
__fixup_entries = (. - _FIXUP_TABLE_) >> 2; |
||||
|
||||
.data : |
||||
{ |
||||
*(.data) |
||||
*(.data1) |
||||
*(.sdata) |
||||
*(.sdata2) |
||||
*(.dynamic) |
||||
CONSTRUCTORS |
||||
} |
||||
_edata = .; |
||||
PROVIDE (edata = .); |
||||
|
||||
. = .; |
||||
__u_boot_cmd_start = .; |
||||
.u_boot_cmd : { *(.u_boot_cmd) } |
||||
__u_boot_cmd_end = .; |
||||
|
||||
|
||||
. = .; |
||||
__start___ex_table = .; |
||||
__ex_table : { *(__ex_table) } |
||||
__stop___ex_table = .; |
||||
|
||||
. = ALIGN(4096); |
||||
__init_begin = .; |
||||
.text.init : { *(.text.init) } |
||||
.data.init : { *(.data.init) } |
||||
. = ALIGN(4096); |
||||
__init_end = .; |
||||
|
||||
__bss_start = .; |
||||
.bss : |
||||
{ |
||||
*(.sbss) *(.scommon) |
||||
*(.dynbss) |
||||
*(.bss) |
||||
*(COMMON) |
||||
} |
||||
_end = . ; |
||||
PROVIDE (end = .); |
||||
} |
||||
@ -0,0 +1,46 @@ |
||||
#
|
||||
# (C) Copyright 2006
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
include $(TOPDIR)/config.mk |
||||
|
||||
LIB = lib$(BOARD).a
|
||||
|
||||
OBJS := $(BOARD).o
|
||||
|
||||
$(LIB): $(OBJS) $(SOBJS) |
||||
$(AR) crv $@ $(OBJS)
|
||||
|
||||
clean: |
||||
rm -f $(SOBJS) $(OBJS)
|
||||
|
||||
distclean: clean |
||||
rm -f $(LIB) core *.bak .depend
|
||||
|
||||
#########################################################################
|
||||
|
||||
.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) |
||||
$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
|
||||
|
||||
-include .depend |
||||
|
||||
#########################################################################
|
||||
@ -0,0 +1,28 @@ |
||||
#
|
||||
# (C) Copyright 2006
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
#
|
||||
# MPC8349EMDS
|
||||
#
|
||||
|
||||
TEXT_BASE = 0xFE000000
|
||||
@ -0,0 +1,602 @@ |
||||
/*
|
||||
* (C) Copyright 2006 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
* |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <ioports.h> |
||||
#include <mpc83xx.h> |
||||
#include <asm/mpc8349_pci.h> |
||||
#include <i2c.h> |
||||
#include <spd.h> |
||||
#include <miiphy.h> |
||||
#include <command.h> |
||||
#if defined(CONFIG_PCI) |
||||
#include <pci.h> |
||||
#endif |
||||
#if defined(CONFIG_SPD_EEPROM) |
||||
#include <spd_sdram.h> |
||||
#endif |
||||
int fixed_sdram(void); |
||||
void sdram_init(void); |
||||
|
||||
#if defined(CONFIG_DDR_ECC) && defined(CONFIG_MPC83XX) |
||||
void ddr_enable_ecc(unsigned int dram_size); |
||||
#endif |
||||
|
||||
int board_early_init_f (void) |
||||
{ |
||||
volatile u8* bcsr = (volatile u8*)CFG_BCSR; |
||||
|
||||
/* Enable flash write */ |
||||
bcsr[1] &= ~0x01; |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
#define ns2clk(ns) (ns / (1000000000 / CONFIG_8349_CLKIN) + 1) |
||||
|
||||
long int initdram (int board_type) |
||||
{ |
||||
volatile immap_t *im = (immap_t *)CFG_IMMRBAR; |
||||
u32 msize = 0; |
||||
|
||||
if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im) |
||||
return -1; |
||||
|
||||
puts("Initializing\n"); |
||||
|
||||
/* DDR SDRAM - Main SODIMM */ |
||||
im->sysconf.ddrlaw[0].bar = CFG_DDR_BASE & LAWBAR_BAR; |
||||
#if defined(CONFIG_SPD_EEPROM) |
||||
msize = spd_sdram(); |
||||
#else |
||||
msize = fixed_sdram(); |
||||
#endif |
||||
/*
|
||||
* Initialize SDRAM if it is on local bus. |
||||
*/ |
||||
sdram_init(); |
||||
|
||||
#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) |
||||
/*
|
||||
* Initialize and enable DDR ECC. |
||||
*/ |
||||
ddr_enable_ecc(msize * 1024 * 1024); |
||||
#endif |
||||
puts(" DDR RAM: "); |
||||
/* return total bus SDRAM size(bytes) -- DDR */ |
||||
return (msize * 1024 * 1024); |
||||
} |
||||
|
||||
#if !defined(CONFIG_SPD_EEPROM) |
||||
/*************************************************************************
|
||||
* fixed sdram init -- doesn't use serial presence detect. |
||||
************************************************************************/ |
||||
int fixed_sdram(void) |
||||
{ |
||||
volatile immap_t *im = (immap_t *)CFG_IMMRBAR; |
||||
u32 msize = 0; |
||||
u32 ddr_size; |
||||
u32 ddr_size_log2; |
||||
|
||||
msize = CFG_DDR_SIZE; |
||||
for (ddr_size = msize << 20, ddr_size_log2 = 0; |
||||
(ddr_size > 1); |
||||
ddr_size = ddr_size>>1, ddr_size_log2++) { |
||||
if (ddr_size & 1) { |
||||
return -1; |
||||
} |
||||
} |
||||
im->sysconf.ddrlaw[0].bar = ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff); |
||||
im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE); |
||||
|
||||
#if (CFG_DDR_SIZE != 256) |
||||
#warning Currenly any ddr size other than 256 is not supported |
||||
#endif |
||||
im->ddr.csbnds[2].csbnds = 0x0000000f; |
||||
im->ddr.cs_config[2] = CFG_DDR_CONFIG; |
||||
|
||||
/* currently we use only one CS, so disable the other banks */
|
||||
im->ddr.cs_config[0] = 0; |
||||
im->ddr.cs_config[1] = 0; |
||||
im->ddr.cs_config[3] = 0; |
||||
|
||||
im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1; |
||||
im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2; |
||||
|
||||
im->ddr.sdram_cfg = |
||||
SDRAM_CFG_SREN |
||||
#if defined(CONFIG_DDR_2T_TIMING) |
||||
| SDRAM_CFG_2T_EN |
||||
#endif |
||||
| 2 << SDRAM_CFG_SDRAM_TYPE_SHIFT; |
||||
#if defined (CONFIG_DDR_32BIT) |
||||
/* for 32-bit mode burst length is 8 */ |
||||
im->ddr.sdram_cfg |= (SDRAM_CFG_32_BE | SDRAM_CFG_8_BE); |
||||
#endif |
||||
im->ddr.sdram_mode = CFG_DDR_MODE; |
||||
|
||||
im->ddr.sdram_interval = CFG_DDR_INTERVAL;
|
||||
udelay(200); |
||||
|
||||
/* enable DDR controller */ |
||||
im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN; |
||||
return msize; |
||||
} |
||||
#endif/*!CFG_SPD_EEPROM*/ |
||||
|
||||
|
||||
int checkboard (void) |
||||
{ |
||||
puts("Board: Freescale MPC8349EMDS\n"); |
||||
return 0; |
||||
} |
||||
|
||||
#if defined(CONFIG_PCI) |
||||
/*
|
||||
* Initialize PCI Devices, report devices found |
||||
*/ |
||||
#ifndef CONFIG_PCI_PNP |
||||
static struct pci_config_table pci_mpc8349emds_config_table[] = { |
||||
{PCI_ANY_ID,PCI_ANY_ID,PCI_ANY_ID,PCI_ANY_ID, |
||||
pci_cfgfunc_config_device, {PCI_ENET0_IOADDR, |
||||
PCI_ENET0_MEMADDR, |
||||
PCI_COMMON_MEMORY | PCI_COMMAND_MASTER |
||||
} }, |
||||
{} |
||||
} |
||||
#endif |
||||
|
||||
volatile static struct pci_controller hose[] = { |
||||
{ |
||||
#ifndef CONFIG_PCI_PNP |
||||
config_table:pci_mpc8349emds_config_table, |
||||
#endif |
||||
}, |
||||
{ |
||||
#ifndef CONFIG_PCI_PNP |
||||
config_table:pci_mpc8349emds_config_table, |
||||
#endif |
||||
} |
||||
}; |
||||
#endif /* CONFIG_PCI */ |
||||
|
||||
void pci_init_board(void) |
||||
{ |
||||
#ifdef CONFIG_PCI |
||||
extern void pci_mpc83xx_init(volatile struct pci_controller *hose); |
||||
|
||||
pci_mpc83xx_init(hose); |
||||
#endif /* CONFIG_PCI */ |
||||
} |
||||
|
||||
/*
|
||||
* if MPC8349EMDS is soldered with SDRAM |
||||
*/ |
||||
#if defined(CFG_BR2_PRELIM) \ |
||||
&& defined(CFG_OR2_PRELIM) \
|
||||
&& defined(CFG_LBLAWBAR2_PRELIM) \
|
||||
&& defined(CFG_LBLAWAR2_PRELIM) |
||||
/*
|
||||
* Initialize SDRAM memory on the Local Bus. |
||||
*/ |
||||
|
||||
void sdram_init(void) |
||||
{ |
||||
volatile immap_t *immap = (immap_t *)CFG_IMMRBAR; |
||||
volatile lbus8349_t *lbc= &immap->lbus; |
||||
uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE; |
||||
|
||||
puts("\n SDRAM on Local Bus: "); |
||||
print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n"); |
||||
|
||||
/*
|
||||
* Setup SDRAM Base and Option Registers, already done in cpu_init.c |
||||
*/ |
||||
|
||||
/* setup mtrpt, lsrt and lbcr for LB bus */ |
||||
lbc->lbcr = CFG_LBC_LBCR; |
||||
lbc->mrtpr = CFG_LBC_MRTPR; |
||||
lbc->lsrt = CFG_LBC_LSRT; |
||||
asm("sync"); |
||||
|
||||
/*
|
||||
* Configure the SDRAM controller Machine Mode Register. |
||||
*/ |
||||
lbc->lsdmr = CFG_LBC_LSDMR_5; /* 0x40636733; normal operation */ |
||||
|
||||
lbc->lsdmr = CFG_LBC_LSDMR_1; /* 0x68636733; precharge all the banks */ |
||||
asm("sync"); |
||||
*sdram_addr = 0xff; |
||||
udelay(100); |
||||
|
||||
lbc->lsdmr = CFG_LBC_LSDMR_2; /* 0x48636733; auto refresh */ |
||||
asm("sync"); |
||||
/*1 times*/ |
||||
*sdram_addr = 0xff; |
||||
udelay(100); |
||||
/*2 times*/ |
||||
*sdram_addr = 0xff; |
||||
udelay(100); |
||||
/*3 times*/ |
||||
*sdram_addr = 0xff; |
||||
udelay(100); |
||||
/*4 times*/ |
||||
*sdram_addr = 0xff; |
||||
udelay(100); |
||||
/*5 times*/ |
||||
*sdram_addr = 0xff; |
||||
udelay(100); |
||||
/*6 times*/ |
||||
*sdram_addr = 0xff; |
||||
udelay(100); |
||||
/*7 times*/ |
||||
*sdram_addr = 0xff; |
||||
udelay(100); |
||||
/*8 times*/ |
||||
*sdram_addr = 0xff; |
||||
udelay(100); |
||||
|
||||
/* 0x58636733; mode register write operation */ |
||||
lbc->lsdmr = CFG_LBC_LSDMR_4; |
||||
asm("sync"); |
||||
*sdram_addr = 0xff; |
||||
udelay(100); |
||||
|
||||
lbc->lsdmr = CFG_LBC_LSDMR_5; /* 0x40636733; normal operation */ |
||||
asm("sync"); |
||||
*sdram_addr = 0xff; |
||||
udelay(100); |
||||
} |
||||
#else |
||||
void sdram_init(void) |
||||
{ |
||||
put("SDRAM on Local Bus is NOT available!\n"); |
||||
} |
||||
#endif |
||||
|
||||
#if defined(CONFIG_DDR_ECC) && defined(CONFIG_DDR_ECC_CMD) |
||||
/*
|
||||
* ECC user commands |
||||
*/ |
||||
void ecc_print_status(void) |
||||
{ |
||||
volatile immap_t *immap = (immap_t *)CFG_IMMRBAR; |
||||
volatile ddr8349_t *ddr = &immap->ddr; |
||||
|
||||
printf("\nECC mode: %s\n\n", (ddr->sdram_cfg & SDRAM_CFG_ECC_EN) ? "ON" : "OFF"); |
||||
|
||||
/* Interrupts */ |
||||
printf("Memory Error Interrupt Enable:\n"); |
||||
printf(" Multiple-Bit Error Interrupt Enable: %d\n", |
||||
(ddr->err_int_en & ECC_ERR_INT_EN_MBEE) ? 1 : 0); |
||||
printf(" Single-Bit Error Interrupt Enable: %d\n", |
||||
(ddr->err_int_en & ECC_ERR_INT_EN_SBEE) ? 1 : 0); |
||||
printf(" Memory Select Error Interrupt Enable: %d\n\n", |
||||
(ddr->err_int_en & ECC_ERR_INT_EN_MSEE) ? 1 : 0); |
||||
|
||||
/* Error disable */ |
||||
printf("Memory Error Disable:\n"); |
||||
printf(" Multiple-Bit Error Disable: %d\n", |
||||
(ddr->err_disable & ECC_ERROR_DISABLE_MBED) ? 1 : 0); |
||||
printf(" Sinle-Bit Error Disable: %d\n", |
||||
(ddr->err_disable & ECC_ERROR_DISABLE_SBED) ? 1 : 0); |
||||
printf(" Memory Select Error Disable: %d\n\n", |
||||
(ddr->err_disable & ECC_ERROR_DISABLE_MSED) ? 1 : 0); |
||||
|
||||
/* Error injection */ |
||||
printf("Memory Data Path Error Injection Mask High/Low: %08lx %08lx\n", |
||||
ddr->data_err_inject_hi, ddr->data_err_inject_lo); |
||||
|
||||
printf("Memory Data Path Error Injection Mask ECC:\n"); |
||||
printf(" ECC Mirror Byte: %d\n", |
||||
(ddr->ecc_err_inject & ECC_ERR_INJECT_EMB) ? 1 : 0); |
||||
printf(" ECC Injection Enable: %d\n", |
||||
(ddr->ecc_err_inject & ECC_ERR_INJECT_EIEN) ? 1 : 0); |
||||
printf(" ECC Error Injection Mask: 0x%02x\n\n", |
||||
ddr->ecc_err_inject & ECC_ERR_INJECT_EEIM); |
||||
|
||||
/* SBE counter/threshold */ |
||||
printf("Memory Single-Bit Error Management (0..255):\n"); |
||||
printf(" Single-Bit Error Threshold: %d\n", |
||||
(ddr->err_sbe & ECC_ERROR_MAN_SBET) >> ECC_ERROR_MAN_SBET_SHIFT); |
||||
printf(" Single-Bit Error Counter: %d\n\n", |
||||
(ddr->err_sbe & ECC_ERROR_MAN_SBEC) >> ECC_ERROR_MAN_SBEC_SHIFT); |
||||
|
||||
/* Error detect */ |
||||
printf("Memory Error Detect:\n"); |
||||
printf(" Multiple Memory Errors: %d\n", |
||||
(ddr->err_detect & ECC_ERROR_DETECT_MME) ? 1 : 0); |
||||
printf(" Multiple-Bit Error: %d\n", |
||||
(ddr->err_detect & ECC_ERROR_DETECT_MBE) ? 1 : 0); |
||||
printf(" Single-Bit Error: %d\n", |
||||
(ddr->err_detect & ECC_ERROR_DETECT_SBE) ? 1 : 0); |
||||
printf(" Memory Select Error: %d\n\n", |
||||
(ddr->err_detect & ECC_ERROR_DETECT_MSE) ? 1 : 0); |
||||
|
||||
/* Capture data */ |
||||
printf("Memory Error Address Capture: 0x%08lx\n", ddr->capture_address); |
||||
printf("Memory Data Path Read Capture High/Low: %08lx %08lx\n", |
||||
ddr->capture_data_hi, ddr->capture_data_lo); |
||||
printf("Memory Data Path Read Capture ECC: 0x%02x\n\n", |
||||
ddr->capture_ecc & CAPTURE_ECC_ECE); |
||||
|
||||
printf("Memory Error Attributes Capture:\n"); |
||||
printf(" Data Beat Number: %d\n", |
||||
(ddr->capture_attributes & ECC_CAPT_ATTR_BNUM) >> ECC_CAPT_ATTR_BNUM_SHIFT); |
||||
printf(" Transaction Size: %d\n", |
||||
(ddr->capture_attributes & ECC_CAPT_ATTR_TSIZ) >> ECC_CAPT_ATTR_TSIZ_SHIFT); |
||||
printf(" Transaction Source: %d\n", |
||||
(ddr->capture_attributes & ECC_CAPT_ATTR_TSRC) >> ECC_CAPT_ATTR_TSRC_SHIFT); |
||||
printf(" Transaction Type: %d\n", |
||||
(ddr->capture_attributes & ECC_CAPT_ATTR_TTYP) >> ECC_CAPT_ATTR_TTYP_SHIFT); |
||||
printf(" Error Information Valid: %d\n\n", |
||||
ddr->capture_attributes & ECC_CAPT_ATTR_VLD); |
||||
} |
||||
|
||||
int do_ecc ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) |
||||
{ |
||||
volatile immap_t *immap = (immap_t *)CFG_IMMRBAR; |
||||
volatile ddr8349_t *ddr = &immap->ddr; |
||||
volatile u32 val; |
||||
u64 *addr, count, val64; |
||||
register u64 *i; |
||||
|
||||
if (argc > 4) { |
||||
printf ("Usage:\n%s\n", cmdtp->usage); |
||||
return 1; |
||||
} |
||||
|
||||
if (argc == 2) { |
||||
if (strcmp(argv[1], "status") == 0) { |
||||
ecc_print_status(); |
||||
return 0; |
||||
} else if (strcmp(argv[1], "captureclear") == 0) { |
||||
ddr->capture_address = 0; |
||||
ddr->capture_data_hi = 0; |
||||
ddr->capture_data_lo = 0; |
||||
ddr->capture_ecc = 0; |
||||
ddr->capture_attributes = 0; |
||||
return 0; |
||||
} |
||||
}
|
||||
|
||||
if (argc == 3) { |
||||
if (strcmp(argv[1], "sbecnt") == 0) { |
||||
val = simple_strtoul(argv[2], NULL, 10); |
||||
if (val > 255) { |
||||
printf("Incorrect Counter value, should be 0..255\n"); |
||||
return 1; |
||||
} |
||||
|
||||
val = (val << ECC_ERROR_MAN_SBEC_SHIFT); |
||||
val |= (ddr->err_sbe & ECC_ERROR_MAN_SBET); |
||||
|
||||
ddr->err_sbe = val; |
||||
return 0; |
||||
} else if (strcmp(argv[1], "sbethr") == 0) { |
||||
val = simple_strtoul(argv[2], NULL, 10); |
||||
if (val > 255) { |
||||
printf("Incorrect Counter value, should be 0..255\n"); |
||||
return 1; |
||||
} |
||||
|
||||
val = (val << ECC_ERROR_MAN_SBET_SHIFT); |
||||
val |= (ddr->err_sbe & ECC_ERROR_MAN_SBEC); |
||||
|
||||
ddr->err_sbe = val; |
||||
return 0; |
||||
} else if (strcmp(argv[1], "errdisable") == 0) { |
||||
val = ddr->err_disable; |
||||
|
||||
if (strcmp(argv[2], "+sbe") == 0) { |
||||
val |= ECC_ERROR_DISABLE_SBED; |
||||
} else if (strcmp(argv[2], "+mbe") == 0) { |
||||
val |= ECC_ERROR_DISABLE_MBED; |
||||
} else if (strcmp(argv[2], "+mse") == 0) { |
||||
val |= ECC_ERROR_DISABLE_MSED; |
||||
} else if (strcmp(argv[2], "+all") == 0) { |
||||
val |= (ECC_ERROR_DISABLE_SBED |
|
||||
ECC_ERROR_DISABLE_MBED |
|
||||
ECC_ERROR_DISABLE_MSED); |
||||
} else if (strcmp(argv[2], "-sbe") == 0) { |
||||
val &= ~ECC_ERROR_DISABLE_SBED; |
||||
} else if (strcmp(argv[2], "-mbe") == 0) { |
||||
val &= ~ECC_ERROR_DISABLE_MBED; |
||||
} else if (strcmp(argv[2], "-mse") == 0) { |
||||
val &= ~ECC_ERROR_DISABLE_MSED; |
||||
} else if (strcmp(argv[2], "-all") == 0) { |
||||
val &= ~(ECC_ERROR_DISABLE_SBED |
|
||||
ECC_ERROR_DISABLE_MBED |
|
||||
ECC_ERROR_DISABLE_MSED); |
||||
} else { |
||||
printf("Incorrect err_disable field\n"); |
||||
return 1; |
||||
} |
||||
|
||||
ddr->err_disable = val; |
||||
__asm__ __volatile__ ("sync"); |
||||
__asm__ __volatile__ ("isync"); |
||||
return 0; |
||||
} else if (strcmp(argv[1], "errdetectclr") == 0) { |
||||
val = ddr->err_detect; |
||||
|
||||
if (strcmp(argv[2], "mme") == 0) { |
||||
val |= ECC_ERROR_DETECT_MME; |
||||
} else if (strcmp(argv[2], "sbe") == 0) { |
||||
val |= ECC_ERROR_DETECT_SBE; |
||||
} else if (strcmp(argv[2], "mbe") == 0) { |
||||
val |= ECC_ERROR_DETECT_MBE; |
||||
} else if (strcmp(argv[2], "mse") == 0) { |
||||
val |= ECC_ERROR_DETECT_MSE; |
||||
} else if (strcmp(argv[2], "all") == 0) { |
||||
val |= (ECC_ERROR_DETECT_MME | |
||||
ECC_ERROR_DETECT_MBE | |
||||
ECC_ERROR_DETECT_SBE | |
||||
ECC_ERROR_DETECT_MSE); |
||||
} else { |
||||
printf("Incorrect err_detect field\n"); |
||||
return 1; |
||||
} |
||||
|
||||
ddr->err_detect = val; |
||||
return 0; |
||||
} else if (strcmp(argv[1], "injectdatahi") == 0) { |
||||
val = simple_strtoul(argv[2], NULL, 16); |
||||
|
||||
ddr->data_err_inject_hi = val; |
||||
return 0; |
||||
} else if (strcmp(argv[1], "injectdatalo") == 0) { |
||||
val = simple_strtoul(argv[2], NULL, 16); |
||||
|
||||
ddr->data_err_inject_lo = val; |
||||
return 0; |
||||
} else if (strcmp(argv[1], "injectecc") == 0) { |
||||
val = simple_strtoul(argv[2], NULL, 16); |
||||
if (val > 0xff) { |
||||
printf("Incorrect ECC inject mask, should be 0x00..0xff\n"); |
||||
return 1; |
||||
} |
||||
val |= (ddr->ecc_err_inject & ~ECC_ERR_INJECT_EEIM); |
||||
|
||||
ddr->ecc_err_inject = val; |
||||
return 0; |
||||
} else if (strcmp(argv[1], "inject") == 0) { |
||||
val = ddr->ecc_err_inject; |
||||
|
||||
if (strcmp(argv[2], "en") == 0) |
||||
val |= ECC_ERR_INJECT_EIEN; |
||||
else if (strcmp(argv[2], "dis") == 0) |
||||
val &= ~ECC_ERR_INJECT_EIEN; |
||||
else |
||||
printf("Incorrect command\n"); |
||||
|
||||
ddr->ecc_err_inject = val; |
||||
__asm__ __volatile__ ("sync"); |
||||
__asm__ __volatile__ ("isync"); |
||||
return 0; |
||||
} else if (strcmp(argv[1], "mirror") == 0) { |
||||
val = ddr->ecc_err_inject; |
||||
|
||||
if (strcmp(argv[2], "en") == 0) |
||||
val |= ECC_ERR_INJECT_EMB; |
||||
else if (strcmp(argv[2], "dis") == 0) |
||||
val &= ~ECC_ERR_INJECT_EMB; |
||||
else |
||||
printf("Incorrect command\n"); |
||||
|
||||
ddr->ecc_err_inject = val; |
||||
return 0; |
||||
} |
||||
} |
||||
|
||||
if (argc == 4) { |
||||
if (strcmp(argv[1], "test") == 0) { |
||||
addr = (u64 *)simple_strtoul(argv[2], NULL, 16); |
||||
count = simple_strtoul(argv[3], NULL, 16); |
||||
|
||||
if ((u32)addr % 8) { |
||||
printf("Address not alligned on double word boundary\n"); |
||||
return 1; |
||||
} |
||||
|
||||
disable_interrupts(); |
||||
icache_disable(); |
||||
|
||||
for (i = addr; i < addr + count; i++) { |
||||
/* enable injects */ |
||||
ddr->ecc_err_inject |= ECC_ERR_INJECT_EIEN; |
||||
__asm__ __volatile__ ("sync"); |
||||
__asm__ __volatile__ ("isync"); |
||||
|
||||
/* write memory location injecting errors */ |
||||
*i = 0x1122334455667788ULL; |
||||
__asm__ __volatile__ ("sync"); |
||||
|
||||
/* disable injects */ |
||||
ddr->ecc_err_inject &= ~ECC_ERR_INJECT_EIEN; |
||||
__asm__ __volatile__ ("sync"); |
||||
__asm__ __volatile__ ("isync"); |
||||
|
||||
/* read data, this generates ECC error */ |
||||
val64 = *i; |
||||
__asm__ __volatile__ ("sync"); |
||||
|
||||
/* disable errors for ECC */ |
||||
ddr->err_disable |= ~ECC_ERROR_ENABLE; |
||||
__asm__ __volatile__ ("sync"); |
||||
__asm__ __volatile__ ("isync"); |
||||
|
||||
/* re-initialize memory, write the location again
|
||||
* NOT injecting errors this time */ |
||||
*i = 0xcafecafecafecafeULL; |
||||
__asm__ __volatile__ ("sync"); |
||||
|
||||
/* enable errors for ECC */ |
||||
ddr->err_disable &= ECC_ERROR_ENABLE; |
||||
__asm__ __volatile__ ("sync"); |
||||
__asm__ __volatile__ ("isync"); |
||||
} |
||||
|
||||
icache_enable(); |
||||
enable_interrupts(); |
||||
|
||||
return 0; |
||||
} |
||||
} |
||||
|
||||
printf ("Usage:\n%s\n", cmdtp->usage); |
||||
return 1; |
||||
} |
||||
|
||||
U_BOOT_CMD( |
||||
ecc, 4, 0, do_ecc, |
||||
"ecc - support for DDR ECC features\n", |
||||
"status - print out status info\n" |
||||
"ecc captureclear - clear capture regs data\n" |
||||
"ecc sbecnt <val> - set Single-Bit Error counter\n" |
||||
"ecc sbethr <val> - set Single-Bit Threshold\n" |
||||
"ecc errdisable <flag> - clear/set disable Memory Error Disable, flag:\n" |
||||
" [-|+]sbe - Single-Bit Error\n" |
||||
" [-|+]mbe - Multiple-Bit Error\n" |
||||
" [-|+]mse - Memory Select Error\n" |
||||
" [-|+]all - all errors\n" |
||||
"ecc errdetectclr <flag> - clear Memory Error Detect, flag:\n" |
||||
" mme - Multiple Memory Errors\n" |
||||
" sbe - Single-Bit Error\n" |
||||
" mbe - Multiple-Bit Error\n" |
||||
" mse - Memory Select Error\n" |
||||
" all - all errors\n" |
||||
"ecc injectdatahi <hi> - set Memory Data Path Error Injection Mask High\n" |
||||
"ecc injectdatalo <lo> - set Memory Data Path Error Injection Mask Low\n" |
||||
"ecc injectecc <ecc> - set ECC Error Injection Mask\n" |
||||
"ecc inject <en|dis> - enable/disable error injection\n" |
||||
"ecc mirror <en|dis> - enable/disable mirror byte\n" |
||||
"ecc test <addr> <cnt> - test mem region:\n" |
||||
" - enables injects\n" |
||||
" - writes pattern injecting errors\n" |
||||
" - disables injects\n" |
||||
" - reads pattern back, generates error\n" |
||||
" - re-inits memory" |
||||
); |
||||
#endif /* if defined(CONFIG_DDR_ECC) && defined(CONFIG_DDR_ECC_CMD) */ |
||||
@ -0,0 +1,123 @@ |
||||
/* |
||||
* (C) Copyright 2006 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
OUTPUT_ARCH(powerpc) |
||||
SECTIONS |
||||
{ |
||||
/* Read-only sections, merged into text segment: */ |
||||
. = + SIZEOF_HEADERS; |
||||
.interp : { *(.interp) } |
||||
.hash : { *(.hash) } |
||||
.dynsym : { *(.dynsym) } |
||||
.dynstr : { *(.dynstr) } |
||||
.rel.text : { *(.rel.text) } |
||||
.rela.text : { *(.rela.text) } |
||||
.rel.data : { *(.rel.data) } |
||||
.rela.data : { *(.rela.data) } |
||||
.rel.rodata : { *(.rel.rodata) } |
||||
.rela.rodata : { *(.rela.rodata) } |
||||
.rel.got : { *(.rel.got) } |
||||
.rela.got : { *(.rela.got) } |
||||
.rel.ctors : { *(.rel.ctors) } |
||||
.rela.ctors : { *(.rela.ctors) } |
||||
.rel.dtors : { *(.rel.dtors) } |
||||
.rela.dtors : { *(.rela.dtors) } |
||||
.rel.bss : { *(.rel.bss) } |
||||
.rela.bss : { *(.rela.bss) } |
||||
.rel.plt : { *(.rel.plt) } |
||||
.rela.plt : { *(.rela.plt) } |
||||
.init : { *(.init) } |
||||
.plt : { *(.plt) } |
||||
.text : |
||||
{ |
||||
cpu/mpc83xx/start.o (.text) |
||||
*(.text) |
||||
*(.fixup) |
||||
*(.got1) |
||||
. = ALIGN(16); |
||||
*(.rodata) |
||||
*(.rodata1) |
||||
*(.rodata.str1.4) |
||||
*(.eh_frame) |
||||
} |
||||
.fini : { *(.fini) } =0 |
||||
.ctors : { *(.ctors) } |
||||
.dtors : { *(.dtors) } |
||||
|
||||
/* Read-write section, merged into data segment: */ |
||||
. = (. + 0x0FFF) & 0xFFFFF000; |
||||
_erotext = .; |
||||
PROVIDE (erotext = .); |
||||
.reloc : |
||||
{ |
||||
*(.got) |
||||
_GOT2_TABLE_ = .; |
||||
*(.got2) |
||||
_FIXUP_TABLE_ = .; |
||||
*(.fixup) |
||||
} |
||||
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; |
||||
__fixup_entries = (. - _FIXUP_TABLE_) >> 2; |
||||
|
||||
.data : |
||||
{ |
||||
*(.data) |
||||
*(.data1) |
||||
*(.sdata) |
||||
*(.sdata2) |
||||
*(.dynamic) |
||||
CONSTRUCTORS |
||||
} |
||||
_edata = .; |
||||
PROVIDE (edata = .); |
||||
|
||||
. = .; |
||||
__u_boot_cmd_start = .; |
||||
.u_boot_cmd : { *(.u_boot_cmd) } |
||||
__u_boot_cmd_end = .; |
||||
|
||||
|
||||
. = .; |
||||
__start___ex_table = .; |
||||
__ex_table : { *(__ex_table) } |
||||
__stop___ex_table = .; |
||||
|
||||
. = ALIGN(4096); |
||||
__init_begin = .; |
||||
.text.init : { *(.text.init) } |
||||
.data.init : { *(.data.init) } |
||||
. = ALIGN(4096); |
||||
__init_end = .; |
||||
|
||||
__bss_start = .; |
||||
.bss : |
||||
{ |
||||
*(.sbss) *(.scommon) |
||||
*(.dynbss) |
||||
*(.bss) |
||||
*(COMMON) |
||||
} |
||||
_end = . ; |
||||
PROVIDE (end = .); |
||||
} |
||||
ENTRY(_start) |
||||
@ -0,0 +1,85 @@ |
||||
#
|
||||
# (C) Copyright 2005
|
||||
# Ladislav Michl, 2N Telekomunikace, michl@2n.cz
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
include $(TOPDIR)/config.mk |
||||
|
||||
LIB = lib$(BOARD).a
|
||||
|
||||
OBJS := netstar.o flash.o nand.o
|
||||
SOBJS := setup.o crcek.o
|
||||
|
||||
gcclibdir := $(shell dirname `$(CC) -print-libgcc-file-name`)
|
||||
|
||||
LOAD_ADDR = 0x10400000
|
||||
LDSCRIPT = $(TOPDIR)/board/$(BOARDDIR)/eeprom.lds
|
||||
|
||||
HOST_CFLAGS = -Wall -pedantic -I$(TOPDIR)/include
|
||||
|
||||
all: $(LIB) eeprom.srec eeprom.bin crcek.srec crcek.bin crcit |
||||
|
||||
$(LIB): $(OBJS) $(SOBJS) |
||||
$(AR) crv $@ $^
|
||||
|
||||
eeprom.srec: eeprom.o eeprom_start.o |
||||
$(LD) -T $(LDSCRIPT) -g -Ttext $(LOAD_ADDR) \
|
||||
-o $(<:.o=) -e $(<:.o=) $^ \
|
||||
-L../../examples -lstubs \
|
||||
-L../../lib_generic -lgeneric \
|
||||
-L$(gcclibdir) -lgcc
|
||||
$(OBJCOPY) -O srec $(<:.o=) $@
|
||||
|
||||
eeprom.bin: eeprom.srec |
||||
$(OBJCOPY) -I srec -O binary $< $@ 2>/dev/null
|
||||
|
||||
crcek.srec: crcek.o |
||||
$(LD) -g -Ttext 0x00000000 \
|
||||
-o $(<:.o=) -e $(<:.o=) $^
|
||||
$(OBJCOPY) -O srec $(<:.o=) $@
|
||||
|
||||
crcek.bin: crcek.srec |
||||
$(OBJCOPY) -I srec -O binary $< $@ 2>/dev/null
|
||||
|
||||
crcit: crcit.o crc32.o |
||||
$(HOSTCC) $(HOST_CFLAGS) -o $@ $^
|
||||
|
||||
crcit.o: crcit.c |
||||
$(HOSTCC) $(HOST_CFLAGS) -c $<
|
||||
|
||||
crc32.o: $(TOPDIR)/tools/crc32.c |
||||
$(HOSTCC) $(HOST_CFLAGS) -DUSE_HOSTCC -c $<
|
||||
|
||||
clean: |
||||
rm -f $(SOBJS) $(OBJS) eeprom eeprom.srec eeprom.bin \
|
||||
crcek crcek.srec crcek.bin
|
||||
|
||||
distclean: clean |
||||
rm -f $(LIB) core *.bak .depend
|
||||
|
||||
#########################################################################
|
||||
|
||||
.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) |
||||
$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
|
||||
|
||||
sinclude .depend |
||||
|
||||
#########################################################################
|
||||
@ -0,0 +1,14 @@ |
||||
#
|
||||
# Linux-Kernel is expected to be at 1000'8000,
|
||||
# entry 1000'8000 (mem base + reserved)
|
||||
#
|
||||
# We load ourself to internal RAM at 2001'2000
|
||||
# Check map file when changing TEXT_BASE.
|
||||
# Everything has fit into 192kB internal SRAM!
|
||||
#
|
||||
|
||||
# XXX TEXT_BASE = 0x20012000
|
||||
TEXT_BASE = 0x13FC0000
|
||||
|
||||
# Compile the new NAND code
|
||||
BOARDLIBS = drivers/nand/libnand.a
|
||||
@ -0,0 +1,177 @@ |
||||
/** |
||||
* (C) Copyright 2005 |
||||
* 2N Telekomunikace, Ladislav Michl <michl@2n.cz>
|
||||
* |
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License |
||||
* version 2. |
||||
* |
||||
* Image layout looks like following: |
||||
* u32 - size |
||||
* u32 - version |
||||
* ... - data |
||||
* u32 - crc32 |
||||
*/ |
||||
|
||||
#include "crcek.h" |
||||
|
||||
/** |
||||
* do_crc32 - calculate CRC32 of given buffer |
||||
* r0 - crc |
||||
* r1 - pointer to buffer |
||||
* r2 - buffer len |
||||
*/ |
||||
.macro do_crc32
|
||||
ldr r5, FFFFFFFF |
||||
eor r0, r0, r5 |
||||
adr r3, CRC32_TABLE |
||||
1: |
||||
ldrb r4, [r1], #1 |
||||
eor r4, r4, r0 |
||||
and r4, r4, #0xff |
||||
ldr r4, [r3, r4, lsl#2] |
||||
eor r0, r4, r0, lsr#8 |
||||
subs r2, r2, #0x1 |
||||
bne 1b |
||||
eor r0, r0, r5 |
||||
.endm |
||||
|
||||
.macro crcuj, offset, size |
||||
mov r0, #0 |
||||
ldr r1, \offset |
||||
ldr r2, [r1] |
||||
cmp r2, r0 @ no data, no problem
|
||||
beq 2f |
||||
tst r2, #3 @ unaligned size
|
||||
bne 2f |
||||
ldr r3, \size |
||||
cmp r2, r3 @ bogus size
|
||||
bhi 2f |
||||
add r1, r1, #4 |
||||
do_crc32 |
||||
ldr r1, [r1] |
||||
2: |
||||
cmp r0, r1 |
||||
.endm |
||||
|
||||
.macro wait, reg |
||||
mov \reg, #0x1000 |
||||
3: |
||||
subs \reg, \reg, #0x1 |
||||
bne 3b |
||||
|
||||
.endm |
||||
.text |
||||
.globl crcek
|
||||
crcek: |
||||
b crc2_bad |
||||
mov r6, #0 |
||||
crcuj _LOADER1_OFFSET, _LOADER_SIZE |
||||
bne crc1_bad |
||||
orr r6, r6, #1 |
||||
crc1_bad: |
||||
crcuj _LOADER2_OFFSET, _LOADER_SIZE |
||||
bne crc2_bad |
||||
orr r6, r6, #2 |
||||
crc2_bad: |
||||
ldr r3, _LOADER1_OFFSET |
||||
ldr r4, _LOADER2_OFFSET |
||||
b boot_2nd |
||||
tst r6, #3 |
||||
beq one_is_bad @ one of them (or both) has bad crc
|
||||
ldr r1, [r3, #4] |
||||
ldr r2, [r4, #4] |
||||
cmp r1, r2 @ boot 2nd loader if versions differ
|
||||
beq boot_1st |
||||
b boot_2nd |
||||
one_is_bad: |
||||
tst r6, #1 |
||||
bne boot_1st |
||||
tst r6, #2 |
||||
bne boot_2nd |
||||
@ We are doomed, so let user know.
|
||||
ldr r0, GPIO_BASE @ configure GPIO pins
|
||||
ldr r1, GPIO_DIRECTION |
||||
strh r1, [r0, #0x08] |
||||
blink_loop: |
||||
mov r1, #0x08 |
||||
strh r1, [r0, #0x04] |
||||
wait r3 |
||||
mov r1, #0x10 |
||||
strh r1, [r0, #0x04] |
||||
wait r3 |
||||
b blink_loop |
||||
boot_1st: |
||||
add pc, r3, #8 |
||||
boot_2nd: |
||||
add pc, r4, #8 |
||||
|
||||
_LOADER_SIZE: |
||||
.word LOADER_SIZE - 8 @ minus size and crc32
|
||||
_LOADER1_OFFSET: |
||||
.word LOADER1_OFFSET
|
||||
_LOADER2_OFFSET: |
||||
.word LOADER2_OFFSET
|
||||
|
||||
FFFFFFFF: |
||||
.word 0xffffffff
|
||||
CRC32_TABLE: |
||||
.word 0x00000000, 0x77073096, 0xee0e612c, 0x990951ba, 0x076dc419 |
||||
.word 0x706af48f, 0xe963a535, 0x9e6495a3, 0x0edb8832, 0x79dcb8a4 |
||||
.word 0xe0d5e91e, 0x97d2d988, 0x09b64c2b, 0x7eb17cbd, 0xe7b82d07 |
||||
.word 0x90bf1d91, 0x1db71064, 0x6ab020f2, 0xf3b97148, 0x84be41de |
||||
.word 0x1adad47d, 0x6ddde4eb, 0xf4d4b551, 0x83d385c7, 0x136c9856 |
||||
.word 0x646ba8c0, 0xfd62f97a, 0x8a65c9ec, 0x14015c4f, 0x63066cd9 |
||||
.word 0xfa0f3d63, 0x8d080df5, 0x3b6e20c8, 0x4c69105e, 0xd56041e4 |
||||
.word 0xa2677172, 0x3c03e4d1, 0x4b04d447, 0xd20d85fd, 0xa50ab56b |
||||
.word 0x35b5a8fa, 0x42b2986c, 0xdbbbc9d6, 0xacbcf940, 0x32d86ce3 |
||||
.word 0x45df5c75, 0xdcd60dcf, 0xabd13d59, 0x26d930ac, 0x51de003a |
||||
.word 0xc8d75180, 0xbfd06116, 0x21b4f4b5, 0x56b3c423, 0xcfba9599 |
||||
.word 0xb8bda50f, 0x2802b89e, 0x5f058808, 0xc60cd9b2, 0xb10be924 |
||||
.word 0x2f6f7c87, 0x58684c11, 0xc1611dab, 0xb6662d3d, 0x76dc4190 |
||||
.word 0x01db7106, 0x98d220bc, 0xefd5102a, 0x71b18589, 0x06b6b51f |
||||
.word 0x9fbfe4a5, 0xe8b8d433, 0x7807c9a2, 0x0f00f934, 0x9609a88e |
||||
.word 0xe10e9818, 0x7f6a0dbb, 0x086d3d2d, 0x91646c97, 0xe6635c01 |
||||
.word 0x6b6b51f4, 0x1c6c6162, 0x856530d8, 0xf262004e, 0x6c0695ed |
||||
.word 0x1b01a57b, 0x8208f4c1, 0xf50fc457, 0x65b0d9c6, 0x12b7e950 |
||||
.word 0x8bbeb8ea, 0xfcb9887c, 0x62dd1ddf, 0x15da2d49, 0x8cd37cf3 |
||||
.word 0xfbd44c65, 0x4db26158, 0x3ab551ce, 0xa3bc0074, 0xd4bb30e2 |
||||
.word 0x4adfa541, 0x3dd895d7, 0xa4d1c46d, 0xd3d6f4fb, 0x4369e96a |
||||
.word 0x346ed9fc, 0xad678846, 0xda60b8d0, 0x44042d73, 0x33031de5 |
||||
.word 0xaa0a4c5f, 0xdd0d7cc9, 0x5005713c, 0x270241aa, 0xbe0b1010 |
||||
.word 0xc90c2086, 0x5768b525, 0x206f85b3, 0xb966d409, 0xce61e49f |
||||
.word 0x5edef90e, 0x29d9c998, 0xb0d09822, 0xc7d7a8b4, 0x59b33d17 |
||||
.word 0x2eb40d81, 0xb7bd5c3b, 0xc0ba6cad, 0xedb88320, 0x9abfb3b6 |
||||
.word 0x03b6e20c, 0x74b1d29a, 0xead54739, 0x9dd277af, 0x04db2615 |
||||
.word 0x73dc1683, 0xe3630b12, 0x94643b84, 0x0d6d6a3e, 0x7a6a5aa8 |
||||
.word 0xe40ecf0b, 0x9309ff9d, 0x0a00ae27, 0x7d079eb1, 0xf00f9344 |
||||
.word 0x8708a3d2, 0x1e01f268, 0x6906c2fe, 0xf762575d, 0x806567cb |
||||
.word 0x196c3671, 0x6e6b06e7, 0xfed41b76, 0x89d32be0, 0x10da7a5a |
||||
.word 0x67dd4acc, 0xf9b9df6f, 0x8ebeeff9, 0x17b7be43, 0x60b08ed5 |
||||
.word 0xd6d6a3e8, 0xa1d1937e, 0x38d8c2c4, 0x4fdff252, 0xd1bb67f1 |
||||
.word 0xa6bc5767, 0x3fb506dd, 0x48b2364b, 0xd80d2bda, 0xaf0a1b4c |
||||
.word 0x36034af6, 0x41047a60, 0xdf60efc3, 0xa867df55, 0x316e8eef |
||||
.word 0x4669be79, 0xcb61b38c, 0xbc66831a, 0x256fd2a0, 0x5268e236 |
||||
.word 0xcc0c7795, 0xbb0b4703, 0x220216b9, 0x5505262f, 0xc5ba3bbe |
||||
.word 0xb2bd0b28, 0x2bb45a92, 0x5cb36a04, 0xc2d7ffa7, 0xb5d0cf31 |
||||
.word 0x2cd99e8b, 0x5bdeae1d, 0x9b64c2b0, 0xec63f226, 0x756aa39c |
||||
.word 0x026d930a, 0x9c0906a9, 0xeb0e363f, 0x72076785, 0x05005713 |
||||
.word 0x95bf4a82, 0xe2b87a14, 0x7bb12bae, 0x0cb61b38, 0x92d28e9b |
||||
.word 0xe5d5be0d, 0x7cdcefb7, 0x0bdbdf21, 0x86d3d2d4, 0xf1d4e242 |
||||
.word 0x68ddb3f8, 0x1fda836e, 0x81be16cd, 0xf6b9265b, 0x6fb077e1 |
||||
.word 0x18b74777, 0x88085ae6, 0xff0f6a70, 0x66063bca, 0x11010b5c |
||||
.word 0x8f659eff, 0xf862ae69, 0x616bffd3, 0x166ccf45, 0xa00ae278 |
||||
.word 0xd70dd2ee, 0x4e048354, 0x3903b3c2, 0xa7672661, 0xd06016f7 |
||||
.word 0x4969474d, 0x3e6e77db, 0xaed16a4a, 0xd9d65adc, 0x40df0b66 |
||||
.word 0x37d83bf0, 0xa9bcae53, 0xdebb9ec5, 0x47b2cf7f, 0x30b5ffe9 |
||||
.word 0xbdbdf21c, 0xcabac28a, 0x53b39330, 0x24b4a3a6, 0xbad03605 |
||||
.word 0xcdd70693, 0x54de5729, 0x23d967bf, 0xb3667a2e, 0xc4614ab8 |
||||
.word 0x5d681b02, 0x2a6f2b94, 0xb40bbe37, 0xc30c8ea1, 0x5a05df1b |
||||
.word 0x2d02ef8d
|
||||
|
||||
GPIO_BASE: |
||||
.word 0xfffce000
|
||||
GPIO_DIRECTION: |
||||
.word 0x0000ffe7
|
||||
|
||||
.end |
||||
@ -0,0 +1,3 @@ |
||||
#define LOADER_SIZE (448 * 1024) |
||||
#define LOADER1_OFFSET (128 * 1024) |
||||
#define LOADER2_OFFSET (LOADER1_OFFSET + LOADER_SIZE) |
||||
Binary file not shown.
@ -0,0 +1,86 @@ |
||||
/*
|
||||
* (C) Copyright 2005 |
||||
* 2N Telekomunikace, Ladislav Michl <michl@2n.cz> |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <stdio.h> |
||||
#include <stdlib.h> |
||||
#include <stdint.h> |
||||
#include <fcntl.h> |
||||
#include <string.h> |
||||
#include <unistd.h> |
||||
#include <sys/types.h> |
||||
#include <sys/stat.h> |
||||
#include "crcek.h" |
||||
|
||||
extern unsigned long crc32(unsigned long, const unsigned char *, unsigned int); |
||||
|
||||
uint32_t data[LOADER_SIZE/4 + 3]; |
||||
|
||||
int doit(char *path, unsigned version) |
||||
{ |
||||
uint32_t *p; |
||||
ssize_t size; |
||||
int fd; |
||||
|
||||
fd = open(path, O_RDONLY); |
||||
if (fd == -1) { |
||||
perror("Error opening file"); |
||||
return EXIT_FAILURE; |
||||
} |
||||
p = data + 2; |
||||
size = read(fd, p, LOADER_SIZE + 4); |
||||
if (size == -1) { |
||||
perror("Error reading file"); |
||||
return EXIT_FAILURE; |
||||
} |
||||
if (size > LOADER_SIZE) { |
||||
fprintf(stderr, "File too large\n"); |
||||
return EXIT_FAILURE; |
||||
} |
||||
size = (((size - 1) >> 2) + 1) << 2; |
||||
data[0] = size + 4; /* add size of version field */ |
||||
data[1] = version; |
||||
data[(size >> 2) + 2] = crc32(0, (unsigned char *)(data + 1), data[0]); |
||||
close(fd); |
||||
|
||||
if (write(STDOUT_FILENO, data, size + 3*4) == -1) { |
||||
perror("Error writing file"); |
||||
return EXIT_FAILURE; |
||||
} |
||||
|
||||
return EXIT_SUCCESS; |
||||
} |
||||
|
||||
int main(int argc, char **argv) |
||||
{ |
||||
if (argc == 2) { |
||||
return doit(argv[1], 0); |
||||
} else if ((argc == 4) && (strcmp(argv[1], "-v") == 0)) { |
||||
char *endptr, *nptr = argv[2]; |
||||
unsigned ver = strtoul(nptr, &endptr, 0); |
||||
if (nptr != '\0' && endptr == '\0') |
||||
return doit(argv[3], ver); |
||||
} |
||||
fprintf(stderr, "Usage: crcit [-v version] <image>\n"); |
||||
|
||||
return EXIT_FAILURE; |
||||
} |
||||
@ -0,0 +1,215 @@ |
||||
/*
|
||||
* (C) Copyright 2005 |
||||
* Ladislav Michl, 2N Telekomunikace, michl@2n.cz |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or modify |
||||
* it under the terms of the GNU General Public License version 2 as |
||||
* published by the Free Software Foundation. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
* |
||||
* Some code shamelessly stolen back from Robin Getz. |
||||
*/ |
||||
|
||||
#define DEBUG |
||||
|
||||
#include <common.h> |
||||
#include <exports.h> |
||||
#include "../drivers/smc91111.h" |
||||
|
||||
#define SMC_BASE_ADDRESS CONFIG_SMC91111_BASE |
||||
|
||||
static u16 read_eeprom_reg(u16 reg) |
||||
{ |
||||
int timeout; |
||||
|
||||
SMC_SELECT_BANK(2); |
||||
SMC_outw(reg, PTR_REG); |
||||
|
||||
SMC_SELECT_BANK(1); |
||||
SMC_outw(SMC_inw (CTL_REG) | CTL_EEPROM_SELECT | CTL_RELOAD, |
||||
CTL_REG); |
||||
timeout = 100; |
||||
while((SMC_inw (CTL_REG) & CTL_RELOAD) && --timeout) |
||||
udelay(100); |
||||
if (timeout == 0) { |
||||
printf("Timeout Reading EEPROM register %02x\n", reg); |
||||
return 0; |
||||
} |
||||
|
||||
return SMC_inw (GP_REG); |
||||
} |
||||
|
||||
static int write_eeprom_reg(u16 value, u16 reg) |
||||
{ |
||||
int timeout; |
||||
|
||||
SMC_SELECT_BANK(2); |
||||
SMC_outw(reg, PTR_REG); |
||||
|
||||
SMC_SELECT_BANK(1); |
||||
SMC_outw(value, GP_REG); |
||||
SMC_outw(SMC_inw (CTL_REG) | CTL_EEPROM_SELECT | CTL_STORE, CTL_REG); |
||||
timeout = 100; |
||||
while ((SMC_inw(CTL_REG) & CTL_STORE) && --timeout) |
||||
udelay (100); |
||||
if (timeout == 0) { |
||||
printf("Timeout Writing EEPROM register %02x\n", reg); |
||||
return 0; |
||||
} |
||||
|
||||
return 1; |
||||
} |
||||
|
||||
static int write_data(u16 *buf, int len) |
||||
{ |
||||
u16 reg = 0x23; |
||||
|
||||
while (len--) |
||||
write_eeprom_reg(*buf++, reg++); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static int verify_macaddr(char *s) |
||||
{ |
||||
u16 reg; |
||||
int i, err = 0; |
||||
|
||||
printf("MAC Address: "); |
||||
err = i = 0; |
||||
for (i = 0; i < 3; i++) { |
||||
reg = read_eeprom_reg(0x20 + i); |
||||
printf("%02x:%02x%c", reg & 0xff, reg >> 8, i != 2 ? ':' : '\n'); |
||||
if (s) |
||||
err |= reg != ((u16 *)s)[i]; |
||||
} |
||||
|
||||
return err ? 0 : 1; |
||||
} |
||||
|
||||
static int set_mac(char *s) |
||||
{ |
||||
int i; |
||||
char *e, eaddr[6]; |
||||
|
||||
/* turn string into mac value */ |
||||
for (i = 0; i < 6; i++) { |
||||
eaddr[i] = simple_strtoul(s, &e, 16); |
||||
s = (*e) ? e+1 : e; |
||||
} |
||||
|
||||
for (i = 0; i < 3; i++) |
||||
write_eeprom_reg(*(((u16 *)eaddr) + i), 0x20 + i); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static int parse_element(char *s, unsigned char *buf, int len) |
||||
{ |
||||
int cnt; |
||||
char *p, num[3]; |
||||
unsigned char id; |
||||
|
||||
id = simple_strtoul(s, &p, 16); |
||||
if (*p++ != ':') |
||||
return -1; |
||||
cnt = 2; |
||||
num[2] = 0; |
||||
for (; *p; p += 2) { |
||||
if (p[1] == 0) |
||||
return -2; |
||||
if (cnt + 3 > len) |
||||
return -3; |
||||
num[0] = p[0]; |
||||
num[1] = p[1]; |
||||
buf[cnt++] = simple_strtoul(num, NULL, 16); |
||||
} |
||||
buf[0] = id; |
||||
buf[1] = cnt - 2; |
||||
|
||||
return cnt; |
||||
} |
||||
|
||||
extern int crcek(void); |
||||
|
||||
int eeprom(int argc, char *argv[]) |
||||
{ |
||||
int i, len, ret; |
||||
unsigned char buf[58], *p; |
||||
|
||||
app_startup(argv); |
||||
if (get_version() != XF_VERSION) { |
||||
printf("Wrong XF_VERSION.\n"); |
||||
printf("Application expects ABI version %d\n", XF_VERSION); |
||||
printf("Actual U-Boot ABI version %d\n", (int)get_version()); |
||||
return 1; |
||||
} |
||||
|
||||
return crcek(); |
||||
|
||||
if ((SMC_inw (BANK_SELECT) & 0xFF00) != 0x3300) { |
||||
printf("SMSC91111 not found.\n"); |
||||
return 2; |
||||
} |
||||
|
||||
/* Called without parameters - print MAC address */ |
||||
if (argc < 2) { |
||||
verify_macaddr(NULL); |
||||
return 0; |
||||
} |
||||
|
||||
/* Print help message */ |
||||
if (argv[1][1] == 'h') { |
||||
printf("VoiceBlue EEPROM writer\n"); |
||||
printf("Built: %s at %s\n", __DATE__ , __TIME__ ); |
||||
printf("Usage:\n\t<mac_address> [<element_1>] [<...>]\n"); |
||||
return 0; |
||||
} |
||||
|
||||
/* Try to parse information elements */ |
||||
len = sizeof(buf); |
||||
p = buf; |
||||
for (i = 2; i < argc; i++) { |
||||
ret = parse_element(argv[i], p, len); |
||||
switch (ret) { |
||||
case -1: |
||||
printf("Element %d: malformed\n", i - 1); |
||||
return 3; |
||||
case -2: |
||||
printf("Element %d: odd character count\n", i - 1); |
||||
return 3; |
||||
case -3: |
||||
printf("Out of EEPROM memory\n"); |
||||
return 3; |
||||
default: |
||||
p += ret; |
||||
len -= ret; |
||||
} |
||||
} |
||||
|
||||
/* First argument (MAC) is mandatory */ |
||||
set_mac(argv[1]); |
||||
if (verify_macaddr(argv[1])) { |
||||
printf("*** MAC address does not match! ***\n"); |
||||
return 4; |
||||
} |
||||
|
||||
while (len--) |
||||
*p++ = 0; |
||||
|
||||
write_data((u16 *)buf, sizeof(buf) >> 1); |
||||
|
||||
return 0; |
||||
} |
||||
@ -0,0 +1,51 @@ |
||||
/* |
||||
* (C) Copyright 2002 |
||||
* Gary Jennejohn, DENX Software Engineering, <gj@denx.de> |
||||
* (C) Copyright 2005 |
||||
* Ladislav Michl, 2N Telekomunikace, <michl@2n.cz> |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") |
||||
OUTPUT_ARCH(arm) |
||||
ENTRY(_start) |
||||
SECTIONS |
||||
{ |
||||
. = ALIGN(4); |
||||
.text : |
||||
{ |
||||
eeprom_start.o (.text) |
||||
*(.text) |
||||
} |
||||
|
||||
. = ALIGN(4); |
||||
.rodata : { *(.rodata) } |
||||
|
||||
. = ALIGN(4); |
||||
.data : { *(.data) } |
||||
|
||||
. = ALIGN(4); |
||||
.got : { *(.got) } |
||||
|
||||
. = ALIGN(4); |
||||
__bss_start = .; |
||||
.bss : { *(.bss) } |
||||
_end = .; |
||||
} |
||||
@ -0,0 +1,177 @@ |
||||
/* |
||||
* Copyright (c) 2005 2N Telekomunikace |
||||
* |
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License |
||||
* version 2 as published by the Free Software Foundation. |
||||
* |
||||
*/ |
||||
|
||||
.globl _start
|
||||
_start: b eeprom |
||||
|
||||
#include "crcek.h" |
||||
|
||||
/** |
||||
* do_crc32 - calculate CRC32 of given buffer |
||||
* r0 - crc |
||||
* r1 - pointer to buffer |
||||
* r2 - buffer len |
||||
*/ |
||||
.macro do_crc32
|
||||
ldr r5, FFFFFFFF |
||||
eor r0, r0, r5 |
||||
adr r3, CRC32_TABLE |
||||
1: |
||||
ldrb r4, [r1], #1 |
||||
eor r4, r4, r0 |
||||
and r4, r4, #0xff |
||||
ldr r4, [r3, r4, lsl#2] |
||||
eor r0, r4, r0, lsr#8 |
||||
subs r2, r2, #0x1 |
||||
bne 1b |
||||
eor r0, r0, r5 |
||||
.endm |
||||
|
||||
.macro crcuj, offset, size |
||||
ldr r1, \offset |
||||
ldr r2, [r1] |
||||
cmp r2, #0 @ no data, no problem
|
||||
beq 2f |
||||
mov r7, #1 |
||||
tst r2, #3 @ unaligned size
|
||||
bne 2f |
||||
mov r7, #2 |
||||
ldr r0, \size |
||||
cmp r2, r0 @ bogus size
|
||||
bhi 2f |
||||
mov r7, #3 |
||||
add r1, r1, #4 |
||||
mov r0, #0 |
||||
do_crc32 |
||||
ldr r1, [r1] |
||||
2: |
||||
cmp r0, r1 |
||||
.endm |
||||
|
||||
.macro wait, reg |
||||
mov \reg, #0x1000 |
||||
3: |
||||
subs \reg, \reg, #0x1 |
||||
bne 3b |
||||
|
||||
.endm |
||||
.text |
||||
.globl crcek
|
||||
crcek: |
||||
mov r6, #0 |
||||
@ crcuj _LOADER1_OFFSET, _LOADER_SIZE
|
||||
@ bne crc1_bad
|
||||
@ orr r6, r6, #1
|
||||
crc1_bad: |
||||
crcuj _LOADER2_OFFSET, _LOADER_SIZE |
||||
bne crc2_bad |
||||
orr r6, r6, #2 |
||||
crc2_bad: |
||||
@ mov r0, r6
|
||||
mov pc, lr |
||||
ldr r3, _LOADER1_OFFSET |
||||
ldr r4, _LOADER2_OFFSET |
||||
tst r6, #3 |
||||
beq one_is_bad @ one of them (or both) has bad crc
|
||||
ldr r1, [r3, #4] |
||||
ldr r2, [r4, #4] |
||||
cmp r1, r2 @ boot 2nd loader if versions differ
|
||||
beq boot_1st |
||||
b boot_2nd |
||||
one_is_bad: |
||||
tst r6, #1 |
||||
bne boot_1st |
||||
tst r6, #2 |
||||
bne boot_2nd |
||||
@ We are doomed, so let user know.
|
||||
ldr r0, GPIO_BASE @ configure GPIO pins
|
||||
ldr r1, GPIO_DIRECTION |
||||
strh r1, [r0, #0x08] |
||||
blink_loop: |
||||
mov r1, #0x08 |
||||
strh r1, [r0, #0x04] |
||||
wait r3 |
||||
mov r1, #0x10 |
||||
strh r1, [r0, #0x04] |
||||
wait r3 |
||||
b blink_loop |
||||
boot_1st: |
||||
add pc, r3, #8 |
||||
boot_2nd: |
||||
add pc, r4, #8 |
||||
|
||||
_LOADER_SIZE: |
||||
.word LOADER_SIZE - 8 @ minus size and crc32
|
||||
_LOADER1_OFFSET: |
||||
.word LOADER1_OFFSET
|
||||
_LOADER2_OFFSET: |
||||
.word LOADER2_OFFSET
|
||||
|
||||
FFFFFFFF: |
||||
.word 0xffffffff
|
||||
CRC32_TABLE: |
||||
.word 0x00000000, 0x77073096, 0xee0e612c, 0x990951ba, 0x076dc419 |
||||
.word 0x706af48f, 0xe963a535, 0x9e6495a3, 0x0edb8832, 0x79dcb8a4 |
||||
.word 0xe0d5e91e, 0x97d2d988, 0x09b64c2b, 0x7eb17cbd, 0xe7b82d07 |
||||
.word 0x90bf1d91, 0x1db71064, 0x6ab020f2, 0xf3b97148, 0x84be41de |
||||
.word 0x1adad47d, 0x6ddde4eb, 0xf4d4b551, 0x83d385c7, 0x136c9856 |
||||
.word 0x646ba8c0, 0xfd62f97a, 0x8a65c9ec, 0x14015c4f, 0x63066cd9 |
||||
.word 0xfa0f3d63, 0x8d080df5, 0x3b6e20c8, 0x4c69105e, 0xd56041e4 |
||||
.word 0xa2677172, 0x3c03e4d1, 0x4b04d447, 0xd20d85fd, 0xa50ab56b |
||||
.word 0x35b5a8fa, 0x42b2986c, 0xdbbbc9d6, 0xacbcf940, 0x32d86ce3 |
||||
.word 0x45df5c75, 0xdcd60dcf, 0xabd13d59, 0x26d930ac, 0x51de003a |
||||
.word 0xc8d75180, 0xbfd06116, 0x21b4f4b5, 0x56b3c423, 0xcfba9599 |
||||
.word 0xb8bda50f, 0x2802b89e, 0x5f058808, 0xc60cd9b2, 0xb10be924 |
||||
.word 0x2f6f7c87, 0x58684c11, 0xc1611dab, 0xb6662d3d, 0x76dc4190 |
||||
.word 0x01db7106, 0x98d220bc, 0xefd5102a, 0x71b18589, 0x06b6b51f |
||||
.word 0x9fbfe4a5, 0xe8b8d433, 0x7807c9a2, 0x0f00f934, 0x9609a88e |
||||
.word 0xe10e9818, 0x7f6a0dbb, 0x086d3d2d, 0x91646c97, 0xe6635c01 |
||||
.word 0x6b6b51f4, 0x1c6c6162, 0x856530d8, 0xf262004e, 0x6c0695ed |
||||
.word 0x1b01a57b, 0x8208f4c1, 0xf50fc457, 0x65b0d9c6, 0x12b7e950 |
||||
.word 0x8bbeb8ea, 0xfcb9887c, 0x62dd1ddf, 0x15da2d49, 0x8cd37cf3 |
||||
.word 0xfbd44c65, 0x4db26158, 0x3ab551ce, 0xa3bc0074, 0xd4bb30e2 |
||||
.word 0x4adfa541, 0x3dd895d7, 0xa4d1c46d, 0xd3d6f4fb, 0x4369e96a |
||||
.word 0x346ed9fc, 0xad678846, 0xda60b8d0, 0x44042d73, 0x33031de5 |
||||
.word 0xaa0a4c5f, 0xdd0d7cc9, 0x5005713c, 0x270241aa, 0xbe0b1010 |
||||
.word 0xc90c2086, 0x5768b525, 0x206f85b3, 0xb966d409, 0xce61e49f |
||||
.word 0x5edef90e, 0x29d9c998, 0xb0d09822, 0xc7d7a8b4, 0x59b33d17 |
||||
.word 0x2eb40d81, 0xb7bd5c3b, 0xc0ba6cad, 0xedb88320, 0x9abfb3b6 |
||||
.word 0x03b6e20c, 0x74b1d29a, 0xead54739, 0x9dd277af, 0x04db2615 |
||||
.word 0x73dc1683, 0xe3630b12, 0x94643b84, 0x0d6d6a3e, 0x7a6a5aa8 |
||||
.word 0xe40ecf0b, 0x9309ff9d, 0x0a00ae27, 0x7d079eb1, 0xf00f9344 |
||||
.word 0x8708a3d2, 0x1e01f268, 0x6906c2fe, 0xf762575d, 0x806567cb |
||||
.word 0x196c3671, 0x6e6b06e7, 0xfed41b76, 0x89d32be0, 0x10da7a5a |
||||
.word 0x67dd4acc, 0xf9b9df6f, 0x8ebeeff9, 0x17b7be43, 0x60b08ed5 |
||||
.word 0xd6d6a3e8, 0xa1d1937e, 0x38d8c2c4, 0x4fdff252, 0xd1bb67f1 |
||||
.word 0xa6bc5767, 0x3fb506dd, 0x48b2364b, 0xd80d2bda, 0xaf0a1b4c |
||||
.word 0x36034af6, 0x41047a60, 0xdf60efc3, 0xa867df55, 0x316e8eef |
||||
.word 0x4669be79, 0xcb61b38c, 0xbc66831a, 0x256fd2a0, 0x5268e236 |
||||
.word 0xcc0c7795, 0xbb0b4703, 0x220216b9, 0x5505262f, 0xc5ba3bbe |
||||
.word 0xb2bd0b28, 0x2bb45a92, 0x5cb36a04, 0xc2d7ffa7, 0xb5d0cf31 |
||||
.word 0x2cd99e8b, 0x5bdeae1d, 0x9b64c2b0, 0xec63f226, 0x756aa39c |
||||
.word 0x026d930a, 0x9c0906a9, 0xeb0e363f, 0x72076785, 0x05005713 |
||||
.word 0x95bf4a82, 0xe2b87a14, 0x7bb12bae, 0x0cb61b38, 0x92d28e9b |
||||
.word 0xe5d5be0d, 0x7cdcefb7, 0x0bdbdf21, 0x86d3d2d4, 0xf1d4e242 |
||||
.word 0x68ddb3f8, 0x1fda836e, 0x81be16cd, 0xf6b9265b, 0x6fb077e1 |
||||
.word 0x18b74777, 0x88085ae6, 0xff0f6a70, 0x66063bca, 0x11010b5c |
||||
.word 0x8f659eff, 0xf862ae69, 0x616bffd3, 0x166ccf45, 0xa00ae278 |
||||
.word 0xd70dd2ee, 0x4e048354, 0x3903b3c2, 0xa7672661, 0xd06016f7 |
||||
.word 0x4969474d, 0x3e6e77db, 0xaed16a4a, 0xd9d65adc, 0x40df0b66 |
||||
.word 0x37d83bf0, 0xa9bcae53, 0xdebb9ec5, 0x47b2cf7f, 0x30b5ffe9 |
||||
.word 0xbdbdf21c, 0xcabac28a, 0x53b39330, 0x24b4a3a6, 0xbad03605 |
||||
.word 0xcdd70693, 0x54de5729, 0x23d967bf, 0xb3667a2e, 0xc4614ab8 |
||||
.word 0x5d681b02, 0x2a6f2b94, 0xb40bbe37, 0xc30c8ea1, 0x5a05df1b |
||||
.word 0x2d02ef8d
|
||||
|
||||
GPIO_BASE: |
||||
.word 0xfffce000
|
||||
GPIO_DIRECTION: |
||||
.word 0x0000ffe7
|
||||
|
||||
.end |
||||
@ -0,0 +1,343 @@ |
||||
/*
|
||||
* (C) Copyright 2002 |
||||
* Sysgo Real-Time Solutions, GmbH <www.elinos.com> |
||||
* Alex Zuepke <azu@sysgo.de> |
||||
* |
||||
* (C) Copyright 2005 |
||||
* 2N Telekomunikace, a.s. <www.2n.cz> |
||||
* Ladislav Michl <michl@2n.cz> |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
|
||||
/*#if 0 */ |
||||
#if (PHYS_SDRAM_1_SIZE != SZ_32M) |
||||
|
||||
#include "crcek.h" |
||||
|
||||
#if (CFG_MAX_FLASH_BANKS > 1) |
||||
#error There is always only _one_ flash chip |
||||
#endif |
||||
|
||||
flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; |
||||
|
||||
#define CMD_READ_ARRAY 0x000000f0 |
||||
#define CMD_UNLOCK1 0x000000aa |
||||
#define CMD_UNLOCK2 0x00000055 |
||||
#define CMD_ERASE_SETUP 0x00000080 |
||||
#define CMD_ERASE_CONFIRM 0x00000030 |
||||
#define CMD_PROGRAM 0x000000a0 |
||||
#define CMD_UNLOCK_BYPASS 0x00000020 |
||||
|
||||
#define MEM_FLASH_ADDR1 (*(volatile u16 *)(CFG_FLASH_BASE + (0x00000555 << 1))) |
||||
#define MEM_FLASH_ADDR2 (*(volatile u16 *)(CFG_FLASH_BASE + (0x000002aa << 1))) |
||||
|
||||
#define BIT_ERASE_DONE 0x00000080 |
||||
#define BIT_RDY_MASK 0x00000080 |
||||
#define BIT_PROGRAM_ERROR 0x00000020 |
||||
#define BIT_TIMEOUT 0x80000000 /* our flag */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/ |
||||
|
||||
ulong flash_init(void) |
||||
{ |
||||
int i; |
||||
|
||||
flash_info[0].flash_id = (AMD_MANUFACT & FLASH_VENDMASK) | |
||||
(AMD_ID_LV800B & FLASH_TYPEMASK); |
||||
flash_info[0].size = PHYS_FLASH_1_SIZE; |
||||
flash_info[0].sector_count = CFG_MAX_FLASH_SECT; |
||||
memset(flash_info[0].protect, 0, CFG_MAX_FLASH_SECT); |
||||
|
||||
for (i = 0; i < flash_info[0].sector_count; i++) { |
||||
switch (i) { |
||||
case 0: /* 16kB */ |
||||
flash_info[0].start[0] = CFG_FLASH_BASE; |
||||
break; |
||||
case 1: /* 8kB */ |
||||
flash_info[0].start[1] = CFG_FLASH_BASE + 0x4000; |
||||
break; |
||||
case 2: /* 8kB */ |
||||
flash_info[0].start[2] = CFG_FLASH_BASE + 0x4000 + |
||||
0x2000; |
||||
break; |
||||
case 3: /* 32 KB */ |
||||
flash_info[0].start[3] = CFG_FLASH_BASE + 0x4000 + |
||||
2 * 0x2000; |
||||
break; |
||||
case 4: |
||||
flash_info[0].start[4] = CFG_FLASH_BASE + 0x4000 + |
||||
2 * 0x2000 + 0x8000; |
||||
break; |
||||
default: /* 64kB */ |
||||
flash_info[0].start[i] = flash_info[0].start[i-1] + |
||||
0x10000; |
||||
break; |
||||
} |
||||
} |
||||
|
||||
/* U-Boot */ |
||||
flash_protect(FLAG_PROTECT_SET, |
||||
LOADER1_OFFSET, |
||||
LOADER1_OFFSET + LOADER_SIZE - 1, flash_info); |
||||
/* Protect crcek, env and r_env as well */ |
||||
flash_protect(FLAG_PROTECT_SET, 0, 0x8000 - 1, flash_info); |
||||
|
||||
return flash_info[0].size; |
||||
} |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/ |
||||
void flash_print_info(flash_info_t *info) |
||||
{ |
||||
int i; |
||||
|
||||
switch (info->flash_id & FLASH_VENDMASK) { |
||||
case (AMD_MANUFACT & FLASH_VENDMASK): |
||||
puts("AMD: "); |
||||
break; |
||||
default: |
||||
puts("Unknown vendor "); |
||||
break; |
||||
} |
||||
|
||||
switch (info->flash_id & FLASH_TYPEMASK) { |
||||
case (AMD_ID_LV800B & FLASH_TYPEMASK): |
||||
puts("AM29LV800BB (8Mb)\n"); |
||||
break; |
||||
default: |
||||
puts("Unknown chip type\n"); |
||||
return; |
||||
} |
||||
|
||||
printf(" Size: %ld MB in %d sectors\n", |
||||
info->size >> 20, info->sector_count); |
||||
|
||||
puts(" Sector start addresses:"); |
||||
for (i = 0; i < info->sector_count; i++) { |
||||
if ((i % 5) == 0) |
||||
puts("\n "); |
||||
|
||||
printf(" %08lX%s", info->start[i], |
||||
info->protect[i] ? " (RO)" : " "); |
||||
} |
||||
puts("\n"); |
||||
} |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/ |
||||
|
||||
int flash_erase(flash_info_t *info, int s_first, int s_last) |
||||
{ |
||||
ushort result; |
||||
int prot, sect; |
||||
int rc = ERR_OK; |
||||
|
||||
/* first look for protection bits */ |
||||
|
||||
if (info->flash_id == FLASH_UNKNOWN) |
||||
return ERR_UNKNOWN_FLASH_TYPE; |
||||
|
||||
if ((s_first < 0) || (s_first > s_last)) |
||||
return ERR_INVAL; |
||||
|
||||
if ((info->flash_id & FLASH_VENDMASK) != |
||||
(AMD_MANUFACT & FLASH_VENDMASK)) |
||||
return ERR_UNKNOWN_FLASH_VENDOR; |
||||
|
||||
prot = 0; |
||||
for (sect = s_first; sect <= s_last; ++sect) |
||||
if (info->protect[sect]) |
||||
prot++; |
||||
|
||||
if (prot) |
||||
printf("- Warning: %d protected sectors will not be erased!\n", |
||||
prot); |
||||
else |
||||
putc('\n'); |
||||
|
||||
/* Start erase on unprotected sectors */ |
||||
for (sect = s_first; sect <= s_last && !ctrlc (); sect++) { |
||||
if (info->protect[sect] == 0) { /* not protected */ |
||||
vu_short *addr = (vu_short *) (info->start[sect]); |
||||
|
||||
/* arm simple, non interrupt dependent timer */ |
||||
reset_timer_masked(); |
||||
|
||||
MEM_FLASH_ADDR1 = CMD_UNLOCK1; |
||||
MEM_FLASH_ADDR2 = CMD_UNLOCK2; |
||||
MEM_FLASH_ADDR1 = CMD_ERASE_SETUP; |
||||
|
||||
MEM_FLASH_ADDR1 = CMD_UNLOCK1; |
||||
MEM_FLASH_ADDR2 = CMD_UNLOCK2; |
||||
*addr = CMD_ERASE_CONFIRM; |
||||
|
||||
/* wait until flash is ready */ |
||||
while (1) { |
||||
result = *addr; |
||||
|
||||
/* check timeout */ |
||||
if (get_timer_masked() > CFG_FLASH_ERASE_TOUT) { |
||||
MEM_FLASH_ADDR1 = CMD_READ_ARRAY; |
||||
rc = ERR_TIMOUT; |
||||
break; |
||||
} |
||||
|
||||
if ((result & 0xfff) & BIT_ERASE_DONE) |
||||
break; |
||||
|
||||
if ((result & 0xffff) & BIT_PROGRAM_ERROR) { |
||||
rc = ERR_PROG_ERROR; |
||||
break; |
||||
} |
||||
} |
||||
|
||||
MEM_FLASH_ADDR1 = CMD_READ_ARRAY; |
||||
|
||||
if (rc != ERR_OK) |
||||
goto out; |
||||
|
||||
putc('.'); |
||||
} |
||||
} |
||||
out: |
||||
/* allow flash to settle - wait 10 ms */ |
||||
udelay_masked(10000); |
||||
|
||||
return rc; |
||||
} |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Copy memory to flash |
||||
*/ |
||||
|
||||
static int write_hword(flash_info_t *info, ulong dest, ushort data) |
||||
{ |
||||
vu_short *addr = (vu_short *) dest; |
||||
ushort result; |
||||
int rc = ERR_OK; |
||||
|
||||
/* check if flash is (sufficiently) erased */ |
||||
result = *addr; |
||||
if ((result & data) != data) |
||||
return ERR_NOT_ERASED; |
||||
|
||||
MEM_FLASH_ADDR1 = CMD_UNLOCK1; |
||||
MEM_FLASH_ADDR2 = CMD_UNLOCK2; |
||||
MEM_FLASH_ADDR1 = CMD_PROGRAM; |
||||
*addr = data; |
||||
|
||||
/* arm simple, non interrupt dependent timer */ |
||||
reset_timer_masked(); |
||||
|
||||
/* wait until flash is ready */ |
||||
while (1) { |
||||
result = *addr; |
||||
|
||||
/* check timeout */ |
||||
if (get_timer_masked () > CFG_FLASH_ERASE_TOUT) { |
||||
rc = ERR_TIMOUT; |
||||
break; |
||||
} |
||||
|
||||
if ((result & 0x80) == (data & 0x80)) |
||||
break; |
||||
|
||||
if ((result & 0xffff) & BIT_PROGRAM_ERROR) { |
||||
result = *addr; |
||||
|
||||
if ((result & 0x80) != (data & 0x80)) |
||||
rc = ERR_PROG_ERROR; |
||||
} |
||||
} |
||||
|
||||
*addr = CMD_READ_ARRAY; |
||||
|
||||
if (*addr != data) |
||||
rc = ERR_PROG_ERROR; |
||||
|
||||
return rc; |
||||
} |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Copy memory to flash. |
||||
*/ |
||||
|
||||
int write_buff(flash_info_t *info, uchar *src, ulong addr, ulong cnt) |
||||
{ |
||||
ulong cp, wp; |
||||
int l; |
||||
int i, rc; |
||||
ushort data; |
||||
|
||||
wp = (addr & ~1); /* get lower word aligned address */ |
||||
|
||||
/*
|
||||
* handle unaligned start bytes |
||||
*/ |
||||
if ((l = addr - wp) != 0) { |
||||
data = 0; |
||||
for (i = 0, cp = wp; i < l; ++i, ++cp) |
||||
data = (data >> 8) | (*(uchar *) cp << 8); |
||||
for (; i < 2 && cnt > 0; ++i) { |
||||
data = (data >> 8) | (*src++ << 8); |
||||
--cnt; |
||||
++cp; |
||||
} |
||||
for (; cnt == 0 && i < 2; ++i, ++cp) |
||||
data = (data >> 8) | (*(uchar *) cp << 8); |
||||
|
||||
if ((rc = write_hword(info, wp, data)) != 0) |
||||
return (rc); |
||||
wp += 2; |
||||
} |
||||
|
||||
/*
|
||||
* handle word aligned part |
||||
*/ |
||||
while (cnt >= 2) { |
||||
data = *((vu_short *) src); |
||||
if ((rc = write_hword(info, wp, data)) != 0) |
||||
return (rc); |
||||
src += 2; |
||||
wp += 2; |
||||
cnt -= 2; |
||||
} |
||||
|
||||
if (cnt == 0) |
||||
return ERR_OK; |
||||
|
||||
/*
|
||||
* handle unaligned tail bytes |
||||
*/ |
||||
data = 0; |
||||
for (i = 0, cp = wp; i < 2 && cnt > 0; ++i, ++cp) { |
||||
data = (data >> 8) | (*src++ << 8); |
||||
--cnt; |
||||
} |
||||
for (; i < 2; ++i, ++cp) |
||||
data = (data >> 8) | (*(uchar *) cp << 8); |
||||
|
||||
return write_hword(info, wp, data); |
||||
} |
||||
|
||||
#endif |
||||
@ -0,0 +1,66 @@ |
||||
/*
|
||||
* (C) Copyright 2005 2N TELEKOMUNIKACE, Ladislav Michl |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_NAND) |
||||
|
||||
#include <nand.h> |
||||
|
||||
/*
|
||||
* hardware specific access to control-lines |
||||
*/ |
||||
#define MASK_CLE 0x02 |
||||
#define MASK_ALE 0x04 |
||||
|
||||
static void netstar_nand_hwcontrol(struct mtd_info *mtd, int cmd) |
||||
{ |
||||
struct nand_chip *this = mtd->priv; |
||||
ulong IO_ADDR_W = (ulong) this->IO_ADDR_W; |
||||
|
||||
IO_ADDR_W &= ~(MASK_ALE|MASK_CLE); |
||||
switch (cmd) { |
||||
case NAND_CTL_SETCLE: IO_ADDR_W |= MASK_CLE; break; |
||||
case NAND_CTL_SETALE: IO_ADDR_W |= MASK_ALE; break; |
||||
} |
||||
this->IO_ADDR_W = (void *) IO_ADDR_W; |
||||
} |
||||
|
||||
/*
|
||||
* chip R/B detection |
||||
*/ |
||||
/***
|
||||
static int netstar_nand_ready(struct mtd_info *mtd) |
||||
{ |
||||
return (*(volatile ushort *)GPIO_DATA_INPUT_REG) & 0x02; |
||||
} |
||||
***/ |
||||
|
||||
void board_nand_init(struct nand_chip *nand) |
||||
{ |
||||
nand->options = NAND_SAMSUNG_LP_OPTIONS; |
||||
nand->eccmode = NAND_ECC_SOFT; |
||||
nand->hwcontrol = netstar_nand_hwcontrol; |
||||
/* nand->dev_ready = netstar_nand_ready; */ |
||||
nand->chip_delay = 18; |
||||
} |
||||
#endif |
||||
@ -0,0 +1,68 @@ |
||||
/*
|
||||
* (C) Copyright 2005 2N TELEKOMUNIKACE, Ladislav Michl |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
|
||||
int board_init(void) |
||||
{ |
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
/* arch number of NetStar board */ |
||||
/* TODO: use define from asm/mach-types.h */ |
||||
gd->bd->bi_arch_number = 692; |
||||
|
||||
/* adress of boot parameters */ |
||||
gd->bd->bi_boot_params = 0x10000100; |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
int dram_init(void) |
||||
{ |
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
gd->bd->bi_dram[0].start = PHYS_SDRAM_1; |
||||
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; |
||||
|
||||
/* Take the Ethernet controller out of reset and wait
|
||||
* for the EEPROM load to complete. */ |
||||
*((volatile unsigned short *) GPIO_DATA_OUTPUT_REG) |= 0x80; |
||||
udelay(10); /* doesn't work before interrupt_init call */ |
||||
*((volatile unsigned short *) GPIO_DATA_OUTPUT_REG) &= ~0x80; |
||||
udelay(500); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
extern void partition_flash(void); |
||||
|
||||
int misc_init_r(void) |
||||
{ |
||||
return 0; |
||||
} |
||||
|
||||
extern void nand_init(void); |
||||
|
||||
int board_late_init(void) |
||||
{ |
||||
return 0; |
||||
} |
||||
@ -0,0 +1,287 @@ |
||||
/* |
||||
* Board specific setup info |
||||
* |
||||
* (C) Copyright 2004 Ales Jindra <jindra@2n.cz>
|
||||
* (C) Copyright 2005 Ladislav Michl <michl@2n.cz>
|
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <config.h> |
||||
#include <version.h> |
||||
|
||||
_TEXT_BASE: |
||||
.word TEXT_BASE /* SDRAM load addr from config.mk */ |
||||
|
||||
OMAP5910_LPG1_BASE: .word 0xfffbd000 |
||||
OMAP5910_TIPB_SWITCHES_BASE: .word 0xfffbc800 |
||||
OMAP5910_MPU_TC_BASE: .word 0xfffecc00 |
||||
OMAP5910_MPU_CLKM_BASE: .word 0xfffece00 |
||||
OMAP5910_ULPD_PWR_MNG_BASE: .word 0xfffe0800 |
||||
OMAP5910_DPLL1_BASE: .word 0xfffecf00 |
||||
OMAP5910_GPIO_BASE: .word 0xfffce000 |
||||
OMAP5910_MPU_WD_TIMER_BASE: .word 0xfffec800 |
||||
OMAP5910_MPUI_BASE: .word 0xfffec900 |
||||
|
||||
_OMAP5910_ARM_CKCTL: .word OMAP5910_ARM_CKCTL |
||||
_OMAP5910_ARM_EN_CLK: .word OMAP5910_ARM_EN_CLK |
||||
|
||||
OMAP5910_MPUI_CTRL: .word 0x0000ff1b |
||||
|
||||
VAL_EMIFS_CS0_CONFIG: .word 0x00009090 |
||||
VAL_EMIFS_CS1_CONFIG: .word 0x00003031 |
||||
VAL_EMIFS_CS2_CONFIG: .word 0x0000a0a1 |
||||
VAL_EMIFS_CS3_CONFIG: .word 0x0000c0c0 |
||||
VAL_EMIFS_DYN_WAIT: .word 0x00000000 |
||||
/* autorefresh counter 0x246 ((64000000/13.4)-400)/8192) */ |
||||
/* SLRF SD_RET ARE SDRAM_TYPE ARCV SDRAM_FREQUENCY PWD CLK */ |
||||
|
||||
#if (PHYS_SDRAM_1_SIZE == SZ_32M) |
||||
VAL_EMIFF_SDRAM_CONFIG: .word ((0 << 0) | (0 << 1) | (3 << 2) | (0xf << 4) | (0x246 << 8) | (0 << 24) | (0 << 26) | (0 << 27)) |
||||
#else |
||||
VAL_EMIFF_SDRAM_CONFIG: .word ((0 << 0) | (0 << 1) | (3 << 2) | (0xd << 4) | (0x246 << 8) | (0 << 24) | (0 << 26) | (0 << 27)) |
||||
#endif |
||||
|
||||
VAL_EMIFF_SDRAM_CONFIG2: .word 0x00000003 |
||||
VAL_EMIFF_MRS: .word 0x00000037 |
||||
|
||||
/* |
||||
* GPIO04 - Green LED (Red LED is connected to LED Pulse Generator) |
||||
* GPIO07 - LAN91C111 reset |
||||
*/ |
||||
GPIO_DIRECTION: |
||||
.word 0x0000ff6f
|
||||
/* |
||||
* Disable everything (green LED is connected via invertor) |
||||
*/ |
||||
GPIO_OUTPUT: |
||||
.word 0x00000010
|
||||
|
||||
MUX_CONFIG_BASE: |
||||
.word 0xfffe1000
|
||||
|
||||
MUX_CONFIG_VALUES: |
||||
.align 4
|
||||
.word 0x00000000 @ FUNC_MUX_CTRL_0
|
||||
.word 0x00000000 @ FUNC_MUX_CTRL_1
|
||||
.word 0x00000000 @ FUNC_MUX_CTRL_2
|
||||
.word 0x00000000 @ FUNC_MUX_CTRL_3
|
||||
.word 0x00000000 @ FUNC_MUX_CTRL_4
|
||||
.word 0x02080480 @ FUNC_MUX_CTRL_5
|
||||
.word 0x0100001c @ FUNC_MUX_CTRL_6
|
||||
.word 0x0004800b @ FUNC_MUX_CTRL_7
|
||||
.word 0x10001200 @ FUNC_MUX_CTRL_8
|
||||
.word 0x01201012 @ FUNC_MUX_CTRL_9
|
||||
.word 0x02082248 @ FUNC_MUX_CTRL_A
|
||||
.word 0x00000248 @ FUNC_MUX_CTRL_B
|
||||
.word 0x12240000 @ FUNC_MUX_CTRL_C
|
||||
.word 0x00002000 @ FUNC_MUX_CTRL_D
|
||||
.word 0x00000000 @ PULL_DWN_CTRL_0
|
||||
.word 0x00000800 @ PULL_DWN_CTRL_1
|
||||
.word 0x01801000 @ PULL_DWN_CTRL_2
|
||||
.word 0x00000000 @ PULL_DWN_CTRL_3
|
||||
.word 0x00000000 @ GATE_INH_CTRL_0
|
||||
.word 0x00000000 @ VOLTAGE_CTRL_0
|
||||
.word 0x00000000 @ TEST_DBG_CTRL_0
|
||||
.word 0x00000006 @ MOD_CONF_CTRL_0
|
||||
.word 0x0000eaef @ COMP_MODE_CTRL_0
|
||||
|
||||
MUX_CONFIG_OFFSETS: |
||||
.align 1
|
||||
.byte 0x00 @ FUNC_MUX_CTRL_0
|
||||
.byte 0x04 @ FUNC_MUX_CTRL_1
|
||||
.byte 0x08 @ FUNC_MUX_CTRL_2
|
||||
.byte 0x10 @ FUNC_MUX_CTRL_3
|
||||
.byte 0x14 @ FUNC_MUX_CTRL_4
|
||||
.byte 0x18 @ FUNC_MUX_CTRL_5
|
||||
.byte 0x1c @ FUNC_MUX_CTRL_6
|
||||
.byte 0x20 @ FUNC_MUX_CTRL_7
|
||||
.byte 0x24 @ FUNC_MUX_CTRL_8
|
||||
.byte 0x28 @ FUNC_MUX_CTRL_9
|
||||
.byte 0x2c @ FUNC_MUX_CTRL_A
|
||||
.byte 0x30 @ FUNC_MUX_CTRL_B
|
||||
.byte 0x34 @ FUNC_MUX_CTRL_C
|
||||
.byte 0x38 @ FUNC_MUX_CTRL_D
|
||||
.byte 0x40 @ PULL_DWN_CTRL_0
|
||||
.byte 0x44 @ PULL_DWN_CTRL_1
|
||||
.byte 0x48 @ PULL_DWN_CTRL_2
|
||||
.byte 0x4c @ PULL_DWN_CTRL_3
|
||||
.byte 0x50 @ GATE_INH_CTRL_0
|
||||
.byte 0x60 @ VOLTAGE_CTRL_0
|
||||
.byte 0x70 @ TEST_DBG_CTRL_0
|
||||
.byte 0x80 @ MOD_CONF_CTRL_0
|
||||
.byte 0x0c @ COMP_MODE_CTRL_0
|
||||
.byte 0xff
|
||||
|
||||
.globl lowlevel_init
|
||||
lowlevel_init: |
||||
/* Improve performance a bit... */ |
||||
mrc p15, 0, r1, c0, c0, 0 @ read C15 ID register
|
||||
mrc p15, 0, r1, c0, c0, 1 @ read C15 Cache information register
|
||||
mrc p15, 0, r1, c1, c0, 0 @ read C15 Control register
|
||||
orr r1, r1, #0x1000 @ enable I-cache, map interrupt vector 0xffff0000
|
||||
mcr p15, 0, r1, c1, c0, 0 @ write C15 Control register
|
||||
mov r1, #0x00 |
||||
mcr p15, 0, r1, c7, c5, 0 @ Flush I-cache
|
||||
nop |
||||
nop |
||||
nop |
||||
nop |
||||
|
||||
/* Setup clocking mode */ |
||||
ldr r0, OMAP5910_MPU_CLKM_BASE @ prepare base of CLOCK unit
|
||||
ldrh r1, [r0, #0x18] @ get reset status
|
||||
bic r1, r1, #(7 << 11) @ clear clock select
|
||||
orr r1, r1, #(2 << 11) @ set synchronous scalable
|
||||
mov r2, #0 @ set wait counter to 100 clock cycles
|
||||
|
||||
icache_loop: |
||||
cmp r2, #0x01 |
||||
streqh r1, [r0, #0x18] |
||||
add r2, r2, #0x01 |
||||
cmp r2, #0x10 |
||||
bne icache_loop |
||||
nop |
||||
|
||||
/* Setup clock divisors */ |
||||
ldr r0, OMAP5910_MPU_CLKM_BASE @ base of CLOCK unit
|
||||
ldr r1, _OMAP5910_ARM_CKCTL |
||||
orr r1, r1, #0x2000 @ enable DSP clock
|
||||
strh r1, [r0, #0x00] @ setup clock divisors
|
||||
|
||||
/* Setup DPLL to generate requested freq */ |
||||
ldr r0, OMAP5910_DPLL1_BASE @ base of DPLL1 register
|
||||
mov r1, #0x0010 @ set PLL_ENABLE
|
||||
orr r1, r1, #0x2000 @ set IOB to new locking
|
||||
orr r1, r1, #(OMAP5910_DPLL_MUL << 7) @ setup multiplier CLKREF
|
||||
orr r1, r1, #(OMAP5910_DPLL_DIV << 5) @ setup divider CLKREF
|
||||
strh r1, [r0] @ write
|
||||
|
||||
locking: |
||||
ldrh r1, [r0] @ get DPLL value
|
||||
tst r1, #0x01 |
||||
beq locking @ while LOCK not set
|
||||
|
||||
/* Enable clock */ |
||||
ldr r0, OMAP5910_MPU_CLKM_BASE @ base of CLOCK unit
|
||||
mov r1, #(1 << 10) @ disable idle mode do not check
|
||||
@ nWAKEUP pin, other remain active
|
||||
strh r1, [r0, #0x04] |
||||
ldr r1, _OMAP5910_ARM_EN_CLK |
||||
strh r1, [r0, #0x08] |
||||
mov r1, #0x003f @ FLASH.RP not enabled in idle and
|
||||
@ max delayed ( 32 x CLKIN )
|
||||
strh r1, [r0, #0x0c] |
||||
|
||||
/* Configure 5910 pins functions to match our board. */ |
||||
ldr r0, MUX_CONFIG_BASE |
||||
adr r1, MUX_CONFIG_VALUES |
||||
adr r2, MUX_CONFIG_OFFSETS |
||||
next_mux_cfg: |
||||
ldrb r3, [r2], #1 |
||||
ldr r4, [r1], #4 |
||||
cmp r3, #0xff |
||||
strne r4, [r0, r3] |
||||
bne next_mux_cfg |
||||
|
||||
/* Configure GPIO pins (also disables Green LED) */ |
||||
ldr r0, OMAP5910_GPIO_BASE |
||||
ldr r1, GPIO_OUTPUT |
||||
strh r1, [r0, #0x04] |
||||
ldr r1, GPIO_DIRECTION |
||||
strh r1, [r0, #0x08] |
||||
|
||||
/* EnablePeripherals */ |
||||
ldr r0, OMAP5910_MPU_CLKM_BASE @ CLOCK unit
|
||||
mov r1, #0x0001 @ Peripheral enable
|
||||
strh r1, [r0, #0x14] |
||||
|
||||
/* Program LED Pulse Generator */ |
||||
ldr r0, OMAP5910_LPG1_BASE @ 1st LED Pulse Generator
|
||||
mov r1, #0x7F @ Set obscure frequency in
|
||||
strb r1, [r0, #0x00] @ LCR
|
||||
mov r1, #0x01 @ Enable clock (CLK_EN) in
|
||||
strb r1, [r0, #0x04] @ PMR
|
||||
|
||||
/* TIPB Lock UART1 */ |
||||
ldr r0, OMAP5910_TIPB_SWITCHES_BASE @ prepare base of TIPB switches
|
||||
mov r1, #1 @ ARM allocated
|
||||
strh r1, [r0,#0x04] @ clear IRQ line and status bits
|
||||
strh r1, [r0,#0x00] |
||||
ldrh r1, [r0,#0x04] |
||||
|
||||
/* Disable watchdog */ |
||||
ldr r0, OMAP5910_MPU_WD_TIMER_BASE |
||||
mov r1, #0xf5 |
||||
strh r1, [r0, #0x8] |
||||
mov r1, #0xa0 |
||||
strh r1, [r0, #0x8] |
||||
|
||||
/* Enable MCLK */ |
||||
ldr r0, OMAP5910_ULPD_PWR_MNG_BASE |
||||
mov r1, #0x6 |
||||
strh r1, [r0, #0x34] |
||||
strh r1, [r0, #0x34] |
||||
|
||||
/* Setup clock divisors */ |
||||
ldr r0, OMAP5910_ULPD_PWR_MNG_BASE @ base of ULDPL DPLL1 register
|
||||
|
||||
mov r1, #0x0010 @ set PLL_ENABLE
|
||||
orr r1, r1, #0x2000 @ set IOB to new locking
|
||||
strh r1, [r0] @ write
|
||||
|
||||
ulocking: |
||||
ldrh r1, [r0] @ get DPLL value
|
||||
tst r1, #1 |
||||
beq ulocking @ while LOCK not set
|
||||
|
||||
/* EMIF init */ |
||||
ldr r0, OMAP5910_MPU_TC_BASE |
||||
ldrh r1, [r0, #0x0c] @ EMIFS_CONFIG_REG
|
||||
bic r1, r1, #0x0c @ pwr down disabled, flash WP
|
||||
orr r1, r1, #0x01 |
||||
str r1, [r0, #0x0c] |
||||
|
||||
ldr r1, VAL_EMIFS_CS0_CONFIG |
||||
str r1, [r0, #0x10] @ EMIFS_CS0_CONFIG
|
||||
ldr r1, VAL_EMIFS_CS1_CONFIG |
||||
str r1, [r0, #0x14] @ EMIFS_CS1_CONFIG
|
||||
ldr r1, VAL_EMIFS_CS2_CONFIG |
||||
str r1, [r0, #0x18] @ EMIFS_CS2_CONFIG
|
||||
ldr r1, VAL_EMIFS_CS3_CONFIG |
||||
str r1, [r0, #0x1c] @ EMIFS_CS3_CONFIG
|
||||
ldr r1, VAL_EMIFS_DYN_WAIT |
||||
str r1, [r0, #0x40] @ EMIFS_CFG_DYN_WAIT
|
||||
|
||||
/* Setup SDRAM */ |
||||
ldr r1, VAL_EMIFF_SDRAM_CONFIG |
||||
str r1, [r0, #0x20] @ EMIFF_SDRAM_CONFIG
|
||||
ldr r1, VAL_EMIFF_SDRAM_CONFIG2 |
||||
str r1, [r0, #0x3c] @ EMIFF_SDRAM_CONFIG2
|
||||
ldr r1, VAL_EMIFF_MRS |
||||
str r1, [r0, #0x24] @ EMIFF_MRS
|
||||
/* SDRAM needs 100us to stabilize */ |
||||
mov r0, #0x4000 |
||||
sdelay: |
||||
subs r0, r0, #0x1 |
||||
bne sdelay |
||||
|
||||
/* back to arch calling code */ |
||||
mov pc, lr |
||||
.end |
||||
@ -0,0 +1,55 @@ |
||||
/* |
||||
* (C) Copyright 2002 |
||||
* Gary Jennejohn, DENX Software Engineering, <gj@denx.de> |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") |
||||
OUTPUT_ARCH(arm) |
||||
ENTRY(_start) |
||||
SECTIONS |
||||
{ |
||||
. = 0x00000000; |
||||
|
||||
. = ALIGN(4); |
||||
.text : |
||||
{ |
||||
cpu/arm925t/start.o (.text) |
||||
*(.text) |
||||
} |
||||
|
||||
. = ALIGN(4); |
||||
.rodata : { *(.rodata) } |
||||
|
||||
. = ALIGN(4); |
||||
.data : { *(.data) } |
||||
|
||||
. = ALIGN(4); |
||||
.got : { *(.got) } |
||||
|
||||
__u_boot_cmd_start = .; |
||||
.u_boot_cmd : { *(.u_boot_cmd) } |
||||
__u_boot_cmd_end = .; |
||||
|
||||
. = ALIGN(4); |
||||
__bss_start = .; |
||||
.bss : { *(.bss) } |
||||
_end = .; |
||||
} |
||||
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in new issue