This converts the following to Kconfig:
CONFIG_CONS_INDEX
We have existing entries for this option in a number of places, with
different guards on them. They're also sometimes used for things not
directly inside of the serial driver. First, introduce a new symbol to
guard the use of CONFIG_CONS_INDEX, so that in the case where we don't
need this for the serial driver, but for some other use, we can still do
it. Next, consolidate all of these into the single entry in
drivers/serial/Kconfig. Finally, introduce CONS_INDEX_[023456] so that
we can imply a correct value here to make the defconfig side of this
smaller.
Signed-off-by: Adam Ford <aford173@gmail.com>
[trini: Rework a lot of the logic here, such that I took authorship from
Adam, but kept his S-o-B line]
Signed-off-by: Tom Rini <trini@konsulko.com>
This SUNXI variant SPL SPI code doesn't use either SPI or
SPL_FLASG subsystems due to size constraints and also placing
this code in drivers/mtd/spi will unnecessary build SPI_FLASH
code(if defined) which never required, hence moved to arch area.
And also renamed the file according to kconfig which resembles
proper name.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Some H5 boards are designed to start at 1.1V CPUx voltage (e.g. Nano Pi
NEO2), which may not work properly at 1008MHz if the chip's quality is
not so good.
Lower the default CPUx frequency of H5 to 816MHz.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Extend DE2 driver with LCD support. Tested on Pinebook which is based
on A64 and has ANX6345 eDP bridge with eDP panel connected to it.
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
[agust: rebased v5 on u-boot-video/master]
Signed-off-by: Anatolij Gustschin <agust@denx.de>
As the support of EFI boot on Allwinner H3 is broken, we still need to
use simplefb to pass the framebuffer to Linux.
Add code to setup simplefb for Allwinner DE2 driver.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Add an option to indicate that the video driver should setup a SimpleFB
node that passes the video framebuffer initialized by U-Boot to the
operating system kernel.
Currently only the Allwinner DE driver uses this option, and the
definition of this option in the sunxi-common.h config header is
converted to an imply of this option from CONFIG_VIDEO_SUNXI.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The sunxi DE1 video option used to be CONFIG_VIDEO, which has the same
name as the "Enable legacy video support" option in
drivers/video/Kconfig.
Change the option name to CONFIG_VIDEO_SUNXI, which is really used by
Makefile under drivers/video/sunxi/, and defined in sunxi-common.h
when CONFIG_VIDEO is selected before this change. Now CONFIG_VIDEO_SUNXI
selects CONFIG_VIDEO and the usages of CONFIG_VIDEO in sunxi Kconfig and
config headers are all converted to use CONFIG_VIDEO_SUNXI.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
The eMMC controller for the A83T uses the new operating mode. Enable it.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
At present we support multiple environment drivers but there is not way to
select between them at run time. Also settings related to the position and
size of the environment area are global (i.e. apply to all locations).
Until these limitations are removed we cannot really support more than one
environment location. Adjust the location to be a choice so that only one
can be selected. By default the environment is 'nowhere', meaning that the
environment exists only in memory and cannot be saved.
Also expand the help for the 'nowhere' option and move it to the top since
it is the default.
Signed-off-by: Simon Glass <sjg@chromium.org>
[trini: Move all of the imply logic to default X if Y so it works again]
Signed-off-by: Tom Rini <trini@konsulko.com>
With SPL_LDSCRIPT moved to Kconfig (and this being a 'string' config
node), all the lingering definitions in header files will cause
warnings/errors due to the redefinition of the configuration item.
As we don't want to pollute the defconfig files (and values should
usually be identical for entire architectures), the defaults are moved
into Kconfig. Kconfig will always pick the first default that
matches, so please keep these values at the end of each file (to allow
any board-specific Kconfig, which will be included earlier) to
override with an unconditional default setting.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This converts the following to Kconfig:
CONFIG_ENV_IS_IN_MMC
CONFIG_ENV_IS_IN_NAND
CONFIG_ENV_IS_IN_UBI
CONFIG_ENV_IS_NOWHERE
In fact this already exists for sunxi as a 'choice' config. However not
all the choices are available in Kconfig yet so we cannot use that. It
would lead to more than one option being set.
In addition, one purpose of this series is to allow the environment to be
stored in more than one place. So the existing choice is converted to a
normal config allowing each option to be set independently.
There are not many opportunities for Kconfig updates to reduce the size of
this patch. This was tested with
./tools/moveconfig.py -i CONFIG_ENV_IS_IN_MMC
And then manual updates. This is because for CHAIN_OF_TRUST boards they
can only have ENV_IS_NOWHERE set, so we enforce that via Kconfig logic
now.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
As we added LPDDR3 support in the former patch, we need a set of timing
info to really enable it.
Add the timing info used by stock boot0.
Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
Acked-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
Some A64 boards (SoPine and Pinebook production batch) use LPDDR3 DRAM
chips.
Add support for LPDDR3 DRAM in the DesignWare-like DRAM controller code.
Real LPDDR3 chips' support is not added yet in this commit.
Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
As we have already support for the DesignWare DRAM controller and the
integrated DDR2 chip of V3s, let's enable the SPL support for V3s.
This patch also contains the default DRAM configuration for V3s.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
Allwinner V3s features a DRAM controller like the on in H3, but with a
DDR2 DRAM.
Add support for it.
Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
Allwinner V3s SoC features a co-packaged DDR2 DRAM chip, which needs its
timing param.
Add support for it.
Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
Acked-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
DRAM chip varies, and one code cannot satisfy all DRAMs.
Add options to select a timing set.
Currently only DDR3-1333 (the original set) is added into it.
Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
Some Allwinner SoCs features a DesignWare-like controller with only 16
bit bus width.
Add support for them.
Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
Allwinner SoCs after H3 (e.g. A64, H5, R40, V3s) uses a H3-like
DesignWare DRAM controller, which do not have official free DRAM
initialization code, but can use modified dram_sun8i_h3.c.
Add a invisible option for easier DRAM initialization code reuse.
Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
The Allwinner SoCs with 64-bit cores use an ARM Trusted Firmware binary,
which needs to be loaded alongside U-Boot proper.
Set the respective Kconfig options to let them select this feature and
also automatically build the FIT image.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
[Rename Kconfig path to arch/arm/mach-sunxi/Kconfig]
Signed-off-by: Jagan Teki <jagan@openedev.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
For the consistent location of SoC-level Kconfig.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
This commit adds support for HDMI output.
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
This commits enable DM I2C support for A64/H3/H5 SoCs.
It is not enabled globaly for all sunxi SoCs, because some boards use
PMICs which are connected through I2C. In order to keep same
functionality, PMIC drivers needs to be ported to DM too.
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Reviewed-by: Heiko Schocher <hs@denx.de>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Basic U-Boot support is now present for V3s.
Some memory addresses are changed specially for V3s, as the original
address map cannot fit into a so small DRAM.
As the DRAM controller code needs a big refactor, the SPL support is
disabled in this version.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
This is needed for HDMI, which will be added later.
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The R40's CPU controls are a combination of sun6i and sun7i.
All controls are in the CPUCFG block, and it seems the R40 does not
have a PRCM block. The core reset, power gating and clamp controls
are grouped like sun6i.
Last, the R40 does not have a secure SRAM block.
This patch adds a PSCI implementation for CPU bring-up and hotplug
for the R40.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Now that we can do DRAM initialization for the R40, we can enable
SPL support for it.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
These values were taken from the Banana Pi M2 Ultra fex file
found in the released vendor BSP. This is the only publicly
available R40 device at the time of this writing.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The R40 SoC uses the AXP221s in I2C mode to supply power.
Some regulator's common usages have changed, and also the recommended
voltage for existing usages have changed. Update the defaults to match.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The R40 is the successor to the A20. It is a hybrid of the A20, A33
and the H3.
The R40's PIO controller is compatible with the A20,
Reuse the A20 UART and I2C muxing code by adding the R40's macro.
The display pipeline is the newer DE 2.0 variant.
Block enabling video on R40 for now.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Currently we have some lines in board/sunxi/Kconfig that are very long.
These line either provide default values for a set of SoCs, or limit
some option to a subset of sunxi SoCs.
Fortunately Kconfig makes it easy to split them. The Kconfig language
document states
If multiple dependencies are defined, they are connected with '&&'.
This means we can split existing dependencies at "&&" symbols. This
applies to both the "depends on" lines and "if" expressions.
This patch splits them up to one symbol per line. This will make it
easier to add, remove, or modify one item at a time.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Convert the CONFIG_MACPWR to Kconfig and update all the sunxi defconfigs
that used it in SYS_EXTRA_OPTIONS.
Signed-off-by: Mylène Josserand <mylene.josserand@free-electrons.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Convert the CONFIG_SATAPWR into kconfig.
Thanks to that, many SYS_EXTRA_OPTIONS can be removed from some
defconfigs.
Signed-off-by: Mylène Josserand <mylene.josserand@free-electrons.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
spl_mmc.c calls mmc_initialize(). This symbol is provided in
drivers/mmc/mmc.c when CONFIG_GENERIC_MMC is enabled.
The sunxi Kconfig case is an oddball because it redefines
SPL_MMC_SUPPORT.
Signed-off-by: Alexandru Gagniuc <alex.g@adaptrum.com>
[trini: Update arch/arm/cpu/armv8/zynqmp/Kconfig]
Signed-off-by: Tom Rini <trini@konsulko.com>
The Allwinner H5 Soc is bascially an H3 with high SRAM and ARMv8 cores.
As the peripherals and the pinmuxing are almost identical, we piggy
back on the shared MACH_SUN8I_H3_H5 config symbol.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
The Allwinner H5 is very close to the H3 SoC, but has ARMv8 cores.
To allow sharing the clocks, GPIO and driver code easily, create an
architecture agnostic MACH_SUNXI_H3_H5 Kconfig symbol.
Rename the existing symbol to MACH_SUNXI_H3_H5 where code is shared and
let it be selected by a new shared Kconfig option.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Traditionally Allwinner SoCs have their boot ROM mapped just below 4GB,
while the first SRAM region is mapped at address 0.
With the extended physical memory support of the A80 this was changed,
so the BROM is now at address 0 and the SRAM region starts right behind
this at 64KB. This configuration seems to be called "high SRAM".
Instead of enumerating the SoCs which have copied this configuration,
let's call a spade a spade and introduce a Kconfig option for this setup.
SoCs implementing this (A80, A64 and H5, so far), can then select this
configuration.
Simplify the config header definition on the way.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Instead of enumerating all SoC families that need that bit set, let's
just express this more clearly: The SMP bits needs to be set on
SMP capable ARMv7 CPUs. It's much easier in Kconfig to express it the
other way round, so we use ! CPU_IS_UP and ! ARM64.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The bare default entry is wrong. Just remove it since the (real)
entry in drivers/mmc/Kconfig has "default ARM || PPC || SANDBOX".
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Now that the SPL is ready to be compiled in AArch64 and the DRAM
init code is ready, enable SPL support for the A64 SoC and in the
Pine64 defconfig.
For now we keep the boot0 header in the U-Boot proper, as this allows
to still use boot0 as an SPL replacement without hurting the SPL use
case.
We disable FEL support for now by making its compilation conditional
and disabling it for ARM64, as the code isn't ready yet.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jagan Teki <jagan@openedev.com>
To avoid enumerating the very same DRAM values in defconfig files
for each and every Allwinner A64 board out there, let's put some sane
default values in the Kconfig file.
Boards with different needs can override them at any time.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
The Allwinner A64 SoC starts execution in AArch32 mode, and both
the boot ROM and Allwinner's boot0 keep running in this mode.
So U-Boot gets entered in 32-bit, although we want it to run in AArch64.
By using a "magic" instruction, which happens to be an almost-NOP in
AArch64 and a branch in AArch32, we differentiate between being
entered in 64-bit or 32-bit mode.
If in 64-bit mode, we proceed with the branch to reset, but in 32-bit
mode we trigger an RMR write to bring the core into AArch64/EL3 and
re-enter U-Boot at CONFIG_SYS_TEXT_BASE.
This allows a 64-bit U-Boot to be both entered in 32 and 64-bit mode,
so we can use the same start code for the SPL and the U-Boot proper.
We use the existing custom header (boot0.h) functionality, but restrict
the existing boot0 header reservation to the non-SPL build now. A SPL
wouldn't need such header anyway. This allows to have both options
defined and lets us use one for the SPL and the other for U-Boot proper.
Also add arch/arm/mach-sunxi/rmr_switch.S, which contains the original
ARM assembly code and instructions how to re-generate the encoded
version.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
The ENABLE_ARM_SOC_BOOT0_HOOK option is a generic option shared with
other boards. To allow alternative code to be inserted, we create
another, now function specific config symbol on top of it to simplify
later additions. No functional change at this time.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Both the A80 Optimus board and the Cubieboard 4 use a zq value of
4145117, or 0x3f3fdd.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
In Allwinner's SDK the A80 is clocked to 1008 MHz by default.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Now that DRAM initialization and clock setup is supported,
we can enable SPL for the A80.
[wens@csie.org: Added commit message]
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
This adds DRAM initialisation code for sun9i, which calculates the
appropriate timings based on timing information for the supplied
DDR3 bin and the clock speeds used.
With this DRAM setup, we have verified DDR3 clocks of up to 792MHz
(i.e. DDR3-1600) on the A80-Q7 using a dual-channel configuration.
[wens@csie.org: Moved dram_sun9i.c to arch/arm/mach-sunxi/; style cleanup]
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
[hdegoede@redhat.com: Drop some huge non-documenting #if 0 ... #endif blocks]
[hdegoede@redhat.com: Fix checkpatch warnings]
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Move the config IDENT_STRING to Kconfig and migrate all boards
[sivadur: Migrate zynq boards]
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
[trini: Update configs, add some default to sunxi Kconfig]
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini
Jagan Teki
Icenowy Zheng
Vasily Khoruzhick
Maxime Ripard
Simon Glass
Philipp Tomsich
Icenowy Zheng
Andre Przywara
Masahiro Yamada
Jernej Skrabec
Chen-Yu Tsai
Mylène Josserand
Alexandru Gagniuc
Siva Durga Prasad Paladugu