Add at91sam9x5 series spi flash boot support
Using at91sam9x5ek_spiflash to configure, then it can boot from at25df321
serial flash
SPI mater work in 30Mhz speed, while not 1Mhz speed. This will base on
atmel_spi patch, or else, it will occur receive overrun
Signed-off-by: Bo Shen <voice.shen@atmel.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* Move Efika MX Smarttop and Smartbook boards into a "genesi" vendor directory
* Rename efikamx -> mx51_efikamx since there is an mx53_efikamx and mx6_efikamx to come
Signed-off-by: Matt Sealey <matt@genesi-usa.com>
Acked-by: Stefano Babic <sbabic@denx.de>
Acked-by: Stefano Babic <sbabic@denx.de>
Add SPL options to tegra20 config files and enable SPL build for
tegra20 boards. Also remove redundant code from u-boot that is not
contained in SPL.
Signed-off-by: Allen Martin <amartin@nvidia.com>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Tested-by: Thierry Reding <thierry.reding@avionic-design.de>
Signed-off-by: Tom Warren <twarren@nvidia.com>
This is make naming consistent with the kernel and devicetree and in
preparation of pulling out the common tegra20 code.
Signed-off-by: Allen Martin <amartin@nvidia.com>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Tested-by: Thierry Reding <thierry.reding@avionic-design.de>
Signed-off-by: Tom Warren <twarren@nvidia.com>
The Raspberry Pi model B uses the BCM2835 SoC, has 256MB of RAM,
contains an SMSC 9512 USB LAN/Hub chip, and various IO connectors.
For more details, see http://www.raspberrypi.org/.
Various portions (cache enable, MACH_TYPE setup, RAM size limit, stack
relocation to top of RAM) extracted from work by:
Oleksandr Tymoshenko <gonzo@bluezbox.com>.
GPIO driver enablement by Vikram Narayanan <vikram186@gmail.com>.
Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
Acked-by: Tom Rini <trini@ti.com>
Fix build failure due the move of mx28 code to 'mxs' SoC.
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Acked-by: Stefano Babic <sbabic@denx.de>
Most code can be shared between i.MX23 and i.MX28 as both are from
i.MXS family; this source directory structure makes easy to share code
among them.
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Acked-by: Stefano Babic <sbabic@denx.de>
This adds support for Bluegiga APX4 Development Kit. It is built around
Freescale i.MX28. Currently supported features are: ethernet, I2C, MMC,
RTC and USB. APX4 has only one ethernet port.
Signed-off-by: Veli-Pekka Peltola <veli-pekka.peltola@bluegiga.com>
Signed-off-by: Lauri Hintsala <lauri.hintsala@bluegiga.com>
Cc: Stefano Babic <sbabic@denx.de>
This adds support for the AT91SAM9G20 boards by taskit GmbH.
Both boards, Stamp9G20 and PortuxG20, are integrated in one
file. PortuxG20 is basically a SBC built around the Stamp9G20.
Signed-off-by: Markus Hubig <mhubig@imko.de>
Cc: Andreas Bießmann <andreas.devel@googlemail.com>
Signed-off-by: Andreas Bießmann <andreas.deve@googlemail.com>
Add at91sam9x5ek board support, this board support the following SoCs
AT91SAM9G15, AT91SAM9G25, AT91SAM9G35, AT91SAM9X25, AT91SAM9X35
Using at91sam9x5ek_nandflash to configure for the board
Now only supports NAND with software ECC boot up
Signed-off-by: Bo Shen <voice.shen@atmel.com>
[move MAINTAINERS entry to right place]
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
IGEP-based boards can have two different flash memories, a OneNAND or a
NAND device. Add a configuration option for to choose which memory to use.
Signed-off-by: Javier Martinez Canillas <javier@dowhile0.org>
Acked-by: Enric Balletbo i Serra <eballetbo@gmail.com>
This patch adds support for direct NOR boot mode on
da850/omap-l138. Added da850evm_direct_nor entry in
boards.cfg to allow to build targets.
Tested-by: Christian Riesch <christian.riesch@omicron.at>
Signed-off-by: Lad, Prabhakar <prabhakar.lad@ti.com>
Signed-off-by: Rajashekhara, Sudhakar <sudhakar.raj@ti.com>
Signed-off-by: Hadli, Manjunath <manjunath.hadli@ti.com>
Remove old o2dnt board without OF support. New support for this board
is added by the previous patch, O2I configuration.
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Add common code for o2dnt and o2dnt2 based boards and add different
board configuration files for O2D, O2I, O2DNT2, O2D300, O2MNT and
O3DNT boards.
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Add support for specifying a differnt CPU for main u-boot and SPL
u-boot builds. This is done by adding an optional SPL CPU after the
main CPU in boards.cfg as follows:
normal_cpu:spl_cpu
This this case CPU will be set to "normal_cpu" during the main u-boot
build and "spl_cpu" during the SPL build.
Signed-off-by: Allen Martin <amartin@nvidia.com>
Add TLB mappings, board target options, and configuration items
need for SPI/SD boot.
Since P1022DS RevB board, the NOR flash have been changed to 16 bit/28bit
address flash, therefore, when SDHC/ESPI booting and access to eLBC,
the PMUXCR[0~1] must be set to 10b, and PMUXCR[9~10] must be set to
00b for them.
Configure the PX_BRDCFG0[0~1] to 10b which is connected to
SPI devices as SPI_CS(0:3)_B.
Signed-off-by: Matthew McClintock <msm@freescale.com>
Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com>
Signed-off-by: Jiang Yutang <b14898@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Since mgcoge and mgcoge3ne are the only km82xx boards, there is no need
to keep them as separate .h config files.
Therefore, make mgcoge3ne.h and mgcoge.h converge into a single km82xx.h
file.
Signed-off-by: Gerlando Falauto <gerlando.falauto@keymile.com>
* add support for board VL+MA2SC
* adds vl_ma2sc_config for standard NOR boot configuration
* adds vl_ma2sc_ram_config for RAM load configuration
Signed-off-by: Jens Scharsig <esw@bus-elektronik.de>
This patch adds options for all the below mentioned configurations and
subsequently renames the include/configs/spearxxx.h files to spear3xx_evb.h,
spear6xx_evb.h etc to depict evaluation board configuration.
SPEAr3xx and SPEAr6xx boards can be compiled in following configurations
1. Environment placed in NAND
2. Console on usb device
3. Console on usb device with environment placed in NAND
4. SPEAr310 and SPEAr320 support environment variables in parallel
NOR flash.
Signed-off-by: Vipin Kumar <vipin.kumar@st.com>
Signed-off-by: Amit Virdi <amit.virdi@st.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Remove config options from boards.cfg and simply add one switch
per board and differ afterwards in km_kirkwood.h between the features.
More boards are upcoming and therefore it's easier to have this
at one place.
Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
cc: Gerlando Falauto <gerlando.falauto@keymile.com>
cc: Prafulla Wadaskar <prafulla@marvell.com>
This adds a first support of the FPGA download for a PCIe FPGA based
on the BOCO2 CPLD.
This takes place in 3 steps, all done accessing the SPICTRL reg of the
BOCO2:
1) start the FPGA config with an access to the FPGA_PROG bit
2) later in the boot sequence, wait for the FPGA_DONE bit to toggle to 1
for the end of the FPGA configuration (with a timeout)
3) reset the FPGA
4) finally remove the access to its config EEPROM from the FPGA so that
the CPU can update the FPGA configuration when the kernel is running
The boards with a PCIe FPGA but without BOCO2 still are supported.
The config option name is CONFIG_KM_FPGA_CONFIG
Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
cc: Gerlando Falauto <gerlando.falauto@keymile.com>
cc: Prafulla Wadaskar <prafulla@marvell.com>
The additional headerfile is unneeded here, we can use the generic
km_kirkwood.h instead. And we can use the better config option
KM_PIGGY4_88E6061 for the specific features for boards with this
design in km_arm.c.
Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
cc: Gerlando Falauto <gerlando.falauto@keymile.com>
cc: Prafulla Wadaskar <prafulla@marvell.com>
Use the generic header km_kirkwood.h and get rid of the
board specific header.
changes for v2: rebased because of changes in other patches
Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
cc: Gerlando Falauto <gerlando.falauto@keymile.com>
cc: Prafulla Wadaskar <prafulla@marvell.com>
For u-boot this board is similar to mgcoge3un. But some differences
are present. We have a different SDRAM on it and therefore a new
SDRAM config file. Additionaly this board has a direct MAC/MAC
connection from the kirkwood to a marvell simple switch without a
phy inbetween, this needs a new configuration for the mvgbe driver.
Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
cc: Gerlando Falauto <gerlando.falauto@keymile.com>
cc: Prafulla Wadaskar <prafulla@marvell.com>
This board is similar to portl2, but it has the u-boot environment
in a SPI NOR flash and not in an i2c eeprom like portl2 have.
Some other details:
- IVM EEPROM is at adress: pca9547:70:9
- PCI is enabled
- PIGGY4 is connected via MV88E6352 simple switch. There is no phy
between the simple switch and the kirkwood.
Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
cc: Gerlando Falauto <gerlando.falauto@keymile.com>
cc: Prafulla Wadaskar <prafulla@marvell.com>
This patch adds support for both the Linkstation Live (LS-CHLv2) and
Linkstation Pro (LS-XHL) by Buffalo.
Signed-off-by: Michael Walle <michael@walle.cc>
Cc: Prafulla Wadaskar <prafulla@marvell.com>
Some other kirkwood boards from keymile will follow. They will have some
small differences, but we want to use the km_kirkwood.h for all to
distinguish them. This patch a preparation for this.
Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
cc: Gerlando Falauto <gerlando.falauto@keymile.com>
cc: Prafulla Wadaskar <prafulla@marvell.com>
Whistler is a highly configurable Tegra evaluation and development board.
This change adds support for the following specific configuration:
E1120 motherboard
E1108 CPU board
E1116 PMU board
The motherboard configuration switches are set as follows:
SW1=0 SW2=0 SW3=5
S1/S2/S3/S4 all on, except S3 7/8 are off.
Other combinations of daugher boards may work to varying degrees, but will
likely require some SW adjustment.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
BSC9131RDB is a Freescale reference design board for BSC9131 SoC. BSC9131 SOC
is an integrated device that targets Femto base station market. It combines
Power Architecture e500v2 and DSP StarCore SC3850 core technologies with
MAPLE-B2F baseband acceleration processing elements
BSC9131RDB Overview
-----------------
-1Gbyte DDR3 (on board DDR)
-128Mbyte 2K page size NAND Flash
-256 Kbit M24256 I2C EEPROM
-128 Mbit SPI Flash memory
-USB-ULPI
-eTSEC1: Connected to RGMII PHY
-eTSEC2: Connected to RGMII PHY
-DUART interface: supports one UARTs up to 115200 bps for console display
Apart from the above it also consists various peripherals to support DSP
functionalities.
This patch adds support for mainly Power side functionalities and peripherals
Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Signed-off-by: Akhil Goyal <Akhil.Goyal@freescale.com>
Signed-off-by: Rajan Srivastava <rajan.srivastava@freescale.com>
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
This board is a MPC8360 board. Two flashes are present
a NOR flash were u-boot and the u-boot environment is stored
and a NAND flash for the application code. This board has 512MB
SDRAM.
Additionaly we introduce a common km8360.h file and convert kmeter1 to
use this.
Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
Signed-off-by: Christian Herzig <christian.herzig@keymile.com>
cc: Kim Phillips <kim.phillips@freescale.com>
cc: Valentin Longchamp <valentin.longchamp@keymile.com>
cc: Gerlando Falauto <gerlando.falauto@keymile.com>
cc: Heiko Schocher <hs@denx.de>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
This additional header is unneeded, we can use the tuxx1.h for this
target.
Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
cc: Kim Phillips <kim.phillips@freescale.com>
cc: Valentin Longchamp <valentin.longchamp@keymile.com>
cc: Gerlando Falauto <gerlando.falauto@keymile.com>
cc: Heiko Schocher <hs@denx.de>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
This is an sh2a device (max 266MHz) with FPU, video display
controller (VDC), 8 serial ports, 4 I2C channels, 3 CAN ports,
SD and on-chip USB.
The RSK2+SH7269 board uses the SH7269 processor. It is often
referred to as just rsk7269.
Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
The AP-SH4A-4A board has SH7734, 64MB DDR2-SDRAM, USB,
Ethernet, and more.
This patch supports the following functions:
- 64MB DDR2-SDRAM
- 16MB NOR Flash memory
- Serial console (SCIF)
- Ethernet (SH-Ether with Gigabit)
- I2C
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
The r0p7734 board has SH7734, 128MB DDR2-SDRAM, USB,
Ethernet, and more.
This patch supports the following functions:
- 128MB DDR2-SDRAM
- 32MB NOR Flash memory
- Serial console (SCIF)
- Ethernet (SH-Ether/SMSC)
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
The ESG ima3-mx53 board is based on the Freescale
i.MX53 SOC. It boots from NOR (128 MB) and
supports Ethernet (FEC), SATA.
Signed-off-by: Stefano Babic <sbabic@denx.de>
This is rework on config files of IGEP-based boards with the aim to remove
duplicated code to be more maintainable. Basically this patch creates a
common configuration file for both boards and only sets the specific option
in the board config file.
On board files the hardcored mach type was replaced in favour of using the
CONFIG_MACH_TYPE option.
More than 200 duplicated lines have been deleted.
Signed-off-by: Enric Balletbo i Serra <eballetbo@gmail.com>
This change adds a basic support for Embest/Timll DevKit3250 board,
NOR and UART are the only supported peripherals for a moment. The board
doesn't require low-level init, because the initial SDRAM and GPIO
configuration is performed during kickstart bootloader execution.
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Acked-by: Marek Vasut <marek.vasut@gmail.com>
In order to add boards that have different hardware for fpga reset,
any 405ep gdsys board now provides these functions:
void gd405ep_init(void);
void gd405ep_set_fpga_reset(unsigned state);
void gd405ep_setup_hw(void);
int gd405ep_get_fpga_done(unsigned fpga);
Signed-off-by: Dirk Eibach <eibach@gdsys.de>
Cc: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
For the powerpc processors with SRIO interface, boot location can be configured
from SRIO1 or SRIO2 by RCW. The processor booting from SRIO can do without flash
for u-boot image. The image can be fetched from another processor's memory
space by SRIO link connected between them.
The processor boots from SRIO is slave, the processor boots from normal flash
memory space and can help slave to boot from its memory space is master.
They are different environments and requirements:
master:
1. NOR flash for its own u-boot image, ucode and ENV space.
2. Slave's u-boot image in master NOR flash.
3. Normally boot from local NOR flash.
4. Configure SRIO switch system if needed.
slave:
1. Just has EEPROM for RCW. No flash for u-boot image, ucode and ENV.
2. Boot location should be set to SRIO1 or SRIO2 by RCW.
3. RCW should configure the SerDes, SRIO interfaces correctly.
4. Slave must be powered on after master's boot.
5. Must define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE because of no ucode
locally.
For the slave module, need to finish these processes:
1. Set the boot location to SRIO1 or SRIO2 by RCW.
2. Set a specific TLB entry for the boot process.
3. Set a LAW entry with the TargetID SRIO1 or SRIO2 for the boot.
4. Slave's u-boot image should be generated specifically by
make xxxx_SRIOBOOT_SLAVE_config.
This will set SYS_TEXT_BASE=0xFFF80000 and other configurations.
Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
For the powerpc processors with SRIO interface, boot location can be configured
from SRIO1 or SRIO2 by RCW. The processor booting from SRIO can do without flash
for u-boot image. The image can be fetched from another processor's memory
space by SRIO link connected between them.
The processor boots from SRIO is slave, the processor boots from normal flash
memory space and can help slave to boot from its memory space is master.
They are different environments and requirements:
master:
1. NOR flash for its own u-boot image, ucode and ENV space.
2. Slave's u-boot image in master NOR flash.
3. Normally boot from local NOR flash.
4. Configure SRIO switch system if needed.
slave:
1. Just has EEPROM for RCW. No flash for u-boot image, ucode and ENV.
2. Boot location should be set to SRIO1 or SRIO2 by RCW.
3. RCW should configure the SerDes, SRIO interfaces correctly.
4. Slave must be powered on after master's boot.
For the master module, need to finish these processes:
1. Initialize the SRIO port and address space.
2. Set inbound SRIO windows covered slave's u-boot image stored in
master's NOR flash.
3. Master's u-boot image should be generated specifically by
make xxxx_SRIOBOOT_MASTER_config
4. Master must boot first, and then slave can be powered on.
Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
New P2041RDB board will add a NAND chip, so add support for NAND and
NAND boot.
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
board:
Add config file of board adp-ag102
Add adp-ag102 into boards.cfg
Add adp-ag102 into MAINTAINERS
doc:
add README of ag102
Signed-off-by: Macpaul Lin <macpaul@andestech.com>
Bo Shen
Matt Sealey
Allen Martin
Stephen Warren
Mathieu J. Poirier
Otavio Salvador
Marek Vasut
Veli-Pekka Peltola
Markus Hubig
Javier Martinez Canillas
Lad, Prabhakar
Anatolij Gustschin
Jens Scharsig
Matthew McClintock
Gerlando Falauto
Thierry Reding
esw@bus-elektronik.de
Vipin KUMAR
Holger Brunck
Valentin Longchamp
Michael Walle
Stephen Warren
Prabhakar Kushwaha
Phil Edworthy
Nobuhiro Iwamatsu
Stefano Babic
Enric Balletbò i Serra
David Purdy
Luka Perkov
Vladimir Zapolskiy
Dirk Eibach
Liu Gang
Shaohui Xie
Macpaul Lin