The stdio_dev structure has a private pointer for its creator, but it is
not set up by the serial system. Set it to point to the serial device so
that it can be found by code called by stdio.
Signed-off-by: Simon Glass <sjg@chromium.org>
This is an implementation of GPIOs for Tegra that uses driver model. It has
been tested on trimslice and also using the new iotrace feature.
The implementation uses a top-level GPIO device (which has no actual GPIOS).
Under this all the banks are created as separate GPIO devices.
The GPIOs are named as per the Tegra datasheet/header files: A0..A7, B0..B7,
..., Z0..Z7, AA0..AA7, etc.
Since driver model is not yet available before relocation, or in SPL, a
special function is provided for seaboard's SPL code.
Signed-off-by: Simon Glass <sjg@chromium.org>
For some boards board_init() will change GPIOs, so we need to have driver
model available before then. Adjust the board init to arrange this, but
enable it for driver model only, just to be safe.
This does create additional #ifdef logic, but it is safer than trying to
make a pervasive change which may cause some boards to break.
Signed-off-by: Simon Glass <sjg@chromium.org>
Since driver model registers itself with the stdio subsystem, and we
want to avoid delayed registration and other complexity associated with
the current serial console, move the stdio subsystem init earlier when
driver model is used for serial.
This simplifies the implementation. Should there be any problems with
this approach they can be dealt with as boards are converted over to
use driver model for serial.
Signed-off-by: Simon Glass <sjg@chromium.org>
In order to support GPIO access in board_early_init_f() we must set up
driver model before this function is called. In any case, earlier is
better since driver model is (or will become) a key function for most
init.
Signed-off-by: Simon Glass <sjg@chromium.org>
The microblaze-generic board fails to build at least
with the kernel.org crosstool:
https://www.kernel.org/pub/tools/crosstool/files/bin/x86_64/4.9.0/
x86_64-gcc-4.9.0-nolibc_microblaze-linux.tar.xz
$ make CROSS_COMPILE=microblaze-linux- microblaze-generic_defconfig all
[ snip ]
CC disk/part.o
CC disk/part_dos.o
LD disk/built-in.o
CC drivers/block/systemace.o
{standard input}: Assembler messages:
{standard input}:2495: Error: operation combines symbols in different segments
{standard input}:2496: Error: operation combines symbols in different segments
{standard input}:2499: Error: operation combines symbols in different segments
{standard input}:2500: Error: operation combines symbols in different segments
{standard input}:2505: Error: operation combines symbols in different segments
{standard input}:2506: Error: operation combines symbols in different segments
{standard input}:2515: Error: operation combines symbols in different segments
{standard input}:2516: Error: operation combines symbols in different segments
{standard input}:2519: Error: operation combines symbols in different segments
{standard input}:2520: Error: operation combines symbols in different segments
{standard input}:2529: Error: operation combines symbols in different segments
{standard input}:2530: Error: operation combines symbols in different segments
{standard input}:2533: Error: operation combines symbols in different segments
{standard input}:2534: Error: operation combines symbols in different segments
{standard input}:2539: Error: operation combines symbols in different segments
{standard input}:2540: Error: operation combines symbols in different segments
{standard input}:2549: Error: operation combines symbols in different segments
{standard input}:2550: Error: operation combines symbols in different segments
make[3]: *** [drivers/block/systemace.o] Error 1
make[2]: *** [drivers/block] Error 2
make[1]: *** [drivers] Error 2
make: *** [__build_one_by_one] Error 2
It looks like the cause of this error message is the "#ident" directive.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
try run => dry run
no nothing => do nothing
"..." => '...'
The last one is for consistency with the other option helps.
Change-Id: I1d69047d1fae6ef095a18f69f44ee13c448db9b7
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Simon Glass <sjg@chromium.org>
When creating build directories also create parents as necessary. This
fixes a failure when building a hierarchical branch (i.e. foo/bar).
Signed-off-by: Thierry Reding <treding@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Tom Rini <trini@ti.com>
For an occasional user of patman some failures are not obvious: for
instance when checkpatch reports warnings, the dry run still reports
that the email would be sent. If it is not dry run, the warnings are
shown on the screen, but it is not clear that the email was not sent.
Add some code to report failure to send email explicitly.
Tested by running the script on a patch with style violations,
observed error messages in the script output.
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-by: Doug Anderson <dianders@chromium.org>
Acked-by: Simon Glass <sjg@chromium.org>
Tags like Series-version are normally expected to appear once, and with a
unique value. But buildman doesn't actually look at these tags. So ignore
conflicts.
This allows bulidman to build a branch containing multiple patman series.
Reported-by: Steve Rae <srae@broadcom.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
At present buildman naively uses the branch name as part of its directory
path, which causes problems if the name has an embedded '/'.
Replace these with '_' to fix the problem.
Reported-by: Steve Rae <srae@broadcom.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Now that buildman supports removing the build directory prefix from output,
add a test for it. Also ensure that output directories are removed when the
test completes.
Signed-off-by: Simon Glass <sjg@chromium.org>
This adds coverage of core features of the builder, including the
command-line options which affect building.
Signed-off-by: Simon Glass <sjg@chromium.org>
For reasons that are not well-understood, GetMetaDataForList() can end up
adding to an existing series even when it appears that it should be
starting a new one.
Change from using a default constructor parameter to an explicit one, to
work around this problem.
Signed-off-by: Simon Glass <sjg@chromium.org>
For testing it is useful to clean the output directory before running a
test. This avoids a test interfering with the results of a subsequent
test by leaving data around.
Add this feature as an optional parameter to the control logic.
Signed-off-by: Simon Glass <sjg@chromium.org>
When a build is to be performed, buildman checks to see if it has already
been done. In most cases it will not bother trying again. However, it was
not reading the return code from the 'done' file, so if the result was a
failure, it would not be counted. This depresses the 'failure' count stats
that buildman prints in this case.
Fix this bug by always reading the return code.
Signed-off-by: Simon Glass <sjg@chromium.org>
Rather than reading boards.cfg, which may take time to generate and is not
necessarily suitable for running tests, create our own list of boards.
Signed-off-by: Simon Glass <sjg@chromium.org>
These files may not exist in the environment, or may not be suitable for
testing. Provide our own config file and our own toolchains when running
tests.
Signed-off-by: Simon Glass <sjg@chromium.org>
Move the bsettings code back to the main buildman.py file, so we can do
something different when testing.
Signed-off-by: Simon Glass <sjg@chromium.org>
Buildman currently lacks testing in many areas, including its use of git,
make and many command-line flags.
Add a functional test which covers some of these areas. So far it does
a fake 'build' of all boards for the current source tree.
This version reads the real ~/.buildman and boards.cfg files. Future work
will improve this.
Signed-off-by: Simon Glass <sjg@chromium.org>
Add a test point for the command module. This allows tests to emulate
the execution of commands. This provides more control (since we can make
the fake 'commands' do whatever we like), makes it faster to write tests
since we don't need to set up as much environment, and speeds up test
execution.
Signed-off-by: Simon Glass <sjg@chromium.org>
We want to be able to issue parser commands from within buildman for test
purposes. Move the parser code into its own file so we don't end up needing
the buildman and test modules to reference each other.
Signed-off-by: Simon Glass <sjg@chromium.org>
RunPipe() currently pipes the output of stdout and stderr to a pty, but
this is not the intended behaviour. Fix it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Adjust the basic test so that it checks all console output. This will help
to ensure that the builder is behaving correctly with printing summary
information.
Signed-off-by: Simon Glass <sjg@chromium.org>
To allow us to verify the builder's console output, send it through a
function which can collect it when running in test mode.
Signed-off-by: Simon Glass <sjg@chromium.org>
When running unit tests we don't want output to go to the terminal.
Provide a way of collecting it so that it can be examined by test code
later.
Signed-off-by: Simon Glass <sjg@chromium.org>
The basic idea: Define size_t using the __SIZE_TYPE__ compiler-defined
type.
For detailed explanation see similar patch for the nios2 arch:
"nios2: Fix printf size_t format related warnings (again...)"
(sha1: 00a2517fcb)
Signed-off-by: Vasili Galka <vvv444@gmail.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This patch adds the TWR_LCD_RGB card/HDMI options and the common
configuration for DCU on LS1021ATWR board.
Signed-off-by: Alison Wang <alison.wang@freescale.com>
On LS1021ATWR, Silicon's Sii9022A HDMI Transmitter
is used. This patch adds the common setting for this
chip.
Signed-off-by: Alison Wang <alison.wang@freescale.com>
This patch is to add DCU driver support. DCU also named
2D-ACE(Two Dimensional Animation and Compositing Engine)
is a system master that fetches graphics stored in internal
or external memory and displays them on a TFT LCD panel.
Signed-off-by: Alison Wang <alison.wang@freescale.com>
On vybrid, lpuart's registers are 8-bit. On LS102xA, lpuart's registers
are 32-bit. This patch adds the support for 32-bit registers on
LS102xA.
Signed-off-by: Jingchang Lu <jingchang.lu@freescale.com>
Signed-off-by: Yuan Yao <yao.yuan@freescale.com>
Remove the DMCTRL Tx snooping bits (TDSEN and TBDSEN) as a
workaround for LS1. It has been observed that currently
the Tx stops functioning after a fair amount of Tx traffic
with these settings on. These bits are sticky and once set
they cannot be reset from Linux, for instance.
Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com>
LS102xA is an ARMv7 implementation. This patch is to add
basic support for LS1021ATWR board.
One DDR controller
DUART1 is used as the console
For the detail board information, please refer to README.
Signed-off-by: Chen Lu <chen.lu@freescale.com>
Signed-off-by: Yuan Yao <yao.yuan@freescale.com>
Signed-off-by: Alison Wang <alison.wang@freescale.com>
LS102xA is an ARMv7 implementation. This patch is to add
basic support for LS1021AQDS board.
One DDR controller
DUART1 is used as the console
For the detail board information, please refer to README.
Signed-off-by: Alison Wang <alison.wang@freescale.com>
Signed-off-by: Jason Jin <jason.jin@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Yuan Yao <yao.yuan@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
JEDEC spec allows DRAM vendors to use prime DQ for write leveling. This
is not an issue unless some DQ pins are not connected. If a platform uses
regular DIMMs but with reduced DDR ECC pins, the prime DQ may end up on
those floating pins for the second rank. The workaround is to use a known
good chip select for this purpose.
Signed-off-by: York Sun <yorksun@freescale.com>
Reading DDR register should use ddr_in32() for proper endianess.
This patch fixes incorrect waiting time for ARM platforms.
Signed-off-by: York Sun <yorksun@freescale.com>
If less than 8 ECC pins are used for DDR data bus width smaller than 64
bits, the 8-bit ECC code will be transmitted/received across several beats,
and it will be used to check 64-bits of data once 8-bits of ECC are
accumulated.
Signed-off-by: York Sun <yorksun@freescale.com>
For LS1, esdhc is big-endian IP. Accessing the registers
should be in big-endian mode. So we use esdhc_read32()
to read Host controller capabilities register for LS1.
For LS1, when using CMD12, cmdtype need to be set to
ABORT, otherwise, next read command will hang.
Signed-off-by: Alison Wang <alison.wang@freescale.com>
For LS102xA, the processor is in little-endian mode, while esdhc IP is
in big-endian mode. CONFIG_SYS_FSL_ESDHC_LE and CONFIG_SYS_FSL_ESDHC_BE
are added. So accessing ESDHC registers can be determined by ESDHC IP's
endian mode.
Signed-off-by: Alison Wang <alison.wang@freescale.com>
This patch is to add etsec support for LS102xA. First, Little-endian
descriptor mode should be enabled. So RxBDs and TxBDs are interpreted
with little-endian byte ordering. Second, TSEC_SIZE and TSEC_MDIO_OFFSET
are different from PowerPC, redefine them for LS1021xA.
Signed-off-by: Alison Wang <alison.wang@freescale.com>
fsl_enet.h defines the mapping of the usual MII management
registers, which are included in the MDIO register block
common to Freescale ethernet controllers. So it shouldn't
depend on the CPU architecture but it should be actually
part of the arch independent fsl_mdio.h.
To remove the arch dependency, merge the content of
asm/fsl_enet.h into fsl_mdio.h.
Some files (like fm_eth.h) were simply including fsl_enet.h
only for phy.h. These were updated to include phy.h instead.
Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com>
The existing i.MX's I2C driver mxc_i2c.c is compatible
with the controller of LS102xA. As I2C's registers
are 8-bit on LS102xA, I2C_QUIRK_REG is enabled to
use 8-bit driver.
This patch is to add I2C 1,2,3 support for LS102xA.
Signed-off-by: Alison Wang <alison.wang@freescale.com>
The QorIQ LS1 family is built on Layerscape architecture,
the industry's first software-aware, core-agnostic networking
architecture to offer unprecedented efficiency and scale.
Freescale LS102xA is a set of SoCs combines two ARM
Cortex-A7 cores that have been optimized for high
reliability and pack the highest level of integration
available for sub-3 W embedded communications processors
with Layerscape architecture and with a comprehensive
enablement model focused on ease of programmability.
Signed-off-by: Alison Wang <alison.wang@freescale.com>
Signed-off-by: Jason Jin <jason.jin@freescale.com>
Signed-off-by: Jingchang Lu <jingchang.lu@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Simon Glass
Tom Rini
Masahiro Yamada
Thierry Reding
Vadim Bendebury
Vasili Galka
Wang Huan
Jingchang Lu
Claudiu Manoil
York Sun