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upstream u-boot with additional patches for our devices/boards: https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ; Gbit ethernet patch for some LIME2 revisions ; with SPI flash support
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u-boot/board/jse
History
Wolfgang Denk c8a3b109f0
Cleanup out-or-tree building for some boards (.depend) 		17 years ago
..
Makefile Cleanup out-or-tree building for some boards (.depend) 17 years ago
README.txt * Patch by Stephen Williams, 01 Apr 2004: 21 years ago
config.mk * Patch by Stephen Williams, 01 Apr 2004: 21 years ago
flash.c Patch by Stephen Williams, 11 May 2004: 21 years ago
host_bridge.c * Code cleanup, mostly for GCC-3.3.x 20 years ago
init.S ppc4xx: Remove superfluous dram_init() call or replace it by initdram() 17 years ago
jse.c * Patch by Stephen Williams, 01 Apr 2004: 21 years ago
jse_priv.h * Patch by Stephen Williams, 01 Apr 2004: 21 years ago
sdram.c Change initdram() return type to phys_size_t 17 years ago
u-boot.lds Big white-space cleanup. 17 years ago

README.txt 

JSE Configuration Details

Memory Bank 0 -- Flash chip
---------------------------

0xfff00000 - 0xffffffff

The flash chip is really only 512Kbytes, but the high address bit of
the 1Meg region is ignored, so the flash is replicated through the
region. Thus, this is consistent with a flash base address 0xfff80000.

The placement at the end is to be consistent with reset behavior,
where the processor itself initially uses this bus to load the branch
vector and start running.

On-Chip Memory
--------------

0xf4000000 - 0xf4000fff

The 405GPr includes a 4K on-chip memory that can be placed however
software chooses. I choose to place the memory at this address, to
keep it out of the cachable areas.


Memory Bank 1 -- SystemACE Controller
-------------------------------------

0xf0000000 - 0xf00fffff

The SystemACE chip is along on peripheral bank CS#1. We don't need
much space, but 1Meg is the smallest we can configure the chip to
allocate. We need it far away from the flash region, because this
region is set to be non-cached.


Internal Peripherals
--------------------

0xef600300 - 0xef6008ff

These are scattered various peripherals internal to the PPC405GPr
chip.

SDRAM
-----

0x00000000 - 0x07ffffff  (128 MBytes)