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upstream u-boot with additional patches for our devices/boards: https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ; Gbit ethernet patch for some LIME2 revisions ; with SPI flash support
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u-boot/arch/arm/cpu/armv8/fsl-lsch3
History
York Sun 207774b213
armv8/ls2085a: Fix generic timer clock source 		9 years ago
..
Makefile armv8/fsl-lsch3: Release secondary cores from boot hold off with Boot Page 10 years ago
README fsl-ch3/README: Add description for NOR flash layout (firmware images) 9 years ago
cpu.c armv8/ls2085a: Fix generic timer clock source 9 years ago
cpu.h armv8/fsl-lsch3: Release secondary cores from boot hold off with Boot Page 10 years ago
fdt.c armv8/fsl-lsch3: Add fdt-fixup for clock frequency of the DUART nodes 9 years ago
lowlevel.S armv8/ls2085a: Fix generic timer clock source 9 years ago
mp.c armv8/ls2085a: Fix generic timer clock source 9 years ago
mp.h armv8/ls2085a: Fix generic timer clock source 9 years ago
speed.c armv8/fsl-lsch3: Fix platform clock calculation 9 years ago
speed.h
…

README 

#
# Copyright 2014 Freescale Semiconductor
#
# SPDX-License-Identifier:      GPL-2.0+
#

Freescale LayerScape with Chassis Generation 3

This architecture supports Freescale ARMv8 SoCs with Chassis generation 3,
for example LS2085A.

Flash Layout
============
A typical layout of various images (including Linux and other firmware images)
is shown below considering a 32MB NOR flash device:

	-------------------------
	|	linux		|
	------------------------- ----> 0x0120_0000
	|	Debug Server 	|
	------------------------- ----> 0x00C0_0000
	|	AIOP SW 	|
	------------------------- ----> 0x0070_0000
	|	MC FW 		|
	------------------------- ----> 0x006C_0000
	| MC Data Path Layout 	|
	------------------------- ----> 0x0020_0000
	|	BootLoader 	|
	------------------------- ----> 0x0000_1000
	|	PBI 		|
	------------------------- ----> 0x0000_0080
	|	RCW 		|
	------------------------- ----> 0x0000_0000

	32-MB NOR flash layout