upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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309 lines
12 KiB
309 lines
12 KiB
/*
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* (C) Copyright 2005-2007
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* Stefan Roese, DENX Software Engineering, sr@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/************************************************************************
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* bamboo.h - configuration for BAMBOO board
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***********************************************************************/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*-----------------------------------------------------------------------
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* High Level Configuration Options
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*----------------------------------------------------------------------*/
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#define CONFIG_BAMBOO 1 /* Board is BAMBOO */
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#define CONFIG_440EP 1 /* Specific PPC440EP support */
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#define CONFIG_440 1 /* ... PPC440 family */
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#define CONFIG_4xx 1 /* ... PPC4xx family */
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#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
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/*
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* Include common defines/options for all AMCC eval boards
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*/
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#define CONFIG_HOSTNAME bamboo
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#include "amcc-common.h"
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#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
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/*
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* Please note that, if NAND support is enabled, the 2nd ethernet port
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* can't be used because of pin multiplexing. So, if you want to use the
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* 2nd ethernet port you have to "undef" the following define.
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*/
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#define CONFIG_BAMBOO_NAND 1 /* enable nand flash support */
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/*-----------------------------------------------------------------------
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* Base addresses -- Note these are effective addresses where the
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* actual resources get mapped (not physical addresses)
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*----------------------------------------------------------------------*/
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#define CONFIG_SYS_FLASH_BASE 0xfff00000 /* start of FLASH */
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#define CONFIG_SYS_PCI_MEMBASE 0xa0000000 /* mapped pci memory*/
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#define CONFIG_SYS_PCI_MEMBASE1 CONFIG_SYS_PCI_MEMBASE + 0x10000000
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#define CONFIG_SYS_PCI_MEMBASE2 CONFIG_SYS_PCI_MEMBASE1 + 0x10000000
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#define CONFIG_SYS_PCI_MEMBASE3 CONFIG_SYS_PCI_MEMBASE2 + 0x10000000
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/*Don't change either of these*/
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#define CONFIG_SYS_PERIPHERAL_BASE 0xef600000 /* internal peripherals*/
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#define CONFIG_SYS_PCI_BASE 0xe0000000 /* internal PCI regs*/
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/*Don't change either of these*/
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#define CONFIG_SYS_USB_DEVICE 0x50000000
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#define CONFIG_SYS_NVRAM_BASE_ADDR 0x80000000
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#define CONFIG_SYS_BOOT_BASE_ADDR 0xf0000000
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#define CONFIG_SYS_NAND_ADDR 0x90000000
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#define CONFIG_SYS_NAND2_ADDR 0x94000000
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/*-----------------------------------------------------------------------
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* Initial RAM & stack pointer (placed in SDRAM)
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*----------------------------------------------------------------------*/
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#define CONFIG_SYS_INIT_RAM_DCACHE 1 /* d-cache as init ram */
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#define CONFIG_SYS_INIT_RAM_ADDR 0x70000000 /* DCache */
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#define CONFIG_SYS_INIT_RAM_END (4 << 10)
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#define CONFIG_SYS_GBL_DATA_SIZE 256 /* num bytes initial data */
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#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
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#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
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/*-----------------------------------------------------------------------
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* Serial Port
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*----------------------------------------------------------------------*/
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#define CONFIG_SYS_EXT_SERIAL_CLOCK 11059200 /* use external 11.059MHz clk */
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/* define this if you want console on UART1 */
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#undef CONFIG_UART1_CONSOLE
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/*-----------------------------------------------------------------------
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* NVRAM/RTC
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*
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* NOTE: The RTC registers are located at 0x7FFF0 - 0x7FFFF
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* The DS1558 code assumes this condition
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*
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*----------------------------------------------------------------------*/
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#define CONFIG_SYS_NVRAM_SIZE (0x2000 - 0x10) /* NVRAM size(8k)- RTC regs */
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#define CONFIG_RTC_DS1556 1 /* DS1556 RTC */
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/*-----------------------------------------------------------------------
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* Environment
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*----------------------------------------------------------------------*/
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#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
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#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
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#else
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#define CONFIG_ENV_IS_IN_NAND 1 /* use NAND for environment vars */
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#define CONFIG_ENV_IS_EMBEDDED 1 /* use embedded environment */
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#endif
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/*-----------------------------------------------------------------------
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* FLASH related
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*----------------------------------------------------------------------*/
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#define CONFIG_SYS_MAX_FLASH_BANKS 3 /* number of banks */
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#define CONFIG_SYS_MAX_FLASH_SECT 256 /* sectors per device */
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#undef CONFIG_SYS_FLASH_CHECKSUM
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#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
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#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
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#define CONFIG_SYS_FLASH_ADDR0 0x555
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#define CONFIG_SYS_FLASH_ADDR1 0x2aa
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#define CONFIG_SYS_FLASH_WORD_SIZE unsigned char
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#define CONFIG_SYS_FLASH_2ND_16BIT_DEV 1 /* bamboo has 8 and 16bit device */
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#define CONFIG_SYS_FLASH_2ND_ADDR 0x87800000 /* bamboo has 8 and 16bit device */
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#ifdef CONFIG_ENV_IS_IN_FLASH
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#define CONFIG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
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#define CONFIG_ENV_ADDR ((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
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#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
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/* Address and size of Redundant Environment Sector */
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#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
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#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
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#endif /* CONFIG_ENV_IS_IN_FLASH */
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/*
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* IPL (Initial Program Loader, integrated inside CPU)
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* Will load first 4k from NAND (SPL) into cache and execute it from there.
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*
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* SPL (Secondary Program Loader)
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* Will load special U-Boot version (NUB) from NAND and execute it. This SPL
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* has to fit into 4kByte. It sets up the CPU and configures the SDRAM
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* controller and the NAND controller so that the special U-Boot image can be
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* loaded from NAND to SDRAM.
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*
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* NUB (NAND U-Boot)
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* This NAND U-Boot (NUB) is a special U-Boot version which can be started
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* from RAM. Therefore it mustn't (re-)configure the SDRAM controller.
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*
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* On 440EPx the SPL is copied to SDRAM before the NAND controller is
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* set up. While still running from cache, I experienced problems accessing
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* the NAND controller. sr - 2006-08-25
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*/
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#define CONFIG_SYS_NAND_BOOT_SPL_SRC 0xfffff000 /* SPL location */
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#define CONFIG_SYS_NAND_BOOT_SPL_SIZE (4 << 10) /* SPL size */
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#define CONFIG_SYS_NAND_BOOT_SPL_DST 0x00800000 /* Copy SPL here */
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#define CONFIG_SYS_NAND_U_BOOT_DST 0x01000000 /* Load NUB to this addr */
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#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST /* Start NUB from this addr */
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#define CONFIG_SYS_NAND_BOOT_SPL_DELTA (CONFIG_SYS_NAND_BOOT_SPL_SRC - CONFIG_SYS_NAND_BOOT_SPL_DST)
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/*
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* Define the partitioning of the NAND chip (only RAM U-Boot is needed here)
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*/
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#define CONFIG_SYS_NAND_U_BOOT_OFFS (16 << 10) /* Offset to RAM U-Boot image */
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#define CONFIG_SYS_NAND_U_BOOT_SIZE (384 << 10) /* Size of RAM U-Boot image */
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/*
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* Now the NAND chip has to be defined (no autodetection used!)
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*/
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#define CONFIG_SYS_NAND_PAGE_SIZE 512 /* NAND chip page size */
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#define CONFIG_SYS_NAND_BLOCK_SIZE (16 << 10) /* NAND chip block size */
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#define CONFIG_SYS_NAND_PAGE_COUNT 32 /* NAND chip page count */
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#define CONFIG_SYS_NAND_BAD_BLOCK_POS 5 /* Location of bad block marker */
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#define CONFIG_SYS_NAND_4_ADDR_CYCLE 1 /* Fourth addr used (>32MB) */
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#define CONFIG_SYS_NAND_ECCSIZE 256
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#define CONFIG_SYS_NAND_ECCBYTES 3
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#define CONFIG_SYS_NAND_ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / CONFIG_SYS_NAND_ECCSIZE)
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#define CONFIG_SYS_NAND_OOBSIZE 16
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#define CONFIG_SYS_NAND_ECCTOTAL (CONFIG_SYS_NAND_ECCBYTES * CONFIG_SYS_NAND_ECCSTEPS)
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#define CONFIG_SYS_NAND_ECCPOS {0, 1, 2, 3, 6, 7}
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#ifdef CONFIG_ENV_IS_IN_NAND
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/*
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* For NAND booting the environment is embedded in the U-Boot image. Please take
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* look at the file board/amcc/sequoia/u-boot-nand.lds for details.
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*/
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#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
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#define CONFIG_ENV_OFFSET (CONFIG_SYS_NAND_U_BOOT_OFFS + CONFIG_ENV_SIZE)
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#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
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#endif
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/*-----------------------------------------------------------------------
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* NAND FLASH
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*----------------------------------------------------------------------*/
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#define CONFIG_SYS_MAX_NAND_DEVICE 2
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#define NAND_MAX_CHIPS CONFIG_SYS_MAX_NAND_DEVICE
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#define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_ADDR + CONFIG_SYS_NAND_CS)
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#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_ADDR + 2 }
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#define CONFIG_SYS_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */
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#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
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#define CONFIG_SYS_NAND_CS 1
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#else
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#define CONFIG_SYS_NAND_CS 0 /* NAND chip connected to CSx */
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/* Memory Bank 0 (NAND-FLASH) initialization */
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#define CONFIG_SYS_EBC_PB0AP 0x018003c0
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#define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_NAND_ADDR | 0x1c000)
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#endif
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/*-----------------------------------------------------------------------
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* DDR SDRAM
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*----------------------------------------------------------------------------- */
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#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for setup */
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#undef CONFIG_DDR_ECC /* don't use ECC */
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#define CONFIG_SYS_SIMULATE_SPD_EEPROM 0xff /* simulate spd eeprom on this address */
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#define SPD_EEPROM_ADDRESS {CONFIG_SYS_SIMULATE_SPD_EEPROM, 0x50, 0x51}
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#define CONFIG_SYS_MBYTES_SDRAM (64) /* 64MB fixed size for early-sdram-init */
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#define CONFIG_PROG_SDRAM_TLB
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/*-----------------------------------------------------------------------
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* I2C
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*----------------------------------------------------------------------*/
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#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
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#define CONFIG_SYS_I2C_MULTI_EEPROMS
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#define CONFIG_SYS_I2C_EEPROM_ADDR (0xa8>>1)
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#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
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#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
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#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
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#ifdef CONFIG_ENV_IS_IN_EEPROM
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#define CONFIG_ENV_SIZE 0x200 /* Size of Environment vars */
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#define CONFIG_ENV_OFFSET 0x0
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#endif /* CONFIG_ENV_IS_IN_EEPROM */
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/*
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* Default environment variables
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*/
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#define CONFIG_EXTRA_ENV_SETTINGS \
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CONFIG_AMCC_DEF_ENV \
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CONFIG_AMCC_DEF_ENV_POWERPC \
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CONFIG_AMCC_DEF_ENV_PPC_OLD \
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CONFIG_AMCC_DEF_ENV_NOR_UPD \
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CONFIG_AMCC_DEF_ENV_NAND_UPD \
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"kernel_addr=fff00000\0" \
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"ramdisk_addr=fff10000\0" \
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""
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#define CONFIG_HAS_ETH0
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#define CONFIG_PHY_ADDR 0 /* PHY address, See schematics */
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#define CONFIG_PHY1_ADDR 1
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#ifndef CONFIG_BAMBOO_NAND
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#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
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#endif /* CONFIG_BAMBOO_NAND */
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#ifdef CONFIG_440EP
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/* USB */
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#define CONFIG_USB_OHCI
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#define CONFIG_USB_STORAGE
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/*Comment this out to enable USB 1.1 device*/
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#define USB_2_0_DEVICE
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#endif /*CONFIG_440EP*/
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/*
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* Commands additional to the ones defined in amcc-common.h
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*/
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#define CONFIG_CMD_DATE
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#define CONFIG_CMD_EXT2
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#define CONFIG_CMD_FAT
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#define CONFIG_CMD_PCI
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#define CONFIG_CMD_SDRAM
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#define CONFIG_CMD_SNTP
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#define CONFIG_CMD_USB
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#ifdef CONFIG_BAMBOO_NAND
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#define CONFIG_CMD_NAND
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#endif
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#define CONFIG_SUPPORT_VFAT
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/* Partitions */
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#define CONFIG_MAC_PARTITION
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#define CONFIG_DOS_PARTITION
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#define CONFIG_ISO_PARTITION
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/*-----------------------------------------------------------------------
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* PCI stuff
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*-----------------------------------------------------------------------
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*/
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/* General PCI */
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#define CONFIG_PCI /* include pci support */
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#undef CONFIG_PCI_PNP /* do (not) pci plug-and-play */
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#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
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#define CONFIG_SYS_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE*/
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/* Board-specific PCI */
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#define CONFIG_SYS_PCI_TARGET_INIT
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#define CONFIG_SYS_PCI_MASTER_INIT
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#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
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#define CONFIG_SYS_PCI_SUBSYS_ID 0xcafe /* Whatever */
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#endif /* __CONFIG_H */
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