upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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94 lines
3.0 KiB
94 lines
3.0 KiB
/*
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* Clock Initialization for board based on EXYNOS4210
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*
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* Copyright (C) 2013 Samsung Electronics
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* Rajeshwari Shinde <rajeshwari.s@samsung.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <config.h>
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#include <asm/io.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/clk.h>
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#include <asm/arch/clock.h>
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#include "common_setup.h"
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#include "exynos4_setup.h"
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/*
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* system_clock_init: Initialize core clock and bus clock.
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* void system_clock_init(void)
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*/
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void system_clock_init(void)
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{
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struct exynos4_clock *clk =
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(struct exynos4_clock *)samsung_get_base_clock();
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writel(CLK_SRC_CPU_VAL, &clk->src_cpu);
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sdelay(0x10000);
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writel(CLK_SRC_TOP0_VAL, &clk->src_top0);
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writel(CLK_SRC_TOP1_VAL, &clk->src_top1);
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writel(CLK_SRC_DMC_VAL, &clk->src_dmc);
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writel(CLK_SRC_LEFTBUS_VAL, &clk->src_leftbus);
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writel(CLK_SRC_RIGHTBUS_VAL, &clk->src_rightbus);
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writel(CLK_SRC_FSYS_VAL, &clk->src_fsys);
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writel(CLK_SRC_PERIL0_VAL, &clk->src_peril0);
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writel(CLK_SRC_CAM_VAL, &clk->src_cam);
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writel(CLK_SRC_MFC_VAL, &clk->src_mfc);
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writel(CLK_SRC_G3D_VAL, &clk->src_g3d);
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writel(CLK_SRC_LCD0_VAL, &clk->src_lcd0);
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sdelay(0x10000);
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writel(CLK_DIV_CPU0_VAL, &clk->div_cpu0);
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writel(CLK_DIV_CPU1_VAL, &clk->div_cpu1);
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writel(CLK_DIV_DMC0_VAL, &clk->div_dmc0);
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writel(CLK_DIV_DMC1_VAL, &clk->div_dmc1);
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writel(CLK_DIV_LEFTBUS_VAL, &clk->div_leftbus);
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writel(CLK_DIV_RIGHTBUS_VAL, &clk->div_rightbus);
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writel(CLK_DIV_TOP_VAL, &clk->div_top);
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writel(CLK_DIV_FSYS1_VAL, &clk->div_fsys1);
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writel(CLK_DIV_FSYS2_VAL, &clk->div_fsys2);
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writel(CLK_DIV_FSYS3_VAL, &clk->div_fsys3);
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writel(CLK_DIV_PERIL0_VAL, &clk->div_peril0);
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writel(CLK_DIV_CAM_VAL, &clk->div_cam);
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writel(CLK_DIV_MFC_VAL, &clk->div_mfc);
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writel(CLK_DIV_G3D_VAL, &clk->div_g3d);
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writel(CLK_DIV_LCD0_VAL, &clk->div_lcd0);
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/* Set PLL locktime */
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writel(PLL_LOCKTIME, &clk->apll_lock);
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writel(PLL_LOCKTIME, &clk->mpll_lock);
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writel(PLL_LOCKTIME, &clk->epll_lock);
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writel(PLL_LOCKTIME, &clk->vpll_lock);
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writel(APLL_CON1_VAL, &clk->apll_con1);
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writel(APLL_CON0_VAL, &clk->apll_con0);
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writel(MPLL_CON1_VAL, &clk->mpll_con1);
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writel(MPLL_CON0_VAL, &clk->mpll_con0);
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writel(EPLL_CON1_VAL, &clk->epll_con1);
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writel(EPLL_CON0_VAL, &clk->epll_con0);
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writel(VPLL_CON1_VAL, &clk->vpll_con1);
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writel(VPLL_CON0_VAL, &clk->vpll_con0);
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sdelay(0x30000);
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}
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