upstream u-boot with additional patches for our devices/boards: https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ; Gbit ethernet patch for some LIME2 revisions ; with SPI flash support

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Ajay Kumar 6102560891 Exynos5: Fix rpll_sdiv to support both peach-pit and peach-pi panels ... The existing setting for rpll_sdiv generates 70.5Mhz RPLL video clock to drive 1366x768 panel on peach_pit. This clock rate is not sufficient to drive 1920x1080 panel on peach-pi. So, we adjust rpll_sdiv to 3 so that it generates 141Mhz pixel clock which can drive peach-pi LCD. This change doesn't break peach-pit LCD since 141/2=70.5Mhz, i.e FIMD divider at IP level will get set to 1(the required divider setting will be calculated and set by exynos_fimd_set_clock()) and hence peach-pit LCD still works fine. Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>		10 years ago
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Kconfig	malloc_f: enable SYS_MALLOC_F by default if DM is on	10 years ago
Makefile	…
clock.c	arm: exynos: add display clocks for Exynos5800	10 years ago
clock_init.h	…
clock_init_exynos4.c	remove unnecessary version.h includes	10 years ago
clock_init_exynos5.c	Exynos5: Fix rpll_sdiv to support both peach-pit and peach-pi panels	10 years ago
common_setup.h	…
config.mk	…
dmc_common.c	…
dmc_init_ddr3.c	…
dmc_init_exynos4.c	…
exynos4_setup.h	remove unnecessary version.h includes	10 years ago
exynos5_setup.h	…
lowlevel_init.c	…
pinmux.c	…
power.c	…
sec_boot.S	…
soc.c	…
spl_boot.c	…
system.c	…
tzpc.c	…